CN103456706B - 分立半导体器件封装和制造方法 - Google Patents

分立半导体器件封装和制造方法 Download PDF

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Publication number
CN103456706B
CN103456706B CN201310205500.4A CN201310205500A CN103456706B CN 103456706 B CN103456706 B CN 103456706B CN 201310205500 A CN201310205500 A CN 201310205500A CN 103456706 B CN103456706 B CN 103456706B
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discrete
semiconductor device
electric conductor
encapsulation
wafer
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CN103456706A (zh
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提姆·伯切尔
斯文·沃尔兹克
洛尔夫·格罗恩休斯
洛尔夫·布莱纳
艾米勒·德·布鲁因
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Yasuyo Co. Ltd.
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Naizhiya Co Ltd
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Abstract

公开了一种分立半导体器件封装(100)，包括：半导体管芯(110)，具有第一表面以及与所述第一表面相对且承载触点(112)的第二表面；所述触点上的导电体(120)；密封材料(130)，横向地密封所述导电体；以及与导电体导电接触的封盖部件(140，610)，例如焊接帽、另一半导体管芯或者其组合，所述焊接帽在密封材料上延伸。可以将另一焊接帽(150)设置在第一表面上。也公开了一种制造这种分立半导体器件封装的方法。

Description

分立半导体器件封装和制造方法
技术领域
本发明涉及一种分立半导体器件封装。
本发明还涉及一种对诸如二极管之类的分立半导体器件进行封装的方法。
背景技术
在销售时，诸如二极管之类的分立半导体器件典型地设置在封装中。封装保护分立半导体器件免受意外损坏，并且提供用于将分立半导体器件集成到更大电子设备中的触点，例如通过将分立半导体器件安装到诸如印刷电路板(PCB)之类的载体上。在已知的封装方法中，封装触点典型地是分立半导体器件的触点的散开输出端(fan-out)，即具有较大的面积，因为按照直接且成本有效的方式在封装层面再现小尺寸的分立半导体器件的制造方法当前不是可用的。
由于包括分立半导体器件在内的半导体器件正在微型化，必须对相应的封装尺寸微型化。然而，这并不是轻而易举的，因为封装触点的散开输出端造成了封装尺寸的下限。例如，对于二极管封装，难以将封装微型化超过0.6mm×0.3mm×0.3mm的尺寸。这种封装也称作0603封装。
通常使用引线框封装设计来制造这种分立半导体封装，其中从半导体管芯或晶体到载体触点的连接经由引线键合(wire bond)来提供。然而，超过0603封装尺寸的微型化使得应用引线键合是麻烦且耗时的，从而使得这种连接的使用实际上不能实现。
发明内容
本发明旨在提供一种分立半导体封装，所述分立半导体封装避免了在将封装安装到诸如PCB之类的载体上时使用引线键合的需要。
本发明还旨在提供一种封装方法，所述封装方法便于将分立半导体器件封装(具体地，二极管封装)进一步微型化。
根据本发明的第一方面，提出了一种分立半导体器件封装，包括：半导体管芯，具有第一表面以及与所述第一表面相反且承载触点的第二表面；所述触点上的导电体；密封材料，横向地密封所述导电体；以及与导电体导电接触的封盖部件，所述封盖部件在所述密封材料上延伸。
导电体典型地包括在将封装安装到诸如印刷电路板之类的载体上时的温度下保持固态的材料。例如，在超过280℃的温度下熔化的焊料或者诸如Au、Ni和/或Cu之类的合适金属可以用于金属体。
在实施例中，封盖部件可以是焊接帽。优选地，分立半导体器件还包括与第一表面导电接触的另一焊接帽。
在替代实施例中，封盖部件可以是另一半导体管芯，以进一步增加分立半导体封装的鲁棒性。例如，所述另一管芯可以是另一半导体器件以提供背靠背二极管功能，或者在局限于仅单独器件的封装的情况下代替地可以是虚拟管芯。在该实施例中，半导体管芯的相应底部表面可以用作帽，即，针对用于将封装安装到载体上的焊料的接触表面。如果所述管芯和所述另一管芯包括可焊背部金属叠层，在所述可焊背部金属叠层上可以直接涂覆载体焊料，则这是特别切实可行的。
为了改进这种封装的可焊接性，可以将封盖层设置在相应的底部表面上。
这种封装的优势在于可以在批量工艺中制造并且可以侧向放置在载体上，使得第一表面和第二表面从载体表面垂直地延伸。这允许使用从载体表面延伸至第一表面(上的焊接帽)和第二表面的触点上的密封焊料部分之上的焊接帽的焊接材料来将所述封装电连接至载体，从而避免了键合引线的使用。
导电体可以采取球的形式，或者替代地可以具有柱形形状，例如焊料球或柱、金属球或柱等。
在实施例中，密封材料沿将第一表面和第二表面相连的半导体管芯的相应侧面延伸。这具有向分立半导体器件提供另外的保护以抵抗意外损坏的优点。
根据本发明的另一个方面，提出了一种载体，包括第一载体触点和第二载体触点，所述载体还包括根据本发明实施例的分立半导体器件封装，其中通过相应的另外焊接部分将所述第一载体触点导电连接至第一表面并且将所述第二载体触点导电连接至导电体。如前所述，这种载体具有避免使用键合引线的优势，从而可以更加易于(即更加节省成本地)制造这种载体。
根据本发明的再一个方面，提出了一种制造分立半导体封装的方法，包括：提供晶片，所述晶片包括多个分立半导体器件，每一个所述分立半导体器件具有第一表面以及与所述第一表面相对且承载触点的第二表面；在每一个所述触点上形成相应的导电体；用密封材料至少覆盖承载导电体的晶片表面；分割分立半导体器件；以及至少在每一个所述分立半导体器件的导电体上设置封盖部件。可以通过对晶片切片或等离子体刻蚀执分割步骤，以提供分立半导体器件，并且可以在施加封盖部件之前或之后执行分割步骤。这允许在批量工艺中制造多个分立半导体器件，其中向多个分立半导体器件同时施加每一工艺步骤，从而提供了成本有效的制造方法和无需键合引线就能安装到载体上的半导体器件封装。
在实施例中，该方法还包括：在所述分割步骤之前，对包括分立半导体器件的相应第一表面在内的晶片表面进行减薄。这具有以下优势：由于减小了晶片破裂的风险，改善了在减薄步骤之前的制造工艺的鲁棒性。
在实施例中，封盖部件是与包括多个所述管芯在内的半导体晶片不同的另一半导体管芯。这在封装要求背靠背功能(例如背靠背二极管功能)的情况下是有利的，并且可以在下述封装工艺中是有利的：在所述封装工艺中，因为该实施例允许使用较小的导电体，例如较小的焊料或金属球或凸块，柱形导电体是不可用的。在替代实施例中，在对于只包括单一有源器件的封装需要使用较小的凸块或球的情况下，所述另一晶片包括多个虚拟管芯。在将另一半导体管芯用作封盖部件的情况下，可以在设置封盖部件之后执行分割步骤。
在另一个实施例中，设置封盖部件的步骤包括至少在导电体上设置焊接帽。优选地，该方法还包括在每一个分立半导体器件的第一表面上设置另一焊接帽。将要焊接的表面上存在焊接帽改进了所述表面与焊接材料的亲合力，从而改进了焊料与半导体器件封装触点的粘附性。在使用另一半导体管芯作为封盖部件的情况下，也可以将焊接帽设置在另一半导体管芯上。
在实施例中，该方法还包括：在所述覆盖步骤之前，部分地分割分立半导体器件，从而暴露将第一表面和第二表面相连的每一个分立半导体器件的侧面；以及其中所述覆盖步骤还包括用密封材料覆盖所述侧面。这具有以下优势：利用密封材料也保护了分立半导体封装的侧面。
为此目的，该方法可以包括：在所述部分分割步骤之前，将晶片放置于切割箔上；以及在所述部分分割步骤之后拉伸所述切割箔，以暴露出分立半导体器件的相应侧面。
替代地，该方法可以包括用具有第一厚度的切割刀片切割晶片，其中所述分割步骤包括用具有比第一厚度小的第二厚度的切割刀片切割密封的晶片。
附图说明
参考附图并且通过非限制示例更加详细地描述本发明的实施例，其中：
图1示意性地示出了根据本发明实施例的分立半导体器件封装；
图2示意性地示出了根据本发明另一实施例的分立半导体器件封装；
图3示意性地示出了根据本发明实施例的包括分立半导体器件封装的载体；
图4示意性地示出了根据本发明实施例的制造分立半导体器件封装的方法的各步骤；
图5示意性地示出了根据本发明另一实施例的制造分立半导体器件封装的方法的各步骤；以及
图6示意性地示出了根据本发明再一实施例的制造分立半导体器件封装的方法的各步骤。
具体实施方式
应该理解，附图只是示意性的并且没有按比例绘制。还应该理解，贯穿附图使用相同的附图标记来表示相同或类似的部分。
图1示意性地示出了本发明的分立半导体器件封装100的第一实施例。垂直半导体器件(例如垂直二极管)的半导体管芯110(例如，单晶或多晶硅管芯)承载管芯触点112，在管芯触点112上形成有导电体120，导电体120在该示例中是具有足够高熔点(例如大于280℃)的焊料或金属球。可以按照任意合适的方式形成这种导电体120，例如通过沉积焊料、例如通过引线键合涂覆金或铜球、在电镀槽中涂覆Ni触点、在电镀槽中生长铜柱等。导电体还可以包括可焊镀层，例如Sn镀层或具有足够高熔点的镀层，以改进导电体120的可焊接性。
管芯触点112可以是任意合适的导电材料，例如诸如铜、铝之类的金属，任意合适类型的凸点下金属化层(under-bump metallization)等等。为了改进可焊接性，可以通过从锡、银、金属合金、诸如配置有Ni阻挡层的Au(即NiAu最终层)之类的叠层、NiPdAu等中选择的电镀材料对管芯触点112进一步进行电镀。任意合适的导电合成物可以用于导电体120的形成。
将导电体120密封在模制材料130中，使得导电体120实现与焊接帽140的导电接触。焊接帽140可以包括改进与封装100的焊料粘合性的任意材料。例如，可以使用从锡、银、金属合金、诸如配置有Ni阻挡层的Au(即NiAu最终层)之类的叠层、NiPdAu等中选择的电镀材料。模制材料130典型地是聚合物材料，例如环氧树脂。然而，许多其他合适的模制聚合物材料本身对于本领域普通技术人员也是已知的。
导电体120的横向尺寸小于半导体管芯110的横向尺寸，模制材料130从导电体120横向地延伸至半导体管芯10的边缘，使得在分立半导体器件封装100中从管芯表面到导电体120的顶部的空间完全以模制材料130填充。
除了第一焊接帽140之外，封装100还可以与半导体管芯110的底部触点(未示出)导电接触的第二焊接帽150。因为向这种封装设置焊接帽本身是公知的，为了简明起见不再详细解释这一点。可以说任意合适的焊接帽材料可以用于设置焊接帽140和150。焊接帽150可以是与焊接帽140相同或不同的材料。为了避免封装工艺中的附加复杂性，相同材料是优选的。
图2示出了图1的分立半导体器件封装100的替代实施例，其中用焊接或金属柱120代替导电体120。这说明了分立半导体器件封装100中的导电体120可以具有任意合适的形式。
通常，按照顶部/底部接触朝向将分立半导体器件封装安装到诸如PCB之类的载体上，其中底部触点直接键合到载体，而顶部触点是引线键合触点，用于将顶部触点引线键合至载体。引线键合触点的设置要求最小的面积，这抑制了封装尺寸超过一定尺寸的缩小。
相反，在分立半导体器件封装100中用集成导电体120代替引线键合触点便于这种封装在诸如图3所示的PCB之类的载体200上进行侧向安装，其中焊接帽140和150提供从封装100到外部的触点。载体200具有第一触点210和第二触点220，使用焊接部分250将分立半导体器件封装100焊接到第一和第二触点。在分立半导体器件封装100的端部上设置焊接帽140和150使得焊接部分250能够从相应的触点210和220垂直地延伸。例如，分立半导体器件封装100的侧向安装允许将该封装用于已经设计为容纳更大形状因子的部件如0603二极管封装的PCB。
在图4中示出了用于制造根据图1或图2的半导体封装的方法的实施例。在第一步骤(a)中，提供晶片410，所述晶片包括多个半导体管芯部分110，每一个半导体管芯部分承载管芯触点112。晶片410可以是任意合适的晶片，例如单晶或多晶硅晶片、硅-锗晶片、包括异质结的晶片，例如包括氮化镓异质结器件的晶片等等。管芯触点112可以是任意合适的导电材料，例如金属。优选地，这种金属是在可应用的半导体工艺中可容易应用的金属，例如用于硅基工艺的铜。
在步骤(b)中，相应的导电体120(例如柱或球)形成于每一个管芯触点112上，随后将导电体120密封在模制材料130中，例如诸如环氧树脂之类的聚合物或树脂或者任意其他合适的聚合物材料，如步骤(c)所示。可以在平坦化步骤(未示出)中去除过量的模制材料130，以露出导电体120的上表面。这种密封步骤本身是已知的，并且只是为了简明起见而不再详细地解释。
该方法如可选步骤(d)所示继续，其中将晶片410减薄到所需的厚度，例如通过机械研磨和抛光随后进行可选的回蚀步骤，或者通过诸如化学机械抛光的抛光步骤。随后在步骤(e)中分割晶片410以形成单独的分立半导体器件封装100，例如通过切片或等离子体刻蚀，此后通过在包括导电体120的暴露部分在内的表面上形成焊接帽140、并且在分立半导体器件封装100的半导体管芯110的暴露(底部)表面上形成焊接帽150完成每一个分立半导体器件封装100。
在图4的实施例中，模制材料130形成于半导体管芯110中承载触点112的表面的顶部上，使得通过模制材料130(横向地)密封导电体120。然而，在替代实施例中，使得模制材料130在半导体管芯110中将承载触点112的半导体管芯110表面与半导体管芯110的相对表面(即，底部表面)相连的侧面上延伸，使得模制材料130也密封了半导体管芯110，其具有的优点是对于分立半导体器件封装100的附加保护。
在图5中示出了制造这种分立半导体器件封装100的方法的实施例。步骤(a)和(b)与图4所示方法的步骤(a)和(b)相同，并且只是为了简明起见不再详细描述这些步骤。应注意，在图5中，将晶片410放置于切割带或箔或者一些其他的安装辅助物510上，但是应理解，在图4所示的方法中也可以使用这种安装辅助物。
在步骤(c)中，将晶片410部分地切片以在单独的半导体器件之间产生沟槽520，例如通过等离子体刻蚀或切割步骤，其中至少是安装辅助物510将单独的半导体器件保持在一起。可以增加沟槽520的宽度，即，可以通过拉伸安装辅助物510来将单独的半导体器件彼此进一步间隔开。替代地，具有相对较大厚度的切割刀片可以用于获得针对沟槽520的所需宽度。
接下来，如步骤(d)所示，将所得到的结构密封在模制材料130中。应该注意，在这一步骤中沟槽520也填充了模制材料130，从而在相应半导体管芯110的侧面处提供了密封。如前所述，如果必要，可以向模制材料130施加诸如化学机械抛光步骤之类的平坦化步骤，以暴露导电体120的上表面。在可选步骤(e)中，可以如前所述施加晶片减薄步骤，接着是分割步骤(f)以形成单独的分立半导体器件封装100，例如通过切片(切割)或等离子体刻蚀。在实施例中，通过使用第一厚度的切割刀片的切片步骤来执行步骤(c)，并且通过使用比第一厚度小的第二厚度的切割刀片的切片步骤执行分割步骤(f)，使得第二厚度的切割刀片可以跟随填充有模制材料130的沟槽520，而不会从这些沟槽中完全去除模制材料130。
如前所述，通过在包括导电体120的暴露部分的表面上形成焊接帽140并且在分立半导体器件封装100的半导体管芯110的暴露(底部)表面上形成焊接帽150，如步骤(g)所示完成每一个分立半导体器件封装100。
在图6中示出了本发明的方法的另一实施例。步骤(a)和(b)与图4所示且如上所述的方法的步骤(a)和(b)实质上相同，从而只是为了简明起见不再详细描述这些步骤。唯一的区别在于导电体是凸块或球形而不是如图4所示的柱。在步骤(c)中，提供了包括多个另外的管芯部分的另一半导体晶片610，每一个另外的管芯部分承载管芯触点112’。另外的管芯部分可以限定分离的半导体器件(例如分离的二极管)，以形成背靠背半导体器件封装，或者替代地可以是虚拟管芯部分，在这种情况下最终封装将只包含单独的半导体器件。管芯触点112’导电连接(例如焊接)至导电体120，如步骤(c)所示，使得可以将另外的半导体管芯看作是导电体120的封盖部件。基于双侧晶片的封装工艺的主要优势在于减小了制造复杂度，因此减小了所得到的分立半导体器件封装100的成本。
在替代实施例中(为了简明起见没有明确示出)，可以将另一半导体晶片610划分为更小的部分，之后可以将这种晶片部分的管芯触点112’焊接到导电体120。为了在将另一半导体管芯601放置在焊料部分120上时获得所要求的对准精度，这可能是必要的。
在步骤(d)中，如前所述将导电体120密封在密封材料或模制材料130中，随后可以如前所述执行晶片410和/或另一晶片610的可选减薄步骤。这在步骤(e)中示出。在后续的步骤(f)中，通过分割步骤，例如切片(切割)或等离子刻蚀步骤，形成单独的分立半导体器件封装100，随后如步骤(g)所示，在每一个封装中的半导体管芯的相应底部表面上形成焊接帽140和150。
应该理解，在分立半导体器件封装包括如图6所示的背靠背半导体管芯的情况下，在替代实施例中可以省略步骤(g)，即，可以不向每一个封装提供焊接帽，在这种情况下半导体管芯的底部表面用作封装的帽，如前所述。如果晶片110和610包括可以直接施加载体焊料的可焊背部金属叠层，这是特别切实可行的。
应该注意，上述实施例说明不是限制本发明，本领域的普通技术人员在不脱离所附权利要求的范围的情况下将能够设计许多替代实施例。在权利要求中，不应该将置于括号中的任意附图标记解释为限制权利要求。术语“包括”不排除权利要求中所列元件或步骤以外的元件或步骤的存在。元件前面的词语“一”或“一个”不排除多个这种元件的存在。本发明可以通过包括若干不同元件的硬件来实现。在列举了若干装置的设备权利要求中，这些装置的一些可以由同一硬件来具体实现。在多个彼此不同的从属权利要求中记载某些措施的事实并不表示不能有利地使用这些措施的组合。

Claims (15)

1.一种分立半导体器件封装(100)，包括：
半导体管芯(110)，具有第一表面以及与所述第一表面相对且承载触点(112)的第二表面；
所述触点上的导电体(120)，其中所述导电体(120)的横向尺寸小于半导体管芯(110)的横向尺寸；
密封材料(130)，横向地密封所述导电体；以及
与导电体导电接触的封盖部件(140，610)，所述封盖部件在所述密封材料上延伸。
2.根据权利要求1所述的分立半导体器件封装(100)，其中所述封盖部件(140，610)包括焊接帽(140)。
3.根据权利要求1所述的分立半导体器件封装(100)，其中所述封盖部件(140，610)包括另一半导体管芯(610)，所述分立半导体器件封装(100)还包括所述另一半导体管芯(610)上的焊接帽。
4.根据任一前述权利要求所述的分立半导体器件封装(100)，还包括与所述第一表面导电接触的另一焊接帽(150)。
5.根据权利要求1所述的分立半导体器件封装(100)，其中所述导电体(120)具有球形形状或柱形形状。
6.根据权利要求1所述的分立半导体器件封装(100)，其中所述密封材料(130)沿将第一表面和第二表面相连的半导体管芯(110)的相应侧面延伸。
7.一种载体(200)，包括第一载体触点(210)和第二载体触点(220)，所述载体还包括根据权利要求1至6中任一项所述的分立半导体器件封装(100)，其中通过相应的另外焊接部分(250)将所述第一载体触点导电连接至所述第一表面且将所述第二载体触点导电连接至导电体(120)。
8.一种制造分立半导体封装(100)的方法，包括：
提供晶片(410)，所述晶片包括多个分立半导体器件，每一个所述分立半导体器件具有第一表面以及与所述第一表面相对且承载触点(112)的第二表面；
在每一个所述触点上形成相应的导电体(120)；
用密封材料(130)至少覆盖承载所述导电体的晶片表面，以横向地密封所述导电体；
分割所述分立半导体器件，其中所述导电体(120)的横向尺寸小于分割的分立半导体器件的横向尺寸；以及
至少在每一个所述分立半导体器件的导电体上设置封盖部件(140，610)。
9.根据权利要求8所述的方法，还包括：在所述分割步骤之前，对包括分立半导体器件的相应第一表面在内的晶片(410)的表面进行减薄。
10.根据权利要求8或9所述的方法，其中设置封盖部件(140)的步骤包括在每一个分割的分立半导体器件上设置焊接帽，所述方法还包括在每一个分立半导体器件的第一表面上设置另一焊接帽(150)。
11.根据权利要求8所述的方法，其中所述分割步骤包括对晶片(410)进行切片或等离子体刻蚀以提供分立半导体器件。
12.根据权利要求8所述的方法，还包括：
在所述覆盖步骤之前，部分地分割分立半导体器件，从而暴露将第一表面和第二表面相连的每一个分立半导体器件的侧面；以及
其中所述覆盖步骤还包括用密封材料(130)覆盖所述侧面。
13.根据权利要求12所述的方法，还包括：
在所述部分分割步骤之前，将晶片(410)放置于切割箔(510)上；以及
在所述部分分割步骤之后拉伸所述切割箔，以暴露出分立半导体器件的相应侧面。
14.根据权利要求12所述的方法，其中所述部分分割步骤包括用具有第一厚度的切割刀片切割晶片(410)，并且其中所述分割步骤包括用具有比第一厚度小的第二厚度的切割刀片切割密封的晶片。
15.根据权利要求8所述的方法，其中设置所述封盖部件(610)的步骤还包括将另一半导体晶片(610)设置在所述相应的导电体(120)上。
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