CN105280578A - 可携式装置及其集成电路的封装结构、封装体与封装方法 - Google Patents

可携式装置及其集成电路的封装结构、封装体与封装方法 Download PDF

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CN105280578A
CN105280578A CN201410443444.2A CN201410443444A CN105280578A CN 105280578 A CN105280578 A CN 105280578A CN 201410443444 A CN201410443444 A CN 201410443444A CN 105280578 A CN105280578 A CN 105280578A
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boundary
layer
cut
integrated circuit
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CN105280578B (zh
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温兆均
李兴武
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UPI Semiconductor Corp
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UPI Semiconductor Corp
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Abstract

本发明公开一种可携式装置及其集成电路的封装结构、封装体与封装方法。封装结构包括集成电路的封装体与载板。封装体包括晶粒与冶金层。晶粒具有接触部、切割边界保留部与密封环。密封环位于接触部与切割边界保留部之间。冶金层设置于接触部上且冶金层至少部分设置于密封环之上。冶金层包括涂布有锡膏的可焊层。载板包括焊垫。焊垫耦接涂布有锡膏的可焊层。

Description

可携式装置及其集成电路的封装结构、封装体与封装方法
技术领域
本发明与集成电路的封装有关，特别是关于一种可携式装置及其集成电路的封装结构、封装体与封装方法。
背景技术
近年来，随着科技不断创新与发展，各式各样的可携式装置，例如智能型手机、笔记型电脑、平板电脑、甚至是智能型手表或眼镜等穿戴式电子装置，已广泛地应用于一般消费者的生活中。
然而，由于消费者对于可携式装置的要求愈来愈高，不仅希望可携式装置能够提供更多功能，同时还希望其体积能更轻薄短小，因此，若可携式装置中的具有超小尺寸的集成电路芯片仍采用传统的封装方式，势必无法满足缩减空间的要求，且将集成电路芯片承载于载板及/或印刷电路板上时容易出现空焊(solderempty)等现象，导致产品组装良率不佳。
发明内容
有鉴于此，本发明提供一种可携式装置及其集成电路的封装结构、封装体与封装方法，由此解决现有技术所述及的问题。
根据本发明的一较佳具体实施例为一种集成电路的封装体(PackagingObject)。于此实施例中，集成电路的封装体包括晶粒(Die)与冶金层。晶粒具有接触部、切割边界保留部与密封环(SealRing)。密封环位于接触部与切割边界保留部之间。冶金层设置于接触部上且至少部分设置于密封环之上。
在本发明的一实施例中，切割边界保留部具有预设宽度，且冶金层至少部分设置于切割边界保留部之上。
在本发明的一实施例中，预设宽度为10微米(μm)。
在本发明的一实施例中，冶金层的外侧边缘与切割边界保留部的外侧边缘之间的距离介于0至54微米(μm)之间。
在本发明的一实施例中，冶金层包括可焊层，可焊层可被涂布锡膏，以耦接载板上的焊垫。
根据本发明的另一较佳具体实施例为一种集成电路的封装结构。于此实施例中，集成电路的封装结构包括集成电路的封装体与载板。集成电路的封装体包括晶粒与冶金层。晶粒具有接触部、切割边界保留部与密封环。密封环位于接触部与切割边界保留部之间。冶金层设置于接触部上且至少部分设置于密封环之上。冶金层包括涂布有锡膏的可焊层。载板包括焊垫。焊垫耦接涂布有锡膏的可焊层。
在本发明的一实施例中，切割边界保留部具有预设宽度，且冶金层至少部分设置于切割边界保留部之上。
在本发明的一实施例中，预设宽度为10微米(μm)。
在本发明的一实施例中，冶金层的外侧边缘与切割边界保留部的外侧边缘之间的距离介于0至54微米(μm)之间。
在本发明的一实施例中，焊垫的面积大于涂布有锡膏的可焊层的面积。
根据本发明的另一较佳具体实施例为一种可携式装置。于此实施例中，可携式装置包括电路板与集成电路的封装体。集成电路的封装体包括晶粒与冶金层。晶粒具有接触部、切割边界保留部与密封环。密封环位于接触部与切割边界保留部之间。冶金层设置于接触部上且冶金层至少部分设置于密封环之上。冶金层包括涂布有锡膏的可焊层。载板设置有焊垫。集成电路的封装体通过涂布有锡膏的可焊层耦接电路板。
在本发明的一实施例中，切割边界保留部具有预设宽度，且冶金层至少部分设置于切割边界保留部之上。
在本发明的一实施例中，预设宽度为10微米(μm)。
在本发明的一实施例中，冶金层的外侧边缘与切割边界保留部的外侧边缘之间的距离介于0至54微米(μm)之间。
根据本发明的另一较佳具体实施例为一种集成电路的封装方法。于此实施例中，集成电路的封装方法包括下列步骤：(a)提供一晶粒，晶粒具有接触部、切割边界保留部与密封环，密封环位于接触部与切割边界保留部之间；以及(b)设置冶金层于晶粒的接触部上，其中冶金层至少部分设置于密封环之上。
在本发明的一实施例中，切割边界保留部具有预设宽度，且冶金层至少部分设置于切割边界保留部之上。
在本发明的一实施例中，预设宽度为10微米(μm)。
在本发明的一实施例中，冶金层的外侧边缘与切割边界保留部的外侧边缘之间的距离介于0至54微米(μm)之间。
相较于现有技术，根据本发明所公开的可携式装置及其集成电路的封装结构、封装体与封装方法是通过在集成电路的晶粒中将至少部分的冶金层(MetallurgyLayer)设置于密封环之上及/或设置于切割边界保留部之上，使得冶金层的外侧边缘与切割边界保留部的外侧边缘之间的距离能比现有工艺中所能达到的最小距离更加缩减，进而实现超小尺寸的集成电路的封装结构，故能广泛应用于任何需要体积轻薄短小的可携式装置，例如智能型手表或眼镜等穿戴式电子装置，具有相当庞大的市场发展潜力。
关于本发明的优点与精神可以通过以下的发明具体实施方式与附图得到进一步的了解。
附图说明
图1为晶圆完成品包括多个晶粒的示意图。
图2A与图2B分别为根据本发明的一实施例之从晶圆完成品切割出的晶粒的俯视图与侧视图。
图2C为图2B中的冶金层的放大图。
图3A与图3B分别为载板的俯视图与侧视图。
图4A与图4B为晶粒上的焊垫与载板上的焊垫通过回焊方式形成电性连接的示意图。
图5A为晶粒上至少有部分的冶金层位于密封环之上的俯视图。
图5B为晶粒上至少有部分的冶金层位于切割边界保留部之上的俯视图。
图6为图5A中的晶圆完成品的一部分切割为晶粒后沿AA’的剖面图。
图7为根据本发明的另一实施例的封装方法的流程图。
主要元件符号说明：
1：晶圆完成品
10～12：晶粒
13：晶圆完成品的一部分
CL：切割线
100、110、120：接触部
102、112、122：晶粒边界
104、114、124：密封环
106：有效电路边界
108、118、128：切割边界保留部
20：载板
P1、P1’：冶金层
P2：焊垫
PL：钝化层
AL：粘附层
BL：障碍层
SL：可焊层
ORL：保护层
ST：切割道
AA’：剖面
d0～d2：距离
S10～S20：流程步骤
具体实施方式
现在将详细参考本发明的示范性实施例，并在附图中说明所述示范性实施例的实例。另外，在图式与实施方式中所使用相同或类似标号的元件/构件是用来代表相同或类似部分。在下述诸实施例中，当元件被指为“连接”或“耦接”至另一元件时，其可为直接连接或耦接至另一元件，或可能存在介于其间的元件或特定材料(例如：胶体或焊料)。
根据本发明的一较佳具体实施例为一种集成电路的封装结构。于此实施例中，集成电路的封装结构包括集成电路的封装体与载板。上述集成电路的封装体包括由晶圆完成品(FinishedWafer)切割出来的晶粒，晶粒具有集成电路。载板用以承载封装该晶粒的封装体，但不以此为限。在本发明的一实施例中，上述晶粒中的集成电路可以是功率型金属氧化物半导体场效应晶体(PowerMOSFET)、稳压器(LDO)或其他低接脚数的集成电路，但上述集成电路不以此为限。
需说明的是，上述载板通常可称为IC基板或IC载板，主要功能为承载晶粒做为载体之用，并以载板的内部线路连接晶粒与印刷电路板(PCB)之间的信号，主要为保护电路、固定线路与导散余热，为封装工艺中的关键零件。于实际应用中，上述载板的材质可视实际需求采用印刷电路板、陶瓷载板、塑胶载板、金属载板或卷带载板，并无特定的限制。
请参照图1，图1为晶圆完成品包括多个晶粒的示意图。如图1所示，晶圆完成品(FinishedWafer)1包括有多个晶粒(Dies)10，该些晶粒10上通常会具有各种不同形式或功能的集成电路，但不以此为限。实际上，可通过适当的晶粒切割器沿着晶圆完成品1上的切割线CL进行切割，以切割出该些晶粒10。需说明的是，由于晶粒切割器的刀具通常会具有一定的厚度(宽度)，例如：15～20微米(μm)，所以一般会设计有切割道ST，其具有一预设切割道宽度，例如50微米(μm)，以避免刀具进行切割时产生偏差而造成晶粒10内部电路的损伤。
接着，请参照图2A与图2B，图2A与图2B分别图示从图1中的晶圆完成品1切割出的晶粒10的俯视图与侧视图。如图2A与图2B所示，晶粒10具有接触部100、晶粒边界102、密封环104、有效电路边界106、切割边界保留部108与冶金层(MetallurgyLayer)P1。
接触部100位于有效电路边界106内的有效电路区域里。切割边界保留部108为刀具沿着晶圆完成品1上的切割道ST切割出晶粒10后还保留在晶粒10上的部分的切割道，通常切割边界保留部108会具有10微米(μm)的预设宽度，但不以此为限。切割边界保留部108位于晶粒边界102与密封环104之间。密封环104位于接触部100与切割边界保留部108之间。在本发明的一实施例中，密封环104的宽度可为25微米(μm)。在本发明的一实施例中，冶金层P1设置于接触部100上，并且至少有部分的冶金层P1会位于密封环104之上。
需说明的是，晶粒10上的接触部100(凸块)通常是芯片封装体的接脚(pin)与晶粒10内部集成电路的沟通媒介。此外，本实施例中的晶粒10可应用于轻薄短小的可携式装置，因此晶粒10需具有超小的尺寸，在本实施例中，晶粒10上所设置的接触部100数目至多为16个，较佳为3个至8个，但不以此为限。
于此实施例中，如图2A所示，假设接触部100的外侧边缘与晶粒边界102之间的距离为d0，冶金层P1的外侧边缘与切割边界保留部108的外侧边缘(亦即晶粒边界102)之间的距离为d1，由于传统的冶金层的外侧边缘至多只形成在接触部100的外侧边缘上方。也就是说，传统冶金层的外侧边缘与晶粒边界之间的距离d0最小为55微米(μm)。然而，在本实施例中，冶金层P1的外侧边缘会延伸形成在密封环104之上。因此，在本实施例中，d1会小于55微米(μm)，通常是介于0至55微米(μm)之间，在本发明的一实施例中，d1是介于0至54微米(μm)之间，在其他实施例中，d1最佳是介于10至54微米(μm)之间，但不以此为限。
此外，从图2C所图示的放大图可知，晶粒10的接触部100周围设置有钝化层(PassivationLayer)PL，用以隔离并避免接触部100与外部电性连接。冶金层P1设置于晶粒10的接触部100与钝化层PL上。在本实施例中，冶金层P1可为球下冶金(UnderBumpMetallurgy，UBM)层，其又可称为多层金属层，于此实施例中，作为UBM层的冶金层P1可包括粘附层(AdhesionLayer)AL、障碍层(BarrierLayer)BL、可焊层(SolderableLayer)SL与保护层(OxidationResistanceLayer)ORL。在其他实施例中，冶金层P1亦可包括至少一层金属层或至少一层可焊层，本发明并不对此加以限制。
粘附层AL形成于晶粒10的接触部100与钝化层PL上，用以与接触部100与钝化层PL形成较强的连结；障碍层BL形成于粘附层AL上，用以防止接触部100与可焊层SL之间的扩散发生。实际上，粘附层AL与障碍层BL的材质可以是铬(Cr)、钛(Ti)、钛/钨(Ti/W)、镍(Ni)、钯(Pd)或钼(Mo)，其厚度约为0.15～0.2mm，但不以此为限。
可焊层SL形成于障碍层BL上，用以供焊锡在回焊(Reflow)时可完全滞留附立其上而成球状。实际上，可焊层SL的材质可以是铜(Cu)、镍(Ni)或钯(Pd)，其厚度约为1～5mm，但不以此为限。于此实施例中，可焊层SL上可涂布有锡膏(SolderPaste)，以使得晶粒10能够与载板或电路板形成电性连接。在本发明的一实施例中，可焊层SL的厚度大于障碍层BL的厚度，但不以此为限。
保护层ORL形成于可焊层SL上，用以保护其下方的粘附层AL、障碍层BL与可焊层SL，以避免这些金属层被氧化。实际上，保护层ORL的材质通常为金(Au)，其厚度约为0.05～0.1mm，但不以此为限。
请参照图3A与图3B，图3A与图3B分别为载板的俯视图与侧视图。如图3A与图3B所示，载板20上设置有焊垫P2。为了比较载板20上的焊垫P2与晶粒10上的冶金层P1，图3A中以虚线图示出晶粒10与其冶金层P1。需说明的是，由于载板20用以承载晶粒10，所以载板20上所设置的焊垫P2会对应于晶粒10上的冶金层P1，但载板20上所设置的焊垫P2的面积会稍大于晶粒10上的冶金层P1的面积，使得图2C所示的晶粒10上的涂布有锡膏的可焊层SL与图3B所示的载板20上的焊垫P2在如图4B所示通过回焊(Reflow)方式耦接在一起(如图4B中的斜线部分所示)而形成电性连接时，较不易产生空焊(solderempty)的现象。
由此，晶粒10便可承载于载板20上并且彼此电性连接。根据图3A与图4A可知，由于载板20上所设置的焊垫P2面积较大，会有部分的焊垫P2位于晶粒10的晶粒边界(虚线)102之外，再加上晶粒10上的冶金层P1相当靠近晶粒边界102，因此，当晶粒10上的冶金层P1与载板20上的焊垫P2通过回焊方式耦接在一起时，如图4B所示，载板20上会有些许热融的焊垫P2与晶粒10的一侧部分耦接。
接着，承载晶粒10的载板20可设置于可携式装置中的一印刷电路板(PCB)或主机板上并与印刷电路板电性连接，使得载板20能通过其内部线路连接晶粒10与印刷电路板之间的信号，由此可携式装置可通过印刷电路板与载板20控制晶粒10上的有效电路区域中的集成电路执行某一功能。在其他实施例中，晶粒10也可以通过冶金层P1与涂布在治金层P1的可焊层SL的锡膏来耦接可携式装置中的印刷电路板上的焊垫。
接着，请参照图5A，图5A为图1的晶圆完成品1的一部分13中的晶粒11与12上至少有部分的冶金层位于密封环之上的俯视图。如图5A所示，晶圆完成品1的一部分13上的切割线CL的两侧为切割道ST。切割道ST的左边与右边分别为晶粒11的晶粒边界112与晶粒12的晶粒边界122。
于晶粒12中，晶粒12具有接触部120、晶粒边界122、密封环124、切割边界保留部128与冶金层P1。切割边界保留部128位于晶粒边界122与密封环124之间。密封环124位于切割边界保留部128与接触部120之间。冶金层P1设置于接触部120上，并且至少有部分的冶金层P1会延伸至密封环124之上而位于密封环124之上。
于实际应用中，假设接触部120的外侧边缘与晶粒边界122之间的距离为d0，冶金层P1的外侧边缘与晶粒边界122(亦即切割边界保留部128的外侧边缘)之间的距离为d1，由于传统的冶金层的外侧边缘通常会切齐接触部的外侧边缘，亦即d0即为传统的冶金层的外侧边缘与晶粒边界之间的距离55微米(μm)，至于本实施例的冶金层P1的外侧边缘会延伸至密封环124之上，因此，d1会小于d0，通常是介于0至54微米(μm)之间，最佳是介于10至54微米(μm)之间，但不以此为限。
同理，于晶粒11中，晶粒11具有接触部110、晶粒边界112、密封环114、切割边界保留部118与冶金层P1。切割边界保留部118位于晶粒边界112与密封环114之间。密封环114位于切割边界保留部118与接触部110之间。冶金层P1设置于接触部110上，并且至少有部分的冶金层P1会延伸至密封环114之上而位于密封环114之上，使得接触部110的外侧边缘与晶粒边界112之间的距离会小于冶金层P1的外侧边缘与晶粒边界112(亦即切割边界保留部118的外侧边缘)之间的距离55微米(μm)，通常是介于0至54微米(μm)之间，最佳是介于10至54微米(μm)之间，但不以此为限。
需说明的是，于上述图5A的实施例中，晶粒上的冶金层至少会有一部分延伸至密封环之上而位于密封环之上。于实际应用中，晶粒上的冶金层亦可至少有一部分延伸至切割边界保留部之上而位于切割边界保留部之上。
如图5B所示，于晶粒12中，假设接触部120的外侧边缘与晶粒边界122之间的距离为d0，冶金层P1’的外侧边缘与晶粒边界122(亦即切割边界保留部128的外侧边缘)之间的距离为d2，由于传统的冶金层的外侧边缘通常会切齐接触部120的外侧边缘，亦即d0即为传统的冶金层的外侧边缘与晶粒边界之间的距离55微米(μm)，至于本案的冶金层P1’的外侧边缘会延伸至切割边界保留部128之上，因此，d2会小于55微米(μm)，通常是介于0至54微米(μm)之间，最佳是介于2至54微米(μm)之间，但不以此为限。至于图5B中的晶粒11，由于晶粒11与晶粒12情况相同，故于此不另行赘述。
比较图5A与图5B可知：由于图5A中的晶粒12有部分的冶金层P1会延伸至密封环124之上而位于密封环124之上，而图5B中的晶粒12有部分的冶金层P1’会延伸至切割边界保留部128之上而位于切割边界保留部128之上，并且切割边界保留部128比密封环124更靠近晶粒边界122，亦即图5B中的冶金层P1’的外侧边缘会比图5A中的冶金层P1的外侧边缘更靠近晶粒边界122，因此，图5B中的冶金层P1’的外侧边缘与晶粒边界122之间的距离d2会小于图5A中的冶金层P1的外侧边缘与晶粒边界122之间的距离d1。
请参照图6，图6为将图5中的晶圆完成品1的部分13切割为晶粒12后沿AA’的剖面图。如图6所示，切割边界保留部128位于晶粒边界122与密封环124之间，而密封环124位于切割边界保留部128与接触部120之间。钝化层PL形成于接触部120与密封环124之上，用以隔离并避免接触部120与外部电性连接。保护层PL上形成有一开孔，使得部分的接触部120暴露出来，而能让冶金层P1设置于接触部120与保护层PL上，并且至少有部分的冶金层P1会位于密封环124之上。
根据本发明的另一较佳具体实施例为一种集成电路的封装方法。于此实施例中，集成电路的封装方法用以形成应用于可携式装置中的具有集成电路的一晶粒的封装结构，但不以此为限。至于可携式装置可以是智能型手机、平板电脑、甚至是穿戴式的智能型手表或眼镜等，并无特定的限制。
请参照图7，图7为此实施例的集成电路的封装方法的流程图。如图7所示，于步骤S10中，该封装方法提供一晶粒。于此实施例中，晶粒具有接触部、切割边界保留部与密封环。密封环位于接触部与切割边界保留部之间。
于步骤S12中，该封装方法设置冶金层于晶粒的接触部上，其中冶金层至少部分设置于密封环之上。于此实施例中，冶金层可依序包括连接接触部的粘附层、障碍层、可焊层与涂布于可焊层上的锡膏。于一实施例中，可焊层的厚度大于障碍层的厚度，但不以此为限。
于步骤S14中，该封装方法提供设置有焊垫的载板。于步骤S16中，该封装方法耦接焊垫与涂布有锡膏的可焊层，致使载板承载封装体而形成集成电路的封装结构。于此实施例中，步骤S16可通过回焊方式耦接焊垫与涂布有锡膏的可焊层，但不以此为限。
于步骤S18中，该封装方法提供设置于可携式装置内的电路板。于步骤S20中，该封装方法将步骤S16所完成的封装结构设置于电路板上并与电路板电性连接，以供可携式装置能通过电路板与载板控制晶粒上的有效电路区域中的集成电路执行特定功能。
相较于现有技术，根据本发明所公开的可携式装置及其集成电路的封装结构、封装体与封装方法是通过在集成电路的晶粒中将至少部分的球下金属层(UnderBumpMetallurgy,UBM)设置于密封环之上及/或设置于切割边界保留部之上，使得球下金属层的外侧边缘与切割边界保留部的外侧边缘之间的距离能比现有工艺中所能达到的最小距离更加缩减，进而实现超小尺寸的集成电路的封装结构，故能广泛应用于任何需要体积轻薄短小的可携式装置，例如智能型手表或眼镜等穿戴式电子装置，具有相当庞大的市场发展潜力。
通过以上较佳具体实施例的详述，是希望能更加清楚描述本发明的特征与精神，而并非以上述所公开的较佳具体实施例来对本发明的范畴加以限制。相反地，其目的是希望能涵盖各种改变与具相等性的安排于本发明所欲申请的专利权利要求的范畴内。

Claims (18)

1.一种集成电路的封装体，其特征在于，上述集成电路的封装体包括：
一晶粒，具有一接触部、一切割边界保留部与一密封环，其中上述密封环位于上述接触部与上述切割边界保留部之间；以及
一冶金层，设置于上述接触部上且至少有一部分设置于上述密封环之上。
2.如权利要求1所述的集成电路的封装体，其特征在于，上述切割边界保留部具有一预设宽度，且上述冶金层至少有一部分设置于上述切割边界保留部之上。
3.如权利要求2所述的集成电路的封装体，其特征在于，上述预设宽度为10微米(μm)。
4.如权利要求1所述的集成电路的封装体，其特征在于，上述冶金层的外侧边缘与上述切割边界保留部的外侧边缘之间的一距离介于0至54微米(μm)之间。
5.如权利要求1所述的集成电路的封装体，其特征在于，上述冶金层包括一可焊层，上述可焊层可被涂布一锡膏，以耦接一载板上的一焊垫。
6.一种集成电路的封装结构，其特征在于，上述集成电路的封装结构包括：
一集成电路的封装体，包括：
一晶粒，具有一接触部、一切割边界保留部与一密封环，其中上述密封环位于上述接触部与上述切割边界保留部之间；以及
一冶金层，设置于上述接触部上且上述冶金层至少有一部分设置于上述密封环之上，上述冶金层包括涂布有一锡膏的一可焊层；以及
一载板，包括一焊垫，上述焊垫耦接涂布有上述锡膏的上述可焊层。
7.如权利要求6所述的集成电路的封装结构，其特征在于，上述切割边界保留部具有一预设宽度，且上述冶金层至少上述部分设置于上述切割边界保留部之上。
8.如权利要求7所述的集成电路的封装结构，其特征在于，上述预设宽度为10微米(μm)。
9.如权利要求6所述的集成电路的封装结构，其特征在于，上述冶金层的外侧边缘与上述切割边界保留部的外侧边缘之间的一距离介于0至54微米(μm)之间。
10.如权利要求6所述的集成电路的封装结构，其特征在于，上述焊垫的面积大于涂布有上述锡膏的上述可焊层的面积。
11.一种可携式装置，其特征在于，上述可携式装置包括：
一电路板；以及
一集成电路的封装体，包括：
一晶粒，具有一接触部、一切割边界保留部与一密封环，其中上述密封环位于上述接触部与上述切割边界保留部之间；以及
一冶金层，设置于上述接触部上且至少有一部分设置于上述密封环之上，上述冶金层包括涂布有一锡膏的一可焊层，其中上述封装体通过涂布有上述锡膏的上述可焊层耦接上述电路板。
12.如权利要求11所述的可携式装置，其特征在于，上述切割边界保留部具有一预设宽度，且上述冶金层至少有一部分设置于上述切割边界保留部之上。
13.如权利要求12所述的可携式装置，其特征在于，上述预设宽度为10微米(μm)。
14.如权利要求11项所述的可携式装置，其特征在于，上述冶金层的外侧边缘与上述切割边界保留部的外侧边缘之间的一距离介于0至54微米(μm)之间。
15.一种集成电路的封装方法，其特征在于，上述集成电路的封装方法包括下列步骤：
(a)提供一晶粒，上述晶粒具有一接触部、一切割边界保留部与一密封环，上述密封环位于上述接触部与上述切割边界保留部之间；以及
(b)设置一冶金层于上述晶粒的上述接触部上，其中上述冶金层至少有一部分设置于上述密封环之上。
16.如权利要求15所述的集成电路的封装方法，其特征在于，上述切割边界保留部具有一预设宽度，且上述冶金层至少有一部分设置于上述切割边界保留部之上。
17.如权利要求16所述的集成电路的封装方法，其特征在于，上述预设宽度为10微米(μm)。
18.如权利要求15所述的集成电路的封装方法，其特征在于，上述冶金层的外侧边缘与上述切割边界保留部的外侧边缘之间的一距离介于0至54微米(μm)之间。
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