CN103887183B - 金/硅共晶芯片焊接方法及晶体管 - Google Patents

金/硅共晶芯片焊接方法及晶体管 Download PDF

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Publication number
CN103887183B
CN103887183B CN201210562498.1A CN201210562498A CN103887183B CN 103887183 B CN103887183 B CN 103887183B CN 201210562498 A CN201210562498 A CN 201210562498A CN 103887183 B CN103887183 B CN 103887183B
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Prior art keywords
gold
layer
chip
transistor
welding method
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CN201210562498.1A
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CN103887183A (zh
Inventor
贠伦刚
黄安
田鹏博
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN201210562498.1A priority Critical patent/CN103887183B/zh
Priority to PCT/CN2013/080708 priority patent/WO2014094436A1/zh
Priority to EP13799475.2A priority patent/EP2768015A4/en
Priority to US14/104,237 priority patent/US8916970B2/en
Publication of CN103887183A publication Critical patent/CN103887183A/zh
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Abstract

本发明提供了一种金/硅共晶芯片焊接方法及晶体管，涉及电子器件，用来解决现有金/硅共晶焊接方法中由于芯片载体上电镀金层较厚造成的晶体管成本上升的技术问题。所述金/硅共晶芯片焊接方法包括：在芯片载体的表面电镀厚度小于等于1微米的金层；在焊接区域的所述金层上键合多个金凸起；在共晶温度下将芯片在焊接区域进行摩擦形成焊接层。所述晶体管，包括芯片、芯片载体和连接所述芯片和所述芯片载体的中间层，所述焊中间层为利用上述焊接方法获得的焊接层。本发明较大程度上减少了金的用量，降低了金/硅共晶焊的成本，也相应降低了晶体管的成本。

Description

金/硅共晶芯片焊接方法及晶体管
技术领域
本发明涉及电子器件，尤其涉及金/硅共晶芯片焊接方法及晶体管。
背景技术
功率半导体的芯片通常采用金/硅共晶焊的方式实现和芯片载体的物理连接，具体实现过程是：如图1和图2所示，首先在具有金属材质的芯片载体21的表面电镀金层，然后在高于金/硅共晶温度(363℃)下将具有硅基体的芯片23在芯片载体21上的焊接区域22进行摩擦，金/硅反应形成液态的金/硅合金，冷却后，形成的金/硅合金层24实现芯片23和芯片载体21之间的物理连接。
但是要实现芯片与芯片载体的良好连接，一般要求芯片载体上镀金层厚度至少为2.5微米；而且受电镀技术限制，芯片载体通常只能整体镀金，即芯片载体的所有外表面(包括如图1所示的顶面211、侧面212和底面213)同时镀金，只在芯片载体上单面镀金，或者在焊接区域22局部镀金，现有电镀技术很难实现。然而焊接区域面积只占芯片载体的总外表面面积的百分之几，镀金成本是按照镀金面积(立方体六个面面积之和)计算的，这样导致芯片载体成本昂贵。而且随着金价不断上涨，芯片载体的成本也会不断上涨，这样在功率电子产品上应用金/硅共晶焊的成本越来越高。
因此，提供一种焊接方法，在保证芯片和芯片载体良好连接的前提下，进一步降低金/硅共晶焊的成本成为本领域人员需要解决的问题。
发明内容
本发明提供一种金/硅共晶芯片焊接方法及晶体管，用来解决现有金/硅共晶焊接方法中由于芯片载体上电镀金层较厚造成的晶体管成本上升的技术问题。
为达到上述目的，本发明采用如下技术方案：
一方面，提供了一种金/硅共晶芯片焊接方法，包括：
在芯片载体的表面电镀厚度小于等于1微米的金层。
在焊接区域的所述金层上键合多个金凸起。
在共晶温度下将芯片在焊接区域进行摩擦，使所述金凸起与所述芯片表体反应形成硅金焊点而实现所述芯片在所述载体上的封装。
在第一种可能的实现方式中，所述金层为纯金或钯金。
在第二种可能的实现方式中，当所述金层为纯金时，所述金层的厚度为0.3-1.0微米；当所述金层为钯金时，钯层部分的厚度为0.05-0.2微米，金层部分的厚度为0.05-0.2微米。
在第三种可能的实现方式中，所述金凸起为点状凸起、线状凸起、带状凸起中的一种或多种。
在第四种可能的实现方式中，所述线状凸起的直径为大于等于15微米。
在第五种可能的实现方式中，所述带状凸起的厚度大于等于6微米。
另一方面，提供了一种晶体管，包括芯片、芯片载体和连接所述芯片和所述芯片载体的中间层，所述焊中间层为利用上述焊接方法获得的焊接层。
在第一种可能的实现方式中，所述晶体管为以硅为基体的晶体管。
本发明实施例提供的金/硅共晶芯片焊接方法及晶体管，由于首先在芯片载体的表面电镀厚度小于等于1微米的金层，然后在焊接区域的金层上键合多个金凸起，最后在共晶温度下将芯片在焊接区域进行摩擦形成焊接层。这样相当于只是在焊接区域局部加厚了金层厚度，金凸起提供了金/硅共晶焊所需的大部分金，较大程度上减少了金的用量，降低了金/硅共晶焊的成本，相应也就降低了晶体管的成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术提供的芯片载体的结构示意图；
图2为现有技术提供的芯片与芯片载体的结构示意图；
图3为本发明实施例提供的金/硅共晶芯片焊接方法的流程图；
图4为本发明实施例提供的芯片载体的结构示意图；
图5为本发明实施例提供的芯片载体的另一结构示意图；
图6为本发明实施例提供的芯片载体的另一结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图3所示为本发明提供的金/硅共晶芯片焊接方法的流程图，包括：
步骤11、参见图4-图6，在芯片载体21的表面电镀厚度小于等于1微米的金层。
因为电镀可以实现均匀并且较薄的镀层，所以这里的芯片载体采用可以电镀的金属材质，例如钼合金、钨合金、铜合金、铜-钼合金或其中的一种或多种合金的组合。其中金层可以为为纯金层或钯层与金层构成的钯金层。当所述金层为纯金层时，所述纯金层的厚度为0.3-1.0微米；当所述金层为钯金层时，钯层部分的厚度为0.05-0.2微米，金层部分的厚度为0.05-0.2微米，其电镀过程是首先电镀钯层，然后在钯层上电镀金层。
这里电镀金层的厚度小于等于1微米，比现有技术中电镀2.5微米的金层要小得多。
步骤12、参见图4-图6，在焊接区域22的所述金层上键合多个金凸起25。
由于在芯片载体21上局部镀金，现有电镀技术是很难实现的。因此本发明采用键合的方法在金层的焊接区域22形成多个金凸起25，这样由金凸起25来提供金/硅共晶焊所需要的大部分金，而芯片载体21上其它区域只有小于等于1微米的较薄金层。这在很大程度上减少了金的用量，降低了金/硅共晶焊的成本。
本发明中，实现金凸起的键合方法同半导体封装行业中所指的引线键合方法是一样的，所谓引线键合一般指以金属引线实现半导体芯片和引线框架或者芯片与基板之间的电性连接，引线键合按形式分为球键合和楔键合两类。在半导体封装行业，金属引线应用最多的是金引线，其次是铝引线和铜引线。本发明采用的是金引线键合，以金引线在金层上键合金凸起。其中金凸起25的形状可以为如图4所示的点状、如图5所示的线状或如图6所示的带状或其中一种或多种的组合。但是金凸起不管是哪种形状，其尺寸的限定应满足：金凸起与焊接区域金层的体积之和不低于现有技术中当金层厚度为2.5微米时焊接区域金层的体积，这样才能满足芯片与芯片载体焊接后良好的结合。
另外，当金凸起为点状凸起时，我们可以采用球键合装置将从市场上购买到的金线在焊接区域形成多个球点；当金凸起为线状凸起时，我们既可以采用球键合装置，也可以采用楔键合装置将从市场上购买到的金线在焊接区域形成一系列键合线；当金凸起为带状凸起时，我们可以采用楔键合装置将从市场上购买到的金带焊接在焊接区域的金层上形成一系列带状的键合线。其中，球键合或者楔键合时采用的金线优选其直径大于等于15微米，楔键合时采用的金带优选其厚度大于等于6微米。
步骤13、在共晶温度下将芯片在焊接区域进行摩擦形成焊接层。
因为只有在共晶温度下，金/硅才能形成共晶合金，在常压下金/硅的共晶温度为363℃，当将芯片载体加热到共晶温度时将芯片在焊接区域与金凸起摩擦，产生均匀的金/硅焊接层，将芯片与芯片载体很好地连接在一起。
综上所述，本发明实施例提供的金/硅共晶芯片焊接方法，由于首先在芯片载体的表面电镀厚度小于等于1微米的金层，然后在焊接区域的所述金层上键合多个金凸起，最后在共晶温度下将芯片在焊接区域进行摩擦形成焊接层。这样相当于只是在焊接区域局部加厚了金层厚度，金凸起提供了金/硅共晶焊所需的大部分金，较大程度上减少了金的用量，降低了金/硅共晶焊的成本。
在金/硅共晶焊接完成后便进行外部连接，芯片通过引线键合连接到外部端子上。
本发明实施例还提供了一种晶体管，包括芯片、芯片载体和连接所述芯片和所述芯片载体的中间层，所述中间层为利用上述金/硅共晶焊方法获得的焊接层。
本发明实施例提供的晶体管，由于用于连接芯片和芯片载体的中间层是利用上述金/硅共晶焊方法获得的焊接层，所以晶体管的成本也相应降低。
其中，上述实施例中的晶体管可以为无线基站中的射频场效应晶体管，或是其它电子器件上具有以硅为基体的大功率芯片的功率管。
通常对于射频功率场效应晶体管而言，芯片载体上表面焊接芯片，芯片载体下表面焊接在电路板上，前者采用金/硅共晶焊技术，后者采用含锡焊料焊接；理论上，芯片载体上、下表面的焊接对金厚的要求是不同的，上表面焊接芯片的区域希望金厚不低于2.5微米(厚金)；下表面金厚希望控制的范围在0.08～1微米(薄金)，因为芯片载体和电路板焊接时，会生成脆性较大的金锡化合物，如果金厚达到1微米以上，金锡化合物导致焊点开裂的风险很大。可见，两种焊接对芯片载体上镀金要求是相互矛盾的，现有技术通常是按焊接芯片要求整体至少镀2.5微米的金。这样一方面由于金的用量较大，提高了射频功率场效应晶体管的成本，另一方面由于芯片载体下表面的金厚超过了1微米，提高了金锡化合物导致焊点开裂的风险。因此射频功率场效应晶体管采用本发明提供的晶体管，便可以解决上述问题
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (8)

1.一种金/硅共晶芯片焊接方法，其特征在于，包括：
在芯片载体的表面电镀厚度小于等于1微米的金层；
在焊接区域的所述金层上键合多个金凸起；
在共晶温度下将芯片在焊接区域进行摩擦，使所述金凸起与所述芯片表体反应形成硅金焊点而实现所述芯片在所述载体上的封装。
2.根据权利要求1所述的金/硅共晶芯片焊接方法，其特征在于，所述金层为纯金或钯金。
3.根据权利要求2所述的金/硅共晶芯片焊接方法，其特征在于，当所述金层为纯金时，所述金层的厚度为0.3-1.0微米；当所述金层为钯金时，钯层部分的厚度为0.05-0.2微米，金层部分的厚度为0.05-0.2微米。
4.根据权利要求1所述的金/硅共晶芯片焊接方法，其特征在于，所述金凸起为点状凸起、线状凸起、带状凸起中的一种或多种。
5.根据权利要求4所述的金/硅共晶芯片焊接方法，其特征在于，所述线状凸起的直径为大于等于15微米。
6.根据权利要求4所述的金/硅共晶芯片焊接方法，其特征在于，所述带状凸起的厚度大于等于6微米。
7.一种晶体管，其特征在于，包括芯片、芯片载体和连接所述芯片和所述芯片载体的中间层，所述中间层为利用权利要求1-6中任一项所述的焊接方法获得的焊接层。
8.根据权利要求7所述的晶体管，其特征在于，所述晶体管为以硅为基体的晶体管。
CN201210562498.1A 2012-12-21 2012-12-21 金/硅共晶芯片焊接方法及晶体管 Active CN103887183B (zh)

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EP13799475.2A EP2768015A4 (en) 2012-12-21 2013-08-02 EUTECTIC BRAZING METHOD GOLD / SILICON CHIP AND TRANSISTOR
US14/104,237 US8916970B2 (en) 2012-12-21 2013-12-12 Method for welding gold-silicon eutectic chip, and transistor

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