TWI559413B - 可攜式裝置及其積體電路的封裝結構、封裝體與封裝方法 - Google Patents

可攜式裝置及其積體電路的封裝結構、封裝體與封裝方法 Download PDF

Info

Publication number
TWI559413B
TWI559413B TW103125569A TW103125569A TWI559413B TW I559413 B TWI559413 B TW I559413B TW 103125569 A TW103125569 A TW 103125569A TW 103125569 A TW103125569 A TW 103125569A TW I559413 B TWI559413 B TW I559413B
Authority
TW
Taiwan
Prior art keywords
layer
die
metallurgical
cutting boundary
contact portion
Prior art date
Application number
TW103125569A
Other languages
English (en)
Other versions
TW201604975A (zh
Inventor
溫兆均
李興武
Original Assignee
力智電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力智電子股份有限公司 filed Critical 力智電子股份有限公司
Priority to TW103125569A priority Critical patent/TWI559413B/zh
Priority to CN201410443444.2A priority patent/CN105280578B/zh
Priority to US14/732,086 priority patent/US9443809B2/en
Publication of TW201604975A publication Critical patent/TW201604975A/zh
Application granted granted Critical
Publication of TWI559413B publication Critical patent/TWI559413B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/6027—Mounting on semiconductor conductive members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05012—Shape in top view
    • H01L2224/05014—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05023—Disposition the whole internal layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/08113—Disposition the whole bonding area protruding from the surface of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H01L2224/13027—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being offset with respect to the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/14155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32104—Disposition relative to the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Packages (AREA)
  • Wire Bonding (AREA)

Description

可攜式裝置及其積體電路的封裝結構、封裝體與封裝方法
本發明與積體電路的封裝有關，特別是關於一種可攜式裝置及其積體電路的封裝結構、封裝體與封裝方法。
近年來，隨著科技不斷創新與發展，各式各樣的可攜式裝置，例如智慧型手機、筆記型電腦、平板電腦、甚至是智慧型手錶或眼鏡等穿戴式電子裝置，已廣泛地應用於一般消費者的生活中。
然而，由於消費者對於可攜式裝置之要求愈來愈高，不僅希望可攜式裝置能夠提供更多功能，同時還希望其體積能更輕薄短小，因此，若可攜式裝置中之具有超小尺寸的積體電路晶片仍採用傳統的封裝方式，勢必無法滿足縮減空間之要求，且將積體電路晶片承載於載板及/或印刷電路板上時容易出現空焊(solder empty)等現象，導致產品組裝良率不佳。
有鑑於此，本發明提供一種可攜式裝置及其積體電路的封裝結構、封裝體與封裝方法，藉以解決先前技術所述及的問題。
根據本發明之一較佳具體實施例為一種積體電路的封裝體(Packaging Object)。於此實施例中，積體電路的封裝體包括晶粒及冶金層。晶粒具有接觸部、切割邊界保留部與密封環。密封環位於接觸部與切割邊界保留部之間。冶金層設置於接觸部上且至少部分設置於密封環之上。
在本發明之一實施例中，切割邊界保留部具有預設寬度， 且冶金層至少部分設置於切割邊界保留部之上。
在本發明之一實施例中，預設寬度為10微米(μm)。
在本發明之一實施例中，冶金層的外側邊緣與切割邊界保留部的外側邊緣之間的距離介於0至54微米(μm)之間。
在本發明之一實施例中，冶金層包括可焊層，可焊層可被塗佈錫膏，以耦接載板上之焊墊。
根據本發明之另一較佳具體實施例為一種積體電路的封裝結構。於此實施例中，積體電路的封裝結構包括積體電路的封裝體及載板。積體電路的封裝體包括晶粒及冶金層。晶粒具有接觸部、切割邊界保留部與密封環。密封環位於接觸部與切割邊界保留部之間。冶金層設置於接觸部上且至少部分設置於密封環之上。冶金層包括塗佈有錫膏之可焊層。載板包括焊墊。焊墊耦接塗佈有錫膏之可焊層。
在本發明之一實施例中，切割邊界保留部具有預設寬度，且冶金層至少部分設置於切割邊界保留部之上。
在本發明之一實施例中，預設寬度為10微米(μm)。
在本發明之一實施例中，冶金層的外側邊緣與切割邊界保留部的外側邊緣之間的距離介於0至54微米(μm)之間。
在本發明之一實施例中，焊墊之面積大於塗佈有錫膏之可焊層之面積。
根據本發明之另一較佳具體實施例為一種可攜式裝置。於此實施例中，可攜式裝置包括電路板及積體電路的封裝體。積體電路的封裝體包括晶粒及冶金層。晶粒具有接觸部、切割邊界保留部與密封環。密封環位於接觸部與切割邊界保留部之間。冶金層設置於接觸部上且冶金層至少部分設置於密封環之上。冶金層包括塗佈有錫膏之可焊層。載板設置有焊墊。該封裝體透過塗佈有錫膏之可焊層耦接電路板。
在本發明之一實施例中，切割邊界保留部具有預設寬度，且冶金層至少部分設置於切割邊界保留部之上。
在本發明之一實施例中，預設寬度為10微米(μm)。
在本發明之一實施例中，冶金層的外側邊緣與切割邊界保 留部的外側邊緣之間的距離介於0至54微米(μm)之間。
根據本發明之另一較佳具體實施例為一種積體電路的封裝方法。於此實施例中，積體電路的封裝方法包括下列步驟：(a)提供一晶粒，晶粒具有接觸部、切割邊界保留部與密封環，密封環位於接觸部與切割邊界保留部之間；以及(b)設置冶金層於晶粒之接觸部上，其中冶金層至少部分設置於密封環之上。
在本發明之一實施例中，切割邊界保留部具有預設寬度，且冶金層至少部分設置於切割邊界保留部之上。
在本發明之一實施例中，預設寬度為10微米(μm)。
在本發明之一實施例中，冶金層的外側邊緣與切割邊界保留部的外側邊緣之間的距離介於0至54微米(μm)之間。
相較於先前技術，根據本發明所揭露之可攜式裝置及其積體電路的封裝結構、封裝體與封裝方法是透過在積體電路的晶粒中將至少部分的冶金層(Metallurgy Layer)設置於密封環之上及/或設置於切割邊界保留部之上，使得冶金層的外側邊緣與切割邊界保留部的外側邊緣之間的距離能比現有製程中所能達到的最小距離更加縮減，進而實現超小尺寸之積體電路的封裝結構，故能廣泛應用於任何需要體積輕薄短小的可攜式裝置，例如智慧型手錶或眼鏡等穿戴式電子裝置，具有相當龐大的市場發展潛力。
關於本發明之優點與精神可以藉由以下的發明詳述及所附圖式得到進一步的瞭解。
1‧‧‧晶圓完成品
10~12‧‧‧晶粒
13‧‧‧晶圓完成品的一部分
CL‧‧‧切割線
100、110、120‧‧‧接觸部
102、112、122‧‧‧晶粒邊界
104、114、124‧‧‧密封環
106‧‧‧有效電路邊界
108、118、128‧‧‧切割邊界保留部
20‧‧‧載板
P1、P1’‧‧‧冶金層
P2‧‧‧焊墊
PL‧‧‧鈍化層
AL‧‧‧黏附層
BL‧‧‧障礙層
SL‧‧‧可焊層
ORL‧‧‧保護層
ST‧‧‧切割道
AA’‧‧‧剖面
d0~d2‧‧‧距離
S10~S20‧‧‧流程步驟
圖1繪示晶圓完成品包括多個晶粒之示意圖。
圖2A與圖2B分別繪示根據本發明之一實施例之從晶圓完成品切割出的晶粒之上視圖與側視圖。
圖2C繪示圖2B中之冶金層的放大圖。
圖3A與圖3B分別繪示載板之上視圖與側視圖。
圖4A與圖4B繪示晶粒上的焊墊與載板上的焊墊透過迴焊 方式形成電性連接之示意圖。
圖5A繪示晶粒上至少有部分的冶金層位於密封環之上的上視圖。
圖5B繪示晶粒上至少有部分的冶金層位於切割邊界保留部之上的上視圖。
圖6繪示圖5A中之晶圓完成品的一部分切割為晶粒後沿AA’的剖面圖。
圖7繪示根據本發明之另一實施例之封裝方法的流程圖。
現在將詳細參考本發明的示範性實施例，並在附圖中說明所述示範性實施例的實例。另外，在圖式及實施方式中所使用相同或類似標號的元件/構件是用來代表相同或類似部分。在下述諸實施例中，當元件被指為「連接」或「耦接」至另一元件時，其可為直接連接或耦接至另一元件，或可能存在介於其間的元件或特定材料(例如：膠體或焊料)。
根據本發明之一較佳具體實施例為一種積體電路的封裝結構。於此實施例中，積體電路的封裝結構包括積體電路的封裝體與載板。上述積體電路的封裝體包括由晶圓完成品(Finished Wafer)切割出來的晶粒，晶粒具有積體電路。載板用以承載封裝該晶粒之封裝體，但不以此為限。在本發明的一實施例中，上述晶粒中的積體電路可以是功率型金屬氧化物半導體場效應晶體(Power MOSFET)、穩壓器(LDO)或其他低接腳數的積體電路，但上述積體電路不以此為限。
需說明的是，上述載板通常可稱為IC基板或IC載板，主要功能為承載晶粒做為載體之用，並以載板之內部線路連接晶粒與印刷電路板(PCB)之間的訊號，主要為保護電路、固定線路與導散餘熱，為封裝製程中的關鍵零件。於實際應用中，上述載板之材質可視實際需求採用印刷電路板、陶瓷載板、塑膠載板、金屬載板或卷帶載板，並無特定之限制。
請參照圖1，圖1繪示晶圓完成品包括多個晶粒之示意 圖。如圖1所示，晶圓完成品(Finished Wafer)1包括有多個晶粒(Dies)10，該些晶粒10上通常會具有各種不同形式或功能之積體電路，但不以此為限。實際上，可透過適當的晶粒切割器沿著晶圓完成品1上的切割線CL進行切割，以切割出該些晶粒10。需說明的是，由於晶粒切割器之刀具通常會具有一定的厚度(寬度)，例如：15~20微米(μm)，所以一般會設計有切割道ST，其具有一預設切割道寬度，例如50微米(μm)，以避免刀具進行切割時產生偏差而造成晶粒10內部電路之損傷。
接著，請參照圖2A與圖2B，圖2A與圖2B分別繪示從圖1中之晶圓完成品1切割出的晶粒10之上視圖與側視圖。如圖2A與圖2B所示，晶粒10具有接觸部100、晶粒邊界102、密封環104、有效電路邊界106、切割邊界保留部108與冶金層(Metallurgy Layer)P1。
接觸部100位於有效電路邊界106內的有效電路區域裡。切割邊界保留部108為刀具沿著晶圓完成品1上之切割道ST切割出晶粒10後還保留在晶粒10上之部分的切割道，通常切割邊界保留部108會具有10微米(μm)之預設寬度，但不以此為限。切割邊界保留部108位於晶粒邊界102與密封環104之間。密封環104位於接觸部100與切割邊界保留部108之間。在本發明之一實施例中，密封環104的寬度可為25微米(μm)。在本發明之一實施例中，冶金層P1設置於接觸部100上，並且至少有部分的冶金層P1會位於密封環104之上。
需說明的是，晶粒10上之接觸部100(凸塊)通常是晶片封裝體的接腳(pin)與晶粒10內部積體電路的溝通媒介。此外，本實施例中的晶粒10可應用於輕薄短小的可攜式裝置，因此晶粒10需具有超小的尺寸，在本實施例中，晶粒10上所設置的接觸部100數目至多為16個，較佳為3個至8個，但不以此為限。
於此實施例中，如圖2A所示，假設接觸部100的外側邊緣與晶粒邊界102之間的距離為d0，冶金層P1的外側邊緣與切割邊界保留部108的外側邊緣(亦即晶粒邊界102)之間的距離為d1，由於傳統的冶金層的外側邊緣至多只形成在接觸部100的外側邊緣上方。也就是說，傳統冶金層的外側邊緣與晶粒邊界之間的距離d0最小為55微米(μm)。然而，在本 實施例中，冶金層P1的外側邊緣會延伸形成在密封環104之上。因此，在本實施例中，d1會小於55微米(μm)，通常是介於0至55微米(μm)之間，在本發明之一實施例中，d1是介於0至54微米(μm)之間，在其他實施例中，d1最佳是介於10至54微米(μm)之間，但不以此為限。
此外，從圖2C所繪示的放大圖可知，晶粒10的接觸部100周圍設置有鈍化層(Passivation Layer)PL，用以隔離並避免接觸部100與外部電性連接。冶金層P1設置於晶粒10的接觸部100及鈍化層PL上。在本實施例中，冶金層P1可為球下冶金(Under Bump Metallurgy，UBM)層，其又可稱為多層金屬層，於此實施例中，作為UBM層的冶金層P1可包括黏附層(Adhesion Layer)AL、障礙層(Barrier Layer)BL、可焊層(Solderable Layer)SL與保護層(Oxidation Resistance Layer)ORL。在其他實施例中，冶金層P1亦可包括至少一層金屬層或至少一層可焊層，本發明並不對此加以限制。
黏附層AL形成於晶粒10的接觸部100及鈍化層PL上，用以與接觸部100與鈍化層PL形成較強的連結；障礙層BL形成於黏附層AL上，用以防止接觸部100與可焊層SL之間的擴散發生。實際上，黏附層AL與障礙層BL之材質可以是鉻(Cr)、鈦(Ti)、鈦/鎢(Ti/W)、鎳(Ni)、鈀(Pd)或鉬(Mo)，其厚度約為0.15~0.2mm，但不以此為限。
可焊層SL形成於障礙層BL上，用以供銲錫在迴焊(Reflow)時可完全滯留附立其上而成球狀。實際上，可焊層SL的材質可以是銅(Cu)、鎳(Ni)或鈀(Pd)，其厚度約為1~5mm，但不以此為限。於此實施例中，可焊層SL上可塗佈有錫膏(Solder Paste)，以使得晶粒10能夠與載板或電路板形成電性連接。在本發明之一實施例中，可焊層SL之厚度大於障礙層BL之厚度，但不以此為限。
保護層ORL形成於可焊層SL上，用以保護其下方的黏附層AL、障礙層BL及可焊層SL，以避免這些金屬層被氧化。實際上，保護層ORL的材質通常為金(Au)，其厚度約為0.05~0.1mm，但不以此為限。
請參照圖3A與圖3B，圖3A與圖3B分別繪示載板之上視圖與側視圖。如圖3A與圖3B所示，載板20上設置有焊墊P2。為了比較載板20上之焊墊P2與晶粒10上之冶金層P1，圖3A中以虛線繪示出晶粒 10及其冶金層P1。需說明的是，由於載板20用以承載晶粒10，所以載板20上所設置之焊墊P2會對應於晶粒10上之冶金層P1，但載板20上所設置之焊墊P2的面積會稍大於晶粒10上之冶金層P1的面積，使得圖2C所示之晶粒10上之塗佈有錫膏的可焊層SL與圖3B所示之載板20上的焊墊P2在如圖4B所示透過迴焊(Reflow)方式耦接在一起(如圖4B中之斜線部分所示)而形成電性連接時，較不易產生空焊(solder empty)之現象。
藉此，晶粒10便可承載於載板20上並且彼此電性連接。根據圖3A與圖4A可知，由於載板20上所設置之焊墊P2面積較大，會有部分的焊墊P2位於晶粒10的晶粒邊界(虛線)102之外，再加上晶粒10上的冶金層P1相當靠近晶粒邊界102，因此，當晶粒10上之冶金層P1與載板20上的焊墊P2透過迴焊方式耦接在一起時，如圖4B所示，載板20上會有些許熱融的焊墊P2與晶粒10之一側部分耦接。
接著，承載晶粒10的載板20可設置於可攜式裝置中之一印刷電路板(PCB)或主機板上並與印刷電路板電性連接，使得載板20能透過其內部線路連接晶粒10與印刷電路板之間的訊號，藉此可攜式裝置可透過印刷電路板與載板20控制晶粒10上之有效電路區域中之積體電路執行某一功能。在其他實施例中，晶粒10也可以透過冶金層P1與塗佈在治金層P1的可焊層SL的錫膏來耦接可攜式裝置中的印刷電路板上的焊墊。
接著，請參照圖5A，圖5A繪示圖1之晶圓完成品1的一部分13中之晶粒11與12上至少有部分的冶金層位於密封環之上的上視圖。如圖5A所示，晶圓完成品1的一部分13上之切割線CL的兩側為切割道ST。切割道ST的左邊與右邊分別為晶粒11的晶粒邊界112與晶粒12的晶粒邊界122。
於晶粒12中，晶粒12具有接觸部120、晶粒邊界122、密封環124、切割邊界保留部128與冶金層P1。切割邊界保留部128位於晶粒邊界122與密封環124之間。密封環124位於切割邊界保留部128與接觸部120之間。冶金層P1設置於接觸部120上，並且至少有部分的冶金層P1會延伸至密封環124之上而位於密封環124之上。
於實際應用中，假設接觸部120的外側邊緣與晶粒邊界122 之間的距離為d0，冶金層P1的外側邊緣與晶粒邊界122(亦即切割邊界保留部128的外側邊緣)之間的距離為d1，由於傳統的冶金層的外側邊緣通常會切齊接觸部的外側邊緣，亦即d0即為傳統的冶金層的外側邊緣與晶粒邊界之間的距離55微米(μm)，至於本實施例之冶金層P1的外側邊緣會延伸至密封環124之上，因此，d1會小於d0，通常是介於0至54微米(μm)之間，最佳是介於10至54微米(μm)之間，但不以此為限。
同理，於晶粒11中，晶粒11具有接觸部110、晶粒邊界112、密封環114、切割邊界保留部118與冶金層P1。切割邊界保留部118位於晶粒邊界112與密封環114之間。密封環114位於切割邊界保留部118與接觸部110之間。冶金層P1設置於接觸部110上，並且至少有部分的冶金層P1會延伸至密封環114之上而位於密封環114之上，使得接觸部110的外側邊緣與晶粒邊界112之間的距離會小於冶金層P1的外側邊緣與晶粒邊界112(亦即切割邊界保留部118的外側邊緣)之間的距離55微米(μm)，通常是介於0至54微米(μm)之間，最佳是介於10至54微米(μm)之間，但不以此為限。
需說明的是，於上述圖5A的實施例中，晶粒上的冶金層至少會有一部分延伸至密封環之上而位於密封環之上。於實際應用中，晶粒上的冶金層亦可至少有一部分延伸至切割邊界保留部之上而位於切割邊界保留部之上。
如圖5B所示，於晶粒12中，假設接觸部120的外側邊緣與晶粒邊界122之間的距離為d0，冶金層P1’的外側邊緣與晶粒邊界122(亦即切割邊界保留部128的外側邊緣)之間的距離為d2，由於傳統的冶金層的外側邊緣通常會切齊接觸部120的外側邊緣，亦即d0即為傳統的冶金層的外側邊緣與晶粒邊界之間的距離55微米(μm)，至於本案之冶金層P1’的外側邊緣會延伸至切割邊界保留部128之上，因此，d2會小於55微米(μm)，通常是介於0至54微米(μm)之間，最佳是介於2至54微米(μm)之間，但不以此為限。至於圖5B中之晶粒11，由於晶粒11與晶粒12情況相同，故於此不另行贅述。
比較圖5A與圖5B可知：由於圖5A中之晶粒12有部分的 冶金層P1會延伸至密封環124之上而位於密封環124之上，而圖5B中之晶粒12有部分的冶金層P1’會延伸至切割邊界保留部128之上而位於切割邊界保留部128之上，並且切割邊界保留部128比密封環124更靠近晶粒邊界122，亦即圖5B中之冶金層P1’的外側邊緣會比圖5A中之冶金層P1的外側邊緣更靠近晶粒邊界122，因此，圖5B中之冶金層P1’的外側邊緣與晶粒邊界122之間的距離d2會小於圖5A中之冶金層P1的外側邊緣與晶粒邊界122之間的距離d1。
請參照圖6，圖6繪示將圖5中之晶圓完成品1的部分13切割為晶粒12後沿AA’的剖面圖。如圖6所示，切割邊界保留部128位於晶粒邊界122與密封環124之間，而密封環124位於切割邊界保留部128與接觸部120之間。鈍化層PL形成於接觸部120及密封環124之上，用以隔離並避免接觸部120與外部電性連接。保護層PL上形成有一開孔，使得部分的接觸部120暴露出來，而能讓冶金層P1設置於接觸部120與保護層PL上，並且至少有部分的冶金層P1會位於密封環124之上。
根據本發明之另一較佳具體實施例為一種積體電路的封裝方法。於此實施例中，該積體電路的封裝方法用以形成應用於可攜式裝置中之具有積體電路之一晶粒的封裝結構，但不以此為限。至於可攜式裝置可以是智慧型手機、平板電腦、甚至是穿戴式的智慧型手錶或眼鏡等，並無特定之限制。
請參照圖7，圖7繪示此實施例之積體電路的封裝方法的流程圖。如圖7所示，於步驟S10中，該封裝方法提供一晶粒。於此實施例中，晶粒具有接觸部、切割邊界保留部與密封環。密封環位於接觸部與切割邊界保留部之間。
於步驟S12中，該封裝方法設置冶金層於晶粒之接觸部上，其中冶金層至少部分設置於密封環之上。於此實施例中，冶金層可依序包括連接接觸部之黏附層、障礙層、可焊層與塗佈於可焊層上之錫膏。於一實施例中，可焊層之厚度大於障礙層之厚度，但不以此為限。
於步驟S14中，該封裝方法提供設置有焊墊之載板。於步驟S16中，該封裝方法耦接焊墊與塗佈有錫膏之可焊層，致使載板承載封裝體 而形成積體電路的封裝結構。於此實施例中，步驟S16可透過迴焊方式耦接焊墊與塗佈有錫膏之可焊層，但不以此為限。
於步驟S18中，該封裝方法提供設置於可攜式裝置內之電路板。於步驟S20中，該封裝方法將步驟S16所完成之封裝結構設置於電路板上並與電路板電性連接，以供可攜式裝置能透過電路板與載板控制晶粒上之有效電路區域中之積體電路執行特定功能。
相較於先前技術，根據本發明所揭露之可攜式裝置及其積體電路的封裝結構、封裝體與封裝方法是透過在積體電路的晶粒中將至少部分的球下金屬層(Under Bump Metallurgy,UBM)設置於密封環之上及/或設置於切割邊界保留部之上，使得球下金屬層的外側邊緣與切割邊界保留部的外側邊緣之間的距離能比現有製程中所能達到的最小距離更加縮減，進而實現超小尺寸之積體電路的封裝結構，故能廣泛應用於任何需要體積輕薄短小的可攜式裝置，例如智慧型手錶或眼鏡等穿戴式電子裝置，具有相當龐大的市場發展潛力。
藉由以上較佳具體實施例之詳述，係希望能更加清楚描述本發明之特徵與精神，而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地，其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。
12‧‧‧晶粒
120‧‧‧接觸部
122‧‧‧晶粒邊界
124‧‧‧密封環
128‧‧‧切割邊界保留部
P1‧‧‧冶金層
PL‧‧‧鈍化層

Claims (14)

  1. 一種積體電路的封裝體(Packaging Object)，包括：一晶粒(Die)，具有一接觸部、一切割邊界保留部與一密封環(Seal Ring)，其中該密封環位於該接觸部與該切割邊界保留部之間；以及一冶金層，設置於該接觸部上且至少部分設置於該密封環之上，且該冶金層的外側邊緣與該切割邊界保留部的外側邊緣之間的一距離介於0至54微米(μm)之間。
  2. 如申請專利範圍第1項所述的封裝體，其中該切割邊界保留部具有一預設寬度，且該冶金層至少部分設置於該切割邊界保留部之上。
  3. 如申請專利範圍第2項所述的封裝體，其中該預設寬度為10微米(μm)。
  4. 如申請專利範圍第1項所述的封裝體，其中該冶金層包括一可焊層，該可焊層可被塗佈一錫膏，以耦接一載板上之一焊墊。
  5. 一種積體電路的封裝結構，包括：積體電路的封裝體，包括：一晶粒，具有一接觸部、一切割邊界保留部與一密封環，其中該密封環位於該接觸部與該切割邊界保留部之間；以及一冶金層，設置於該接觸部上且該冶金層至少部分設置於該密封環之上，該冶金層包括塗佈有一錫膏之一可焊層，且該冶金層的外側邊緣與該切割邊界保留部的外側邊緣之間的一距離介於0至54微米(μm)之間；以及一載板，包括一焊墊，該焊墊耦接塗佈有該錫膏之該可焊層。
  6. 如申請專利範圍第5項所述的封裝結構，其中該切割邊界保留部具有一預設寬度，且該冶金層至少部分設置於該切割邊界保留部之上。
  7. 如申請專利範圍第6項所述的封裝結構，其中該預設寬度為10微米(μm)。
  8. 如申請專利範圍第5項所述的封裝結構，其中該焊墊之面積大於塗佈有該錫膏之該可焊層之面積。
  9. 一種可攜式裝置，包括：一電路板；以及一積體電路的封裝體，包括：一晶粒，具有一接觸部、一切割邊界保留部與一密封環，其中該密封環位於該接觸部與該切割邊界保留部之間；以及一冶金層，設置於該接觸部上且至少部分設置於該密封環之上，該冶金層包括塗佈有一錫膏之一可焊層，其中該封裝體透過塗佈有該錫膏之該可焊層耦接該電路板，且該冶金層的外側邊緣與該切割邊界保留部的外側邊緣之間的一距離介於0至54微米(μm)之間。
  10. 如申請專利範圍第9項所述的可攜式裝置，其中該切割邊界保留部具有一預設寬度，且該冶金層至少部分設置於該切割邊界保留部之上。
  11. 如申請專利範圍第10項所述的可攜式裝置，其中該預設寬度為10微米(μm)。
  12. 一種積體電路的封裝方法，包括下列步驟：(a)提供一晶粒，該晶粒具有一接觸部、一切割邊界保留部與一密封環， 該密封環位於該接觸部與該切割邊界保留部之間；以及(b)設置一冶金層於該晶粒之該接觸部上，其中該冶金層至少部分設置於該密封環之上，且該冶金層的外側邊緣與該切割邊界保留部的外側邊緣之間的一距離介於0至54微米(μm)之間。
  13. 如申請專利範圍第12項所述的封裝方法，其中該切割邊界保留部具有一預設寬度，且該冶金層至少部分設置於該切割邊界保留部之上。
  14. 如申請專利範圍第13項所述的封裝方法，其中該預設寬度為10微米(μm)。
TW103125569A 2014-07-25 2014-07-25 可攜式裝置及其積體電路的封裝結構、封裝體與封裝方法 TWI559413B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW103125569A TWI559413B (zh) 2014-07-25 2014-07-25 可攜式裝置及其積體電路的封裝結構、封裝體與封裝方法
CN201410443444.2A CN105280578B (zh) 2014-07-25 2014-09-03 可携式装置及其集成电路的封装结构、封装体与封装方法
US14/732,086 US9443809B2 (en) 2014-07-25 2015-06-05 Portable apparatus, IC packaging structure, IC packaging object, and IC packaging method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW103125569A TWI559413B (zh) 2014-07-25 2014-07-25 可攜式裝置及其積體電路的封裝結構、封裝體與封裝方法

Publications (2)

Publication Number Publication Date
TW201604975A TW201604975A (zh) 2016-02-01
TWI559413B true TWI559413B (zh) 2016-11-21

Family

ID=55149354

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103125569A TWI559413B (zh) 2014-07-25 2014-07-25 可攜式裝置及其積體電路的封裝結構、封裝體與封裝方法

Country Status (3)

Country Link
US (1) US9443809B2 (zh)
CN (1) CN105280578B (zh)
TW (1) TWI559413B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108346952B (zh) * 2018-01-25 2020-11-24 番禺得意精密电子工业有限公司 电连接器固持装置
KR102075764B1 (ko) * 2018-03-28 2020-02-10 한국과학기술원 이종 광 집적회로 및 이의 제조 방법
CN110875396B (zh) * 2018-08-31 2023-08-15 力智电子股份有限公司 沟槽式栅极金氧半场效晶体管及其制造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110037163A1 (en) * 2009-08-13 2011-02-17 Infineon Technologies Ag Device including a ring-shaped metal structure and method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5648661A (en) 1992-07-02 1997-07-15 Lsi Logic Corporation Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies
US6495917B1 (en) * 2000-03-17 2002-12-17 International Business Machines Corporation Method and structure of column interconnect
US6692629B1 (en) 2000-09-07 2004-02-17 Siliconware Precision Industries Co., Ltd. Flip-chip bumbing method for fabricating solder bumps on semiconductor wafer
US7633152B2 (en) * 2005-09-02 2009-12-15 Agere Systems Inc. Heat dissipation in integrated circuits
US8829663B2 (en) * 2007-07-02 2014-09-09 Infineon Technologies Ag Stackable semiconductor package with encapsulant and electrically conductive feed-through
US8519513B2 (en) 2012-01-04 2013-08-27 Freescale Semiconductor, Inc. Semiconductor wafer plating bus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110037163A1 (en) * 2009-08-13 2011-02-17 Infineon Technologies Ag Device including a ring-shaped metal structure and method

Also Published As

Publication number Publication date
US9443809B2 (en) 2016-09-13
CN105280578B (zh) 2018-06-01
CN105280578A (zh) 2016-01-27
US20160027742A1 (en) 2016-01-28
TW201604975A (zh) 2016-02-01

Similar Documents

Publication Publication Date Title
TWI541961B (zh) 具有熱增強型共形屏蔽之半導體封裝及相關方法
KR100520660B1 (ko) 반도체 웨이퍼와 반도체장치 및 그 제조방법
TWI251886B (en) Sensor chip for defining molding exposed region and method for manufacturing the same
KR102107961B1 (ko) 반도체 장치 및 이의 제조 방법
TW588445B (en) Bumpless chip package
TWI559413B (zh) 可攜式裝置及其積體電路的封裝結構、封裝體與封裝方法
TWI595574B (zh) 電子裝置及其積體電路的封裝體
US8877555B2 (en) Flip-chip semiconductor chip packing method
TWI252572B (en) Package structure
JP2003124274A (ja) 半導体ウェハーならびに半導体装置およびその製造方法
KR20170044919A (ko) 반도체 패키지 및 이의 제조 방법
US10269583B2 (en) Semiconductor die attachment with embedded stud bumps in attachment material
JPH06120294A (ja) 化合物半導体装置及びその製造方法及びその実装方法
KR102133448B1 (ko) 반도체 패키지
TWI615928B (zh) 封裝結構及其製法
US20210066162A1 (en) Semiconductor package with attachment and/or stop structures
US20100102429A1 (en) Flip-chip package structure with block bumps and the wedge bonding method thereof
US10157873B1 (en) Semiconductor package including bump
CN111554631A (zh) 一种芯片封装方法
US9735132B1 (en) Semiconductor package
US11552014B2 (en) Semiconductor package structure and method of making the same
TW201841319A (zh) 用於銲線接合應用之封裝結構中的中介層設計
JP2006049602A (ja) 半導体装置およびその製造方法
CN112864022B (zh) 封装结构的制作方法及封装结构
US20220238425A1 (en) Semiconductor package structure