JP6686040B2 - ダイ間相互接続用ブリッジモジュールを有する半導体アセンブリ - Google Patents
ダイ間相互接続用ブリッジモジュールを有する半導体アセンブリ Download PDFInfo
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- JP6686040B2 JP6686040B2 JP2017549670A JP2017549670A JP6686040B2 JP 6686040 B2 JP6686040 B2 JP 6686040B2 JP 2017549670 A JP2017549670 A JP 2017549670A JP 2017549670 A JP2017549670 A JP 2017549670A JP 6686040 B2 JP6686040 B2 JP 6686040B2
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Description
Claims (11)
- パッケージ基板と、
第1の集積回路(IC)ダイであって、そのトップ面に、複数の相互接続部のうちの第1の相互接続部及び複数のダイ間コンタクトのうちの第1のダイ間コンタクトを有し、前記第1の相互接続部が、前記パッケージ基板のトップ面に電気的及び機械的に結合されている、第1のICダイと、
第2のICダイであって、そのトップ面に、前記複数の相互接続部のうちの第2の相互接続部及び前記複数のダイ間コンタクトのうちの第2のダイ間コンタクトを有し、前記第2の相互接続部が、前記パッケージ基板の前記トップ面に電気的及び機械的に結合されている、第2のICダイと、
前記第1の相互接続部と前記第2の相互接続部との間に配置されたブリッジモジュールであって、前記ブリッジモジュールの背面が、前記パッケージ基板に電気的に接続されておらず、且つ前記複数の相互接続部の高さを超えて延びておらず、前記ブリッジモジュールは、
前記複数のダイ間コンタクトに機械的及び電気的に結合された、前記ブリッジモジュールのトップ面のブリッジ相互接続部と、
前記ブリッジモジュールの前記トップ面に配置され、前記第1のICダイと前記第2のICダイとの間で信号をルーティングするように構成された、導電性相互接続部の1つ以上の層と
を含む、ブリッジモジュールと、
前記第1のICダイ、前記第2のICダイ、及び前記ブリッジモジュールの前記背面の各々と前記パッケージ基板の前記トップ面との間に配置されたアンダーフィルと、
前記第1のICダイを前記第2のICダイにボンディングし、前記ブリッジモジュールを前記第1のICダイ及び前記第2のICダイの各々にボンディングするエポキシと
を備える集積回路(IC)パッケージ。 - 前記ブリッジモジュールが、前記パッケージ基板から離れている基板を備える、請求項1に記載のICパッケージ。
- 前記ブリッジモジュールが、能動回路を含む半導体基板を備える、請求項1又は2に記載のICパッケージ。
- 前記ブリッジモジュールが、セラミック基板、有機基板、又は半導体基板を備える、請求項1から3のいずれか一項に記載のICパッケージ。
- 前記パッケージ基板が、その背面に複数の相互接続部を備える、請求項1から4のいずれか一項に記載のICパッケージ。
- 半導体アセンブリを製造する方法であって、
キャリア基板であって、キャビティ及びその上に配置されたリリース層を有するキャリア基板を形成することと、
前記キャビティの1つにブリッジモジュールを配置することであって、前記ブリッジモジュールが、そのトップ面のブリッジ相互接続部と、前記そのトップ面に配置された導電性相互接続部の1つ以上の層とを含む、配置することと、
第1の集積回路(IC)ダイを前記キャリア基板上に配置し、その第1の相互接続部が複数の前記キャビティに配置されるようにすることと、
第2のICダイを前記キャリア基板上に配置し、その第2の相互接続部が複数の前記キャビティに配置されるようにすることと、
前記ブリッジ相互接続部を前記第1のICダイ及び前記第2のICダイのダイ間コンタクトに結合することと、
前記リリース層を離すことによって、前記第1のICダイ、前記第2のICダイ、及び前記ブリッジモジュールを備える半導体アセンブリを前記キャリア基板から分離することと、
前記第1のICダイの前記第1の相互接続部及び前記第2のICダイの前記第2の相互接続部が、パッケージ基板のトップ面に電気的及び機械的に結合されるように、前記パッケージ基板上に前記半導体アセンブリを実装することと、
前記第1のICダイ、前記第2のICダイ、及び前記ブリッジモジュールの背面の各々と前記パッケージ基板の前記トップ面との間にアンダーフィルを堆積させることと
を含み、
前記ブリッジモジュールの背面が、前記パッケージ基板に電気的に接続されておらず、前記第1の相互接続部及び前記第2の相互接続部の高さを超えて延びていない、方法。 - 分離するステップの前に、前記第1のICダイを前記第2のICダイにボンディングし、前記ブリッジモジュールを前記第1のICダイ及び前記第2のICダイの各々にボンディングするエポキシを形成すること
を更に含む、請求項6に記載の方法。 - 分離するステップの前に、前記第1のICダイ、前記第2のICダイ、及び前記ブリッジモジュールを、モールディングコンパウンドに封入することをさらに含む、請求項6に記載の方法。
- 前記ブリッジモジュールが、能動回路を含む半導体基板を備える、請求項6から8のいずれか一項に記載の方法。
- 結合するステップが、
前記ブリッジ相互接続部を前記ダイ間コンタクトにはんだ付けすること、又は
熱圧着プロセスを使用して前記ブリッジ相互接続部を前記ダイ間コンタクトにボンディングすること
を含む、請求項6から9のいずれか一項に記載の方法。 - 集積回路(IC)パッケージであって、
パッケージ基板と、
第1の集積回路(IC)ダイであって、そのトップ面に、複数の相互接続部のうちの第1の相互接続部及び複数のダイ間コンタクトのうちの第1のダイ間コンタクトを有し、前記第1の相互接続部が、前記パッケージ基板のトップ面に電気的及び機械的に結合されている、第1のICダイと、
第2のICダイであって、そのトップ面に、前記複数の相互接続部のうちの第2の相互接続部及び前記複数のダイ間コンタクトのうちの第2のダイ間コンタクトを有し、前記第2の相互接続部が、前記パッケージ基板の前記トップ面に電気的及び機械的に結合されている、第2のICダイと、
前記第1の相互接続部と前記第2の相互接続部との間に配置されたブリッジモジュールであって、前記ブリッジモジュールの背面が、前記パッケージ基板に電気的に接続されておらず、且つ前記複数の相互接続部の高さを超えて延びておらず、前記ブリッジモジュールは、
前記複数のダイ間コンタクトに機械的及び電気的に結合された、前記ブリッジモジュールのトップ面のブリッジ相互接続部と、
前記ブリッジモジュールの前記トップ面に配置され、前記第1のICダイと前記第2のICダイとの間で信号をルーティングするように構成された、導電性相互接続部の1つ以上の層と
を含む、ブリッジモジュールと、
前記第1のICダイ、前記第2のICダイ、及び前記ブリッジモジュールの前記背面の各々と前記パッケージ基板の前記トップ面との間に配置されたアンダーフィルと、
前記第1のICダイ、前記第2のICダイ、及び前記ブリッジモジュールを封入するモールディングコンパウンドと
を備える、集積回路(IC)パッケージ。
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