CN114068514A - 半导体封装件及其制造方法 - Google Patents
半导体封装件及其制造方法 Download PDFInfo
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- CN114068514A CN114068514A CN202110890563.2A CN202110890563A CN114068514A CN 114068514 A CN114068514 A CN 114068514A CN 202110890563 A CN202110890563 A CN 202110890563A CN 114068514 A CN114068514 A CN 114068514A
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Abstract
一种半导体封装件和关联的方法,所述封装件包括:衬底;第一半导体芯片和第二半导体芯片,其位于衬底上;以及外部端子,其位于衬底下方,其中,衬底包括:核心部分;第一堆积部分和第二堆积部分,其位于核心部分的顶表面和底表面上,第一堆积部分和第二堆积部分包括电介质图案和线图案;以及插入器芯片,其位于核心部分中的嵌入区中,并且电连接至第一堆积部分和第二堆积部分,插入器芯片包括基体层;重新分布层,其位于基体层上;以及过孔件,其穿透基体层,过孔件连接至重新分布层,并且在基体层的表面处被暴露,重新分布层连接至第一堆积部分的线图案,并且过孔件连接至第二堆积部分的线图案。
Description
相关申请的交叉引用
标题为“半导体封装件及其制造方法”的于2020年8月7日在韩国知识产权局提交的韩国专利申请No.10-2020-0099253以引用方式全部并入本文中。
技术领域
实施例涉及一种半导体封装件及其制造方法。
背景技术
随着电子工业的开发,电子产品已日益展现出高性能、高速度和紧凑的尺寸。为了适应这种趋势,已经考虑了其中将多个半导体芯片安装在单个封装件中的封装技术。
可以提供半导体封装件来实施集成电路芯片以有资格在电子产品中使用。
发明内容
可以通过提供半导体封装件来实现实施例,该半导体封装件包括:衬底;第一半导体芯片和第二半导体芯片,其安装在衬底上;以及多个外部端子,其位于衬底下方,其中,衬底包括:核心部分;第一堆积部分和第二堆积部分,其分别位于核心部分的顶表面和底表面上,第一堆积部分和第二堆积部分中的每一个包括电介质图案和线图案;以及插入器芯片,其位于核心部分中的嵌入区中,并且电连接至第一堆积部分和第二堆积部分,其中,插入器芯片包括:基体层;重新分布层,其位于基体层的第一表面上;以及过孔件,其穿透基体层,过孔件连接至重新分布层,并且在基体层的第二表面处被暴露,其中,重新分布层连接至第一堆积部分的线图案,并且其中,过孔件连接至第二堆积部分的线图案。
可以通过提供半导体封装件来实现实施例,所述半导体封装件包括:第一布线层;第二布线层,其位于第一布线层上;插入器芯片,其位于第一布线层与第二布线层之间;绝缘层,其位于第一布线层与第二布线层之间,绝缘层围绕插入器芯片;导电元件,其位于第一布线层与第二布线层之间,导电元件与插入器芯片间隔开,并且将第一布线层连接至第二布线层;第一半导体芯片和第二半导体芯片,其安装在第二布线层上;模制层,其位于第二布线层上,模制层覆盖第一半导体芯片和第二半导体芯片;以及多个外部端子,其位于第一布线层下方,其中,插入器芯片包括:基体层;重新分布层,其位于基体层上,并且耦接至第二布线层;以及过孔件,其位于基体层中,过孔件将重新分布层连接至第一布线层,并且其中,第一半导体芯片和第二半导体芯片通过插入器芯片彼此电连接。
可以通过提供制造半导体封装件的方法来实现实施例,所述方法包括:形成插入器芯片,插入器芯片包括基体层、基体层的第一表面上的重新分布层和穿透基体层的过孔件,过孔件连接至重新分布层,并且在基体层的第二表面上被暴露;将插入器芯片提供到核心部分中,核心部分包括导电元件;在核心部分的顶表面和基体层的第一表面上形成第一堆积部分,第一堆积部分连接至导电元件和重新分布层;在核心部分的底表面和基体层的第二表面上形成第二堆积部分,第二堆积部分连接至导电元件和过孔件;在第一堆积部分上安装多个半导体芯片;以及在第一堆积部分上形成覆盖多个半导体芯片的模制层,其中,多个半导体芯片通过第一堆积部分和插入器芯片彼此电连接。
附图说明
通过参照附图详细地描述示例性实施例,特征对于本领域技术人员而言将变得显而易见,在附图中:
图1是根据一些示例实施例的半导体封装件的截面图。
图2是示出图1的部分A的放大图。
图3至图5是根据一些示例实施例的半导体封装件的截面图。
图6至图11是根据一些示例实施例的制造插入器芯片的方法中的阶段的截面图。
图12至图17是根据一些示例实施例的制造半导体封装件的方法中的阶段的截面图。
图18至图21是根据一些示例实施例的制造半导体封装件的方法中的阶段的截面图。
具体实施方式
图1是根据一些示例实施例的半导体封装件的截面图。图2是示出图1的部分A的放大图。图3是根据一些示例实施例的半导体封装件的截面图。
参照图1和图2,半导体封装件1可以包括布线衬底100、安装在布线衬底100上的第一半导体芯片200和第二半导体芯片300以及覆盖布线衬底100上的第一半导体芯片200和第二半导体芯片300的模制层400。
可以提供布线衬底100。布线衬底100可以包括核心部分110、核心部分110中的插入器芯片120、核心部分110的一个表面(例如,顶表面)上的上堆积部分130以及核心部分110的另一表面(例如,底表面)上的下堆积部分140。
核心部分110可以在一个方向(例如,纵向)上延伸。核心部分110可以包括在平面中观看时去除其一部分的核心图案。从其去除该部分的区CA可以与如以下讨论的设置有插入器芯片120的嵌入区CA对应。嵌入区CA可以形成为如开孔的形状,该开孔将核心部分110的顶表面和底表面彼此连接(例如,完全延伸穿过核心部分110)。在实施方式中,核心部分110可以包括一个核心图案。在实施方式中,核心部分110可以包括两个或更多个核心图案。在实施方式中,布线衬底100可以包括在平面中观看时彼此间隔开的多个核心图案。核心部分110可以包括电介质材料。在实施方式中,核心部分110可以包括玻璃纤维、陶瓷板、环氧树脂或树脂。在实施方式中,核心部分110可以包括不锈钢、铝(Al)、镍(Ni)、镁(Mg)、锌(Zn)、钽(Ta)或它们的任意组合。如本文中使用的,术语“或”不是排他性的术语,例如,“A或B”将包括A、B或者A和B。
核心部分110可以包括核心电介质图案112和核心导电图案114(例如,核心电介质图案112中的布线图案)。在实施方式中,核心电介质图案112可以包括氧化硅(例如,SiO2)。核心导电图案114可以与嵌入区CA间隔开。在实施方式中,核心部分110可以在其外侧处具有位于嵌入区CA外部的核心导电图案114。核心导电图案114可以包括上核心焊盘115、核心布线116和下核心焊盘117。上核心焊盘115可以位于核心部分110的顶表面上。上核心焊盘115可以电连接至以下将讨论的上堆积部分130。下核心焊盘117可以位于核心部分110的下部上。下核心焊盘117可以电连接至以下将讨论的下堆积部分140。上核心焊盘115和下核心焊盘117可以具有大约10μm至大约20μm的厚度。核心布线116可以将上核心焊盘115电连接至下核心焊盘117。核心保护层119还可以设置在核心部分110的核心电介质图案112的底表面上,从而覆盖下核心焊盘117。在实施方式中,可以省略核心保护层119。在实施方式中,下核心焊盘117可以在核心部分110的底表面上被暴露。
在实施方式中,如图1中所示,核心导电图案114可以形成为埋置在多个堆叠的核心电介质图案112中。在实施方式中,如图3中所示,核心部分110’可以包括单层核心电介质图案112,并且替代图1中示出的核心导电图案114,贯穿电极114-1可以竖直地穿透核心电介质图案112。贯穿电极114-1可以从核心电介质图案112的顶表面延伸至底表面。上核心焊盘115可以耦接至贯穿电极114-1的顶表面,下核心焊盘117可以耦接至贯穿电极114-1的底表面。下面的描述将集中在图1和图2中示出的实施例上。
插入器芯片120可以位于核心部分110的嵌入区CA中。核心部分110可以包括从其去除核心图案的部分处的嵌入区CA。嵌入区CA可以在核心部分110的顶表面和底表面上或在核心部分110的顶表面和底表面处被暴露。在实施方式中,嵌入区CA可以形成为如从核心部分110的顶表面朝向核心部分110的底表面延伸的通孔的形状。在实施方式中,嵌入区CA可以具有朝向核心部分110的内部延伸的凹陷形状。在此情况下,嵌入区CA可以具有与核心保护层119对应的底表面。
插入器芯片120可以包括基体层121、基体层121上的重新分布层123和基体层121中的过孔件126。
基体层121可以包括硅(Si)。基体层121可以具有大约70μm至大约300μm的厚度。芯片保护层122可以覆盖基体层121的底表面121b。芯片保护层122可以是基体层121的下部的部分区段。在实施方式中,芯片保护层122可以是当基体层121的下部被部分地氧化时形成的部件。
插入器芯片120可以具有顶表面和底表面。在以下的该描述中,语言“顶表面”可以被限定为指其上形成有插入器芯片120的布线线图案的表面,语言“底表面”可以被限定为指面对顶表面的相对表面。在实施方式中,插入器芯片120可以包括其顶表面上或在该处的重新分布层123。重新分布层123可以位于基体层121的顶表面121a上。重新分布层123可以包括插入器芯片120的顶表面上的芯片导电图案124,并且还可以包括覆盖芯片导电图案124的芯片电介质层125。芯片导电图案124可以具有在芯片电介质层125的顶表面上被暴露的部分,芯片导电图案124的暴露部分可以与上芯片焊盘124a、124b和124c对应。上芯片焊盘124a、124b和124c可以具有与芯片电介质层125的暴露表面共面的暴露表面。芯片导电图案124可以包括例如金属的导电材料。在实施方式中,芯片导电图案124可以包括铜(Cu)。在实施方式中,芯片电介质层125可以包括氧化物。在实施方式中,芯片电介质层125可以包括氧化硅(SiOx)。
过孔件126可以竖直地穿透基体层121。过孔件126可以具有在插入器芯片120的底表面上或在该处被暴露的端部(或底表面)126b。过孔件126的底表面126b可以与插入器芯片120的底表面(或者与芯片保护层122的底表面121b,例如,其在形成保护层122之前为基体层121的底表面)共面,过孔件126的底表面126b和插入器芯片120的底表面可以基本上平坦。过孔件126可以具有朝向插入器芯片120的顶表面延伸并且接触重新分布层123的其它端部(或顶表面)126a。过孔件126的顶表面126a可以位于与基体层121的顶表面121a的水平相同的水平处(例如,可以与之共面),可以与重新分布层123的底表面接触,并且可以位于与重新分布层123的底表面的水平相同的水平处。在实施方式中,重新分布层123可以高于过孔件126。过孔件126可以耦接至重新分布层123的芯片导电图案124。过孔件126可以具有大约50μm至大约150μm的宽度。
插入器芯片120还可以包括在其底表面上或在其底表面处的下芯片焊盘127。下芯片焊盘127可以位于芯片保护层122的底表面121b上。下芯片焊盘127可以与过孔件126对准,过孔件126可以将下芯片焊盘127连接至重新分布层123的芯片导电图案124。种子层128可以位于下芯片焊盘127的顶表面中的每一个上。种子层128可以位于下芯片焊盘127与过孔件126之间以及下芯片焊盘127与芯片保护层122之间。
插入器芯片120可以以某一距离与核心部分110的嵌入区CA的内壁间隔开,并且可以被核心部分110的嵌入区CA的内壁围绕。在实施方式中,当在平面中观看时,核心部分110可以具有围绕插入器芯片120的形状。插入器芯片120可以以面向上的方式设置。在实施方式中,插入器芯片120可以被设置为允许重新分布层123面对核心部分110的顶表面。插入器芯片120的厚度可以小于核心部分110的厚度。在实施方式中,插入器芯片120的厚度可以与核心部分110的厚度相同或者小于核心部分110的厚度。插入器芯片120的上芯片焊盘124a、124b和124c可以具有位于比核心部分110的核心电介质图案112的顶表面的水平高的水平处的顶表面。插入器芯片120的上芯片焊盘124a、124b和124c可以位于与核心部分110的上核心焊盘115的水平相同的水平处。插入器芯片120的底表面可以位于比核心部分110的底表面的水平高的水平处。在实施方式中,插入器芯片120的下芯片焊盘127可以具有位于比核心保护层119的底表面的水平高的水平处的底表面。
在实施方式中,当嵌入区CA具有朝向核心部分110的内部延伸的凹陷形状时,插入器芯片120可以放置在嵌入区CA的底表面上。在此情况下,粘合剂或粘合膜可以用于将插入器芯片120附着到嵌入区CA的底表面。
插入器芯片120可以不包括集成电路。在实施方式中,插入器芯片120可以是有助于布线衬底100的布线的组件。半导体集成电路(IC)工艺可以用于形成包括硅(Si)的插入器芯片120的重新分布层123,并且因此,插入器芯片120的重新分布层123可以具有高的线密度。因此,布线衬底100可以具有高的布线自由度。另外,高导热硅(Si)和竖直延伸的过孔件126可以有助于从安装在布线衬底100上的第一半导体芯片200和第二半导体芯片300生成的热量向下排出。结果,半导体封装件1可以具有高的热辐射效率。
在实施方式中,插入器芯片120可以包括某一集成电路。在此情况下,集成电路可以位于插入器芯片120的顶表面上。集成电路可以包括接地电路或电源电路。在实施方式中,集成电路可以包括存储器电路、逻辑电路或射频集成电路。
嵌入区CA可以在其中具有填充核心部分110与插入器芯片120之间的空间的绝缘层113。绝缘层113可以在插入器芯片120和核心部分110下方延伸。在实施方式中,绝缘层113可以覆盖插入器芯片120的底表面和核心部分110的底表面。在实施方式中,绝缘层113可以暴露出(例如,可以不覆盖或接触)插入器芯片120的底表面和核心部分110的底表面。绝缘层113可以包括绝缘聚合物。在实施方式中,绝缘层113可以包括热固性树脂(诸如环氧树脂)、热塑性树脂(诸如聚酰亚胺)或者包括诸如无机填料的增强剂的树脂(诸如味之素复合膜(ABF)、阻燃剂-4(FR-4)或双马来酰亚胺-三嗪(BT))。在实施方式中,绝缘层113可以包括诸如环氧模塑化合物(EMC)的模塑材料或者诸如PIE(光可成像环氧树脂)的光敏材料。
上堆积部分130和下堆积部分140可以分别覆盖核心部分110的顶表面和底表面。上堆积部分130可以覆盖核心部分110的顶表面和插入器芯片120的顶表面。下堆积部分140可以覆盖核心部分110的底表面和插入器芯片120的底表面。
上堆积部分130可以包括顺序地堆叠在核心部分110的顶表面上的上电介质图案132和上线图案134。上堆积部分130可以覆盖核心部分110的顶表面和插入器芯片120的重新分布层123。下堆积部分140可以包括顺序地堆叠在核心部分110的底表面上的下电介质图案142和下线图案144。下堆积部分140可以覆盖核心部分110的底表面和插入器芯片120的芯片电介质层125。上电介质图案132和下电介质图案142可以包括预浸料、味之素复合膜(ABF)、阻燃剂-4(FR-4)或双马来酰亚胺-三嗪(BT)。上线图案134和下线图案144可以包括电路图案。上线图案134可以连接至核心部分110的上核心焊盘115,并且连接至插入器芯片120的上芯片焊盘124a、124b和124c。在实施方式中,上堆积部分130可以接触核心部分110的顶表面和插入器芯片120的顶表面,上线图案134可以接触上核心焊盘115以及上芯片焊盘124a、124b和124c。下线图案144可以连接至核心部分110的下核心焊盘117,并且连接至插入器芯片120的下芯片焊盘127。在实施方式中,下堆积部分140可以接触绝缘层113的底表面,下线图案144可以穿透绝缘层113以与下芯片焊盘127和下核心焊盘117接触。上线图案134和下线图案144可以包括铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的任意组合。
外部端子150可以位于下堆积部分140下方。外部端子150可以位于下堆积部分140的底表面上。在实施方式中,外部端子150可以穿透下堆积部分140的下电介质图案142,并且可以耦接至下线图案144。在实施方式中,外部端子150可以位于下堆积部分140的底表面上的衬底焊盘上。在此情况下,衬底焊盘可以是下线图案144中的从下堆积部分140的下电介质图案142被暴露的下线图案144、或者位于下堆积部分140的下电介质图案142上并且连接至下线图案144的单独的焊盘。外部端子150可以通过下线图案144电连接至插入器芯片120和核心部分110。外部端子150可以包括焊球或焊料凸块。
第一半导体芯片200和第二半导体芯片300可以安装在布线衬底100上。第一半导体芯片200和第二半导体芯片300可以彼此间隔开。第一半导体芯片200和第二半导体芯片300可以包括例如硅(Si)的半导体材料。第一半导体芯片200可以包括第一电路层210,第二半导体芯片300可以包括第二电路层310。第一半导体芯片200的第一电路层210可以包括逻辑电路。在实施方式中,第一半导体芯片200可以是逻辑芯片。第二半导体芯片300的第二电路层310可以包括存储器电路。在实施方式中,第二半导体芯片300可以是存储器芯片。第二半导体芯片300可以被设置为多个。在实施方式中,多个第二半导体芯片300可以具有竖直芯片堆叠结构。第一半导体芯片200和第二半导体芯片300可以是安装在布线衬底100上的倒装芯片。在实施方式中,第一芯片端子230可以位于第一半导体芯片200的第一电路层210的一个表面上的第一芯片焊盘220上。第二芯片端子330可以位于第二半导体芯片300的第二电路层310的一个表面上的第二芯片焊盘320上。第一芯片端子230和第二芯片端子330可以耦接至上堆积部分130的上线图案134。在实施方式中,上线图案134中的一些上线图案134可以是在上电介质图案132的顶表面上被暴露的焊盘,第一芯片端子230和第二芯片端子330可以将暴露的上线图案134连接至第一芯片焊盘220和第二芯片焊盘320。在此情况下,第一半导体芯片200可以通过插入器芯片120连接至第二半导体芯片300。在实施方式中,第一半导体芯片200可以通过上堆积部分130耦接至包括在插入器芯片120中的重新分布层123的第一上芯片焊盘124a。第二半导体芯片300可以通过上堆积部分130耦接至包括在插入器芯片120中的重新分布层123的第二上芯片焊盘124b。第一上芯片焊盘124a和第二上芯片焊盘124b可以在重新分布层123中彼此电连接。因此,可以在第一半导体芯片200与第二半导体芯片300之间实现芯片与芯片连接。当第一半导体芯片200和第二半导体芯片300通过在插入器芯片120中具有高的线密度的重新分布层123彼此连接时,可以在第一半导体芯片200与第二半导体芯片300之间实现减小的电连接长度,半导体封装件1可以具有改善的电特性。
将第一半导体芯片200和第二半导体芯片300彼此连接的第一上芯片焊盘124a和第二上芯片焊盘124b可以从插入器芯片120的过孔件126电浮置。第三上芯片焊盘124c(上芯片焊盘124a、124b和124c之中除了第一上芯片焊盘124a和第二上芯片焊盘124b之外的)可以电连接至过孔件126。
在实施方式中,将第一半导体芯片200和第二半导体芯片300彼此连接的第一上芯片焊盘124a和第二上芯片焊盘124b可以电连接至插入器芯片120的过孔件126。在实施方式中,第一半导体芯片200和第二半导体芯片300可以接收通过下堆积部分140、过孔件126和第三上芯片焊盘124c从外部施加的电力信号或地信号。电力信号或地信号可以通过与核心部分110单独分离的插入器芯片120传输至第一半导体芯片200和第二半导体芯片300,核心部分110用作沿其传输驱动信号的电路径。因此,能够容易地对电力电路或接地电路进行分组,以使传输至第一半导体芯片200和第二半导体芯片300的电力信号或地信号均衡,从而轻松地实现针对驱动信号或者电力信号和地信号的布线设计,并提高布线的自由度。
模制层400可以位于布线衬底100上。布线衬底100可以在其顶表面上设置有覆盖第一半导体芯片200和第二半导体芯片300的模制层400。模制层400可以包括绝缘材料。在实施方式中,模制层400可以包括环氧模塑化合物(EMC)。
可以提供如以上所讨论的半导体封装件1。
图4是根据一些示例实施例的半导体封装件的截面图。在以下的实施例中,可以省略以上参照图1至图3讨论的技术特征的重复详细描述,并且可以详细地讨论其不同之处。与以上讨论的半导体封装件的组件相同的组件将对其分配相同的附图标记。
参照图4,半导体封装件2可以包括布线衬底100、安装在布线衬底100上的第一半导体芯片200和第二半导体芯片300以及覆盖布线衬底100上的第一半导体芯片200和第二半导体芯片300的模制层400。
可以提供布线衬底100。布线衬底100可以包括插入器芯片120、插入器芯片120上的上堆积部分130和插入器芯片120下方的下堆积部分140。
插入器芯片120、上堆积部分130和下堆积部分140可以与参照图1至图3讨论的那些基本上相同或相似。
在实施方式中,插入器芯片120可以包括基体层121、基体层121上的重新分布层123和基体层121中的过孔件126。基体层121可以包括硅(Si)。重新分布层123可以位于基体层121的顶表面121a上。过孔件126可以穿透基体层121,并且可以耦接至重新分布层123。下芯片焊盘127可以位于芯片保护层122的底表面121b上,并且可以与过孔件126对准。
上堆积部分130可以包括顺序地堆叠在插入器芯片120上的上电介质图案132和上线图案134。上线图案134可以连接至插入器芯片120的上芯片焊盘124a、124b和124c。
下堆积部分140可以包括顺序地堆叠在插入器芯片120下方的下电介质图案142和下线图案144。下线图案144可以连接至插入器芯片120的下芯片焊盘127。
绝缘层113-1可以填充下堆积部分140与上堆积部分130之间的空间。绝缘层113-1可以将插入器芯片120埋置在下堆积部分140与上堆积部分130之间。在实施方式中,当在平面中观看时,绝缘层113-1可以围绕插入器芯片120。绝缘层113-1可以接触插入器芯片120的侧表面。绝缘层113-1的一部分可以覆盖插入器芯片120的底表面。在实施方式中,插入器芯片120的下芯片焊盘127可以不被暴露。绝缘层113-1可以包括例如环氧模塑化合物(EMC)的绝缘材料。在实施方式中,绝缘层113-1可以包括绝缘聚合物。在实施方式中,绝缘层113-1可以包括热固性树脂(诸如环氧树脂)、热塑性树脂(诸如聚酰亚胺)或者包括诸如无机填料的增强剂的树脂(诸如味之素复合膜(ABF)、阻燃剂-4(FR-4)或双马来酰亚胺-三嗪(BT))。在实施方式中,绝缘层113-1可以包括诸如环氧模塑化合物(EMC)的模塑材料或者诸如光可成像环氧树脂(PIE)的光敏材料。
贯穿电极114-2可以位于绝缘层113-1中。在插入器芯片120的一侧处,贯穿电极114-2可以竖直地穿透绝缘层113-1。贯穿电极114-2可以具有随着接近上堆积部分130而减小的宽度(例如,贯穿电极114-2可以具有锥形形状)。贯穿电极114-2可以穿透绝缘层113-1,并且可以在绝缘层113-1的顶表面上或在该处被暴露。上堆积部分130的上线图案134可以穿透上电介质图案132,并且可以接触贯穿电极114-2的顶表面。贯穿电极114-2可以穿透绝缘层113-1,并且可以在绝缘层113-1的底表面上或在该处被暴露。下堆积部分140的下线图案144可以穿透下电介质图案142,并且可以接触贯穿电极114-2的底表面。在这样的配置中,与贯穿电极114-2接触的下线图案144可以与贯穿电极114-2一体地形成。下线图案144还可以穿透绝缘层113-1,并且可以耦接至下芯片焊盘127。
图5是根据一些示例实施例的半导体封装件的截面图。
参照图5,半导体封装件3可以包括布线衬底100、安装在布线衬底100上的第一半导体芯片200和第二半导体芯片300以及在布线衬底100上覆盖第一半导体芯片200和第二半导体芯片300的模制层400。
布线衬底100、第一半导体芯片200和第二半导体芯片300以及模制层400可以与参照图1至图3讨论的那些基本上相同或相似。例如,布线衬底100可以包括核心部分110、核心部分110的嵌入区CA中的插入器芯片120、核心部分110上的上堆积部分130以及核心部分110下方的下堆积部分140。第一半导体芯片200和第二半导体芯片300可以安装在布线衬底100的上堆积部分130上。第一半导体芯片200和第二半导体芯片300可以通过上堆积部分130和插入器芯片120的重新分布层123彼此连接。在布线衬底100上,模制层400可以覆盖第一半导体芯片200和第二半导体芯片300。
半导体封装件3还可以包括模制层400上的上封装件500。在实施方式中,半导体封装件3可以设置在层叠封装(POP)的结构中。
上封装件500可以包括上衬底510、上半导体芯片520和上模制层530。
上衬底510可以是印刷电路板(PCB)。在实施方式中,上衬底510可以是重新分布层。上衬底510可以包括上衬底510的底表面上的第一上衬底焊盘512,并且还可以包括上衬底510的顶表面上的第二上衬底焊盘514。
上半导体芯片520可以安装在上衬底510上。在实施方式中,上半导体芯片520可以是安装在上衬底510上的倒装芯片。上半导体芯片520可以通过第二上衬底焊盘514与上芯片焊盘522之间的第三芯片端子524安装在上衬底510上。上半导体芯片520可以包括存储器芯片或逻辑芯片。在实施方式中,如图5中所示,可以提供单个上半导体芯片520。在实施方式中,上半导体芯片520可以被设置为多个。在此情况下,多个上半导体芯片520可以被设置为彼此堆叠,或者在上衬底510上彼此水平地间隔开。
上模制层530可以位于上衬底510上。在上衬底510上,上模制层530可以覆盖上半导体芯片520。上模制层530可以包括例如环氧模塑化合物(EMC)的绝缘材料。
上封装件500可以位于布线衬底100上。在实施方式中,连接端子410可以位于模制层400中。连接端子410可以穿透模制层400,并且可以将上衬底510的第一上衬底焊盘512连接至布线衬底100中的上堆积部分130的上线图案134。在实施方式中,如图5中所示,连接端子410可以是被形成为竖直地穿透模制层400的导电柱。在实施方式中,连接端子410可以包括诸如焊球或焊料凸块的焊接构件,或者可以具有能够将第一上衬底焊盘512机械地连接至上线图案134的各种结构。上封装件500可以通过连接端子410和布线衬底100电连接至外部端子150。
可以提供如以上所讨论的半导体封装件3。
图6至图17是根据一些示例实施例的制造半导体封装件的方法的截面图。在图6至图17中,图6至图11是根据一些示例实施例的制造插入器芯片的方法的截面图。
参照图6,可以提供基体层121。基体层121可以包括例如半导体晶片。在实施方式中,基体层121可以是硅晶片。基体层121可以具有第一表面121a和与第一表面121a相对的第二表面121c。
可以在基体层121上形成孔H。可以通过对基体层121的第一表面121a执行诸如激光打孔的工艺来形成孔H。在实施方式中,可以通过以下步骤来形成孔H:在基体层121的第一表面121a上形成掩模图案,并且随后使用掩模图案作为蚀刻掩模来执行各向异性蚀刻工艺。可以使任何孔H都没有竖直地完全穿透基体层121。在实施方式中,孔H可以被形成为与第二表面121c间隔开。
参照图7,可以在基体层121中形成过孔件126。在实施方式中,可以在基体层121的第一表面121a上涂覆或沉积导电材料。导电材料可以填充基体层121的孔H。之后,可以从基体层121的第一表面121a去除导电材料的一部分,并且可以仅在孔H中保留导电材料。
参照图8,可以在基体层121的第一表面121a上形成重新分布层123。在实施方式中,可以在基体层121的第一表面121a上形成诸如氧化硅的电介质层,然后可以将电介质层图案化以形成芯片电介质层125的一部分。芯片电介质层125可以暴露出过孔件126。可以在芯片电介质层125的顶表面上形成导电层,然后可以将导电层图案化以形成芯片导电图案124。芯片导电图案124可以电连接至过孔件126。如以上所讨论的,可以重复地执行电介质层的形成和图案化以及导电层的形成和图案化以形成重新分布层123。
参照图9,可以去除基体层121的一部分。在实施方式中,基体层121可以被薄化以暴露出过孔件126。在实施方式中,基体层121的第二表面121c可以经历诸如磨削或化学气相抛光(CMP)的薄化工艺。薄化工艺可以使基体层121具有与过孔件126的端部共面的第三表面121b。在实施方式中,基体层121的第三表面121b和过孔件126的端部可以是基本上平坦的。
参照图10,可以在基体层121的第三表面121b上或第三表面121b中形成芯片保护层122。在实施方式中,可以对基体层121的暴露的第三表面121b执行氧化工艺或氮化工艺。因此,基体层121的第三表面121b可以被部分地氧化或氮化以形成芯片保护层122。芯片保护层122可以具有与过孔件126的端部共面的顶表面。
可以在芯片保护层122上形成下芯片焊盘127。在实施方式中,可以在芯片保护层122上形成种子层128。种子层128可以覆盖芯片保护层122的顶表面和过孔件126的端部(或顶表面)。可以在种子层128上形成掩模图案MP。掩模图案MP可以具有与过孔件126叠置的开口。之后,种子层128可以用作用于电镀工艺的种子,以形成填充开口的下芯片焊盘127。可以在过孔件126上形成下芯片焊盘127。
参照图11,可以去除掩模图案MP。之后,下芯片焊盘127可以用作蚀刻掩模,来将种子层128图案化。因此,种子层128可以被图案化以保留在芯片保护层122与下芯片焊盘127之间以及过孔件126与下芯片焊盘127之间。
以上提及的工艺可以形成插入器芯片120。
在实施方式中,如图6至图11中所示,可以在基体层121上形成单个插入器芯片120。在实施方式中,可以在单个基体层121上形成多个插入器芯片120,并且在此情况下,在形成插入器芯片120之后,基体层121可以经历锯切工艺,以使插入器芯片120彼此分离。
以下将继续讨论制造半导体封装件的方法。
参照图12,可以提供核心部分110。核心部分110可以包括核心电介质图案112和形成在核心电介质图案112中的核心导电图案114。核心导电图案114可以包括上核心焊盘115、核心布线116和下核心焊盘117。可以在核心电介质图案112的底表面上形成核心保护层119。在实施方式中,可以在核心电介质图案112的底表面上涂覆电介质材料,从而形成核心保护层119。
可以将第一承载衬底900附着到核心部分110的底表面。第一承载衬底900可以是包括玻璃或聚合物的电介质衬底或者包括金属的导电衬底。第一承载衬底900可以在其顶表面上设置有粘合构件,第一承载衬底900通过该粘合构件可以附着到核心保护层119的底表面。在实施方式中,粘合构件可以包括胶带。
可以在核心部分110上形成保护层910。
参照图13,可以在核心部分110中形成嵌入区CA。可以通过去除核心部分110的部分区来形成嵌入区CA,以允许嵌入区CA穿透核心部分110。在实施方式中,可以通过执行诸如钻孔、激光烧蚀或激光切割的蚀刻工艺来形成嵌入区CA。核心部分110的去除的部分区可以是在后续工艺中要设置插入器芯片120的空间。
参照图14,可以从图13的所得结构去除第一承载衬底900和保护层910。
可以将第二承载衬底920附着到核心部分110。第二承载衬底920可以是包括玻璃或聚合物的绝缘衬底或者包括金属的导电衬底。第二承载衬底920可以在其顶表面上设置有粘合构件,第二承载衬底920通过该粘合构件可以附着到核心部分110。在实施方式中,粘合构件可以包括胶带。可以将核心部分110附着到第二承载衬底920,以允许上核心焊盘115面对第二承载衬底920。
可以在第二承载衬底920上设置插入器芯片120。插入器芯片120可以位于核心部分110的嵌入区CA中。可以将插入器芯片120粘合至第二承载衬底920。在实施方式中,可以将插入器芯片120附着到第二承载衬底920,以允许重新分布层123面对第二承载衬底920。因此,插入器芯片120的重新分布层123的表面可以在低于核心部分110的核心电介质图案112的底表面的水平并且与上核心焊盘115的表面的水平相同的水平处。
参照图15,可以在第二承载衬底920上形成绝缘层113。绝缘层113可以填充核心部分110与插入器芯片120之间的间隙。在实施方式中,可以将绝缘构件引入核心部分110与插入器芯片120之间的间隙,然后,可以将绝缘构件固化以形成绝缘层113。在实施方式中,绝缘构件可以被形成为覆盖插入器芯片120。因此,可以不暴露出插入器芯片120的下芯片焊盘127。另外,绝缘构件的一部分可以覆盖核心部分110的顶表面。在实施方式中,绝缘层113可以被形成为不覆盖核心部分110的顶表面或插入器芯片120的顶表面。
参照图16,可以将第三承载衬底930附着到绝缘层113。第三承载衬底930可以是包括玻璃或聚合物的电介质衬底或者包括金属的导电衬底。第三承载衬底930可以在其顶表面上设置有粘合构件,第三承载衬底930通过该粘合构件可以附着到绝缘层113。在实施方式中,粘合构件可以包括胶带。之后,可以去除第二承载衬底920。
可以在通过去除第二承载衬底920而暴露的插入器芯片120和核心部分110的顶表面上形成上堆积部分130。在实施方式中,可以在核心部分110和插入器芯片120的顶表面上形成上电介质图案132和上线图案134,从而形成上堆积部分130。可以在核心部分110和插入器芯片120的顶表面上形成诸如氧化硅的电介质层,然后,可以将电介质层图案化,以形成上电介质图案132的一部分。上电介质图案132可以暴露出核心部分110的上核心焊盘115和插入器芯片120的上芯片焊盘(见图2的124a、124b和124c)。可以在上电介质图案132的顶表面上形成导电层,然后,可以将导电层图案化以形成上线图案134。上线图案134可以具有与上核心焊盘115和上芯片焊盘(见图2的124a、124b和124c)的对应的电连接。可以在上线图案134的顶表面上形成电介质层,然后,可以将电介质层图案化以形成上电介质图案132的其它部分。上线图案134的所述其它部分可以在上电介质图案132上被暴露。
参照图17,可以将第四承载衬底940附着到上堆积部分130。第四承载衬底940可以是包括玻璃或聚合物的电介质衬底或者包括金属的导电衬底。第四承载衬底940可以在其顶表面上设置有粘合构件,第四承载衬底940通过该粘合构件可以附着到上堆积部分130。在实施方式中,粘合构件可以包括胶带。之后,可以去除第三承载衬底930。
可以在插入器芯片120和核心部分110的通过去除第三承载衬底930而暴露的底表面上形成下堆积部分140。在实施方式中,可以在核心部分110和插入器芯片120的底表面上形成下电介质图案142和下线图案144,从而形成下堆积部分140。可以将绝缘层113图案化以暴露出插入器芯片120的下芯片焊盘127和核心部分110的下核心焊盘117,可以在绝缘层113的底表面上形成导电层,然后,可以将导电层图案化以形成下线图案144的一部分。下线图案144可以具有与下芯片焊盘127和下核心焊盘117的对应电连接。可以在下线图案144的底表面上形成电介质层,并且可以将该电介质层图案化以形成下电介质图案142的其它部分。下线图案144可以在下电介质图案142上被部分地暴露。
之后,可以去除第四承载衬底940以形成布线衬底100。
返回参照图1,可以在布线衬底100上安装第一半导体芯片200和第二半导体芯片300。第一半导体芯片200和第二半导体芯片300可以是安装的倒装芯片。
可以在布线衬底100上形成模制层400。例如,可以在布线衬底100上涂覆电介质材料以覆盖第一半导体芯片200和第二半导体芯片300,并且然后,电介质材料可以固化以形成模制层400。
可以在布线衬底100的底表面上设置外部端子150。可以通过将诸如焊球或焊料凸块的焊接构件提供到下线图案144的通过将下电介质图案142图案化而暴露的表面上来形成外部端子150。
可以通过以上提及的工艺来形成半导体封装件1。
在实施方式中,如图12至图17中所示,可以在单个布线衬底100上形成单个半导体封装件1。在实施方式中,可以在单个布线衬底100上形成多个半导体封装件1,并且在此情况下,在形成半导体封装件1之后,布线衬底100和模制层400可以经历锯切工艺以将半导体封装件1彼此分离。
图18至图21是根据一些示例实施例的制造半导体封装件的方法中的阶段的截面图。
参照图18,可以在第五承载衬底950上设置插入器芯片120。可以将插入器芯片120附着到第五承载衬底950。在实施方式中,可以将插入器芯片120附着到第五承载衬底950,以允许重新分布层123面对第五承载衬底950。
参照图19,可以在第五承载衬底950上形成绝缘层113-1。可以在第五承载衬底950上涂覆绝缘材料,从而形成绝缘层113-1。可以在第五承载衬底950上涂覆绝缘材料以覆盖插入器芯片120。绝缘层113-1可以覆盖插入器芯片120的侧表面和插入器芯片120的顶表面(或者芯片保护层122的顶表面和下芯片焊盘127的顶表面)。绝缘材料可以包括诸如环氧模塑化合物(EMC)的绝缘聚合物。
参照图20,可以在绝缘层113-1中形成贯穿电极114-2。在实施方式中,可以将穿通孔VH形成为竖直地穿透绝缘层113-1,然后可以用导电材料填充穿通孔VH以形成贯穿电极114-2。当用导电材料填充穿通孔VH时,可以在绝缘层113-1上涂覆导电材料以覆盖绝缘层113-1的顶表面,可以将绝缘层113-1上的导电材料图案化以形成以下将讨论的下堆积部分140的下线图案144的一部分。
可以在绝缘层113-1上形成下堆积部分140。在实施方式中,可以在绝缘层113-1的顶表面上形成下电介质图案142和下线图案144,从而形成下堆积部分140。可以将绝缘层113-1图案化以暴露出贯穿电极114-2和插入器芯片120的下芯片焊盘127,可以在绝缘层113-1的顶表面上形成导电层,然后可以将导电层图案化以形成下线图案144的一部分。下线图案144可以具有与下芯片焊盘127和贯穿电极114-2的对应电连接。可以在下线图案144的底表面上形成电介质层,并且可以将电介质层图案化以形成下电介质图案142的其它部分。下线图案144可以在下电介质图案142上被部分地暴露。
参照图21,可以在绝缘层113-1和插入器芯片120的通过去除第五承载衬底950而暴露的表面上形成上堆积部分130。在实施方式中,可以在绝缘层113-1和插入器芯片120的表面上形成上电介质图案132和上线图案134,从而形成上堆积部分130。可以在绝缘层113-1和插入器芯片120的表面上形成诸如氧化硅的电介质层,然后,可以将电介质层图案化以形成上电介质图案132的一部分。上电介质图案132可以暴露出绝缘层113-1中的贯穿电极114-2和插入器芯片120的上芯片焊盘(见图2的124a、124b和124c)。可以在上电介质图案132的顶表面上形成导电层,然后可以将导电层图案化以形成上线图案134。上线图案134可以具有与贯穿电极114-2和上芯片焊盘(见图2的124a、124b和124c)的对应的电连接。可以在上线图案134的顶表面上形成电介质层,然后可以将电介质层图案化以形成上电介质图案132的其它部分。上线图案134可以在上电介质图案132上被部分地暴露。以上讨论的工艺可以形成参照图4讨论的布线衬底100。
之后,可以执行与图1中讨论的那些相同或相似的工艺。在实施方式中,如图4中所示,可以在布线衬底100上安装第一半导体芯片200和第二半导体芯片300。可以在布线衬底100上形成覆盖第一半导体芯片200和第二半导体芯片300的模制层400。可以在布线衬底100的底表面上设置外部端子150。
以上提及的工艺可以形成参照图4讨论的半导体封装件3。
在根据一些示例实施例的半导体封装件中,可以将高的线密度提供至包括硅(Si)的插入器芯片的重新分布层,可以赋予布线衬底高的布线自由度。电力信号或地信号可以通过与核心部分单独分离的插入器芯片传输到半导体芯片,核心部分用作驱动信号沿其传输的电路径。因此,能够容易地对电源电路或接地电路进行分组,以使传输至半导体芯片的电力信号或地信号均衡,从而轻松地实现针对驱动信号或者针对电力信号和地信号的布线设计,并提高布线的自由度。
另外,高导热硅(Si)和竖直延伸的过孔件可以有助于从安装在布线衬底上的半导体芯片生成的热量向下排出。结果,半导体封装件可以被设置为具有高的热辐射效率。
此外,当半导体芯片通过插入器芯片中的具有高的线密度的重新分布层彼此连接时,可以在半导体芯片之间实现减小的电连接长度,并且半导体封装件可以具有改善的电特性。
通过总结和回顾的方式,在一些半导体封装件中,半导体芯片可以安装在印刷电路板(PCB)上,并且键合布线或凸块可以用于将半导体芯片电连接至印刷电路板。随着电子工业的最新开发,可以考虑到紧凑的尺寸、小的重量和/或低的制造成本来开发半导体封装件。另外,许多种类的半导体封装(诸如大容量海量存储装置)可以随着其应用领域的扩展而出现。
一个或多个实施例可以提供具有高的布线自由度的半导体封装件。
一个或多个实施例可以提供具有提高的热辐射效率的半导体封装件。
一个或多个实施例可以提供具有改善的电特性的半导体封装件。
本文中已经公开了示例实施例,并且尽管采用了特定术语,但是将仅以一般性的和描述性的含义而不是出于限制的目的来使用和解释它们。在一些情况下,如对于到提交本申请时为止的本领域普通技术人员而言将显而易见,除非另有明确说明,否则结合特定实施例描述的特征、特性和/或元件可单独使用,或者可以与结合其它实施例描述的特征、特性和/或元件组合使用。因此,本领域技术人员将理解,在不脱离如所附权利要求中阐述的本发明的精神和范围的情况下,可以进行形式和细节上的各种改变。
Claims (20)
1.一种半导体封装件,包括:
衬底;
第一半导体芯片和第二半导体芯片,其安装在所述衬底上;以及
多个外部端子,其位于所述衬底下方,
其中,所述衬底包括:
核心部分;
第一堆积部分和第二堆积部分,其分别位于所述核心部分的顶表面和底表面上,所述第一堆积部分和所述第二堆积部分中的每一个包括电介质图案和线图案;以及
插入器芯片,其位于所述核心部分中的嵌入区中,并且电连接至所述第一堆积部分和所述第二堆积部分,
其中,所述插入器芯片包括:
基体层;
重新分布层,其位于所述基体层的第一表面上;以及
过孔件,其穿透所述基体层,所述过孔件连接至所述重新分布层,并且在所述基体层的第二表面处被暴露,
其中,所述重新分布层连接至所述第一堆积部分的线图案,并且
其中,所述过孔件连接至所述第二堆积部分的线图案。
2.根据权利要求1所述的半导体封装件,其中,所述插入器芯片还包括:
保护层,其覆盖所述基体层的第二表面,并且暴露出所述过孔件;以及
焊盘,其位于所述保护层的一个表面上,所述焊盘将所述过孔件连接至所述第二堆积部分的线图案。
3.根据权利要求1所述的半导体封装件,其中:
所述重新分布层位于所述过孔件上,并且
所述过孔件的顶表面位于与所述基体层的第一表面的水平相同的水平处。
4.根据权利要求1所述的半导体封装件,其中,所述插入器芯片的重新分布层的顶表面位于与所述核心部分的顶表面的水平相同的水平处。
5.根据权利要求1所述的半导体封装件,其中:
所述嵌入区具有竖直地穿透所述核心部分的开孔形状,并且
所述插入器芯片与所述嵌入区的内壁间隔开。
6.根据权利要求5所述的半导体封装件,还包括绝缘层,其填充所述插入器芯片与所述嵌入区的内壁之间的间隙,
其中,所述第二堆积部分的线图案穿透所述绝缘层,并且耦接至所述过孔件。
7.根据权利要求5所述的半导体封装件,其中,所述核心部分包括多个核心导电图案,所述多个核心导电图案与所述嵌入区间隔开,并且将所述第一堆积部分电连接至所述第二堆积部分。
8.根据权利要求1所述的半导体封装件,其中:
所述核心部分围绕所述插入器芯片,并且接触所述插入器芯片的侧表面,并且
所述核心部分包括贯穿电极,所述贯穿电极竖直地穿透所述核心部分,并且将所述第一堆积部分的线图案直接连接至所述第二堆积部分的线图案。
9.根据权利要求1所述的半导体封装件,其中,所述第一半导体芯片和所述第二半导体芯片通过所述第一堆积部分和所述插入器芯片彼此电连接。
10.根据权利要求1所述的半导体封装件,其中:
所述嵌入区位于所述核心部分的上部上,
所述插入器芯片位于所述嵌入区的底表面上,并且
所述第二堆积部分的线图案穿透所述核心部分,并且接触所述插入器芯片的过孔件。
11.根据权利要求1所述的半导体封装件,其中,所述插入器芯片的底表面位于比所述核心部分的底表面的水平高的水平处。
12.根据权利要求1所述的半导体封装件,其中,所述插入器芯片的基体层包括硅。
13.根据权利要求1所述的半导体封装件,还包括:
模制层,其位于所述第一堆积部分上,所述模制层覆盖所述第一半导体芯片和所述第二半导体芯片;
重新分布衬底,其位于所述模制层上;以及
连接端子,其穿透所述模制层,并且将所述重新分布衬底连接至所述第一堆积部分。
14.一种半导体封装件,包括:
第一布线层;
第二布线层,其位于所述第一布线层上;
插入器芯片,其位于所述第一布线层与所述第二布线层之间;
绝缘层,其位于所述第一布线层与所述第二布线层之间,所述绝缘层围绕所述插入器芯片;
导电元件,其位于所述第一布线层与所述第二布线层之间,所述导电元件与所述插入器芯片间隔开,并且将所述第一布线层连接至所述第二布线层;
第一半导体芯片和第二半导体芯片,其安装在所述第二布线层上;
模制层,其位于所述第二布线层上,所述模制层覆盖所述第一半导体芯片和所述第二半导体芯片;以及
多个外部端子,其位于所述第一布线层下方,
其中,所述插入器芯片包括:
基体层;
重新分布层,其位于所述基体层上,并且耦接至所述第二布线层;以及
过孔件,其位于所述基体层中,所述过孔件将所述重新分布层连接至所述第一布线层,并且
其中,所述第一半导体芯片和所述第二半导体芯片通过所述插入器芯片彼此电连接。
15.根据权利要求14所述的半导体封装件,其中,所述过孔件竖直地穿透所述基体层,所述过孔件位于所述重新分布层下方,并且在所述基体层的底表面处被暴露。
16.根据权利要求14所述的半导体封装件,其中,所述插入器芯片还包括:
保护层,其覆盖所述基体层的底表面,并且暴露出所述过孔件;以及
焊盘,其位于所述保护层的一个表面上,所述焊盘将所述过孔件连接至所述第一布线层。
17.根据权利要求14所述的半导体封装件,其中:
所述重新分布层位于所述过孔件上,并且
所述过孔件的顶表面位于与所述基体层的顶表面的水平相同的水平处。
18.根据权利要求14所述的半导体封装件,还包括位于所述第一布线层与所述第二布线层之间的核心部分,所述核心部分包括嵌入区,所述嵌入区具有穿透所述核心部分的内部的开孔形状,
其中,在所述嵌入区中,所述绝缘层填充所述核心部分与所述插入器芯片之间的间隙,并且
其中,所述导电元件包括所述核心部分中的多个核心导电图案。
19.根据权利要求14所述的半导体封装件,其中:
所述绝缘层填充所述第一布线层与所述第二布线层之间的空间,并且
所述导电元件包括竖直地穿透所述绝缘层的贯穿电极。
20.根据权利要求14所述的半导体封装件,其中,所述第一半导体芯片和所述第二半导体芯片通过所述第二布线层和所述插入器芯片彼此电连接。
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