CN102789966A - 用于在基板上制造金属层的方法和器件 - Google Patents

用于在基板上制造金属层的方法和器件 Download PDF

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Publication number
CN102789966A
CN102789966A CN2012101570018A CN201210157001A CN102789966A CN 102789966 A CN102789966 A CN 102789966A CN 2012101570018 A CN2012101570018 A CN 2012101570018A CN 201210157001 A CN201210157001 A CN 201210157001A CN 102789966 A CN102789966 A CN 102789966A
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metal material
semiconductor
semiconductor substrate
metal
metallic particles
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CN2012101570018A
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哈利勒·哈希尼
汉斯-约阿希姆·舒尔茨
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Infineon Technologies AG
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Infineon Technologies AG
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C4/00—Coating by spraying the coating material in the molten state, e.g. by flame, plasma or electric discharge
    • C23C4/01—Selective coating, e.g. pattern coating, without pre-treatment of the material to be coated
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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    • C23C4/04—Coating by spraying the coating material in the molten state, e.g. by flame, plasma or electric discharge characterised by the coating material
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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    • C23C4/12—Coating by spraying the coating material in the molten state, e.g. by flame, plasma or electric discharge characterised by the method of spraying
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Abstract

本发明涉及用于在基板上制造金属层的方法和器件。具体地，本发明提供了一种在半导体基板上制造金属层的方法。通过沉积金属颗粒在半导体基板上制造金属层。该金属颗粒包括由第一金属材料制成的核和包围该核的壳。该壳由抗氧化的第二金属材料制成。本发明还涉及一种用于制造半导体基板中的通孔的方法以及制造半导体芯片的方法。本发明还涉及一种半导体器件，其包括包含第一电极的半导体芯片；和施加于该半导体芯片的第一电极的金属颗粒。

Description

用于在基板上制造金属层的方法和器件
技术领域
本发明涉及一种用于在基板上制造金属层的方法。本发明进一步地涉及一种包括半导体芯片和施加于该半导体芯片电极的金属层的器件。
背景技术
半导体器件制造者正在不断地努力提高其产品的性能，同时降低制造的成本。在半导体器件的制造中，成本主要发生在该半导体芯片的封装上。如本领域技术人员已知的，在晶圆中制造集成电路，然后将其分割（singulate）以制造半导体芯片。将一个或多个半导体芯片置于封装结构中以保护芯片免受环境和物理的压力的伤害。封装半导体芯片增加了制造半导体器件的成本和复杂性，因为封装设计不仅提供保护，而且也允许电信号从半导体芯片进出，并且尤其是除去半导体芯片产生的热。
为了使电能进入该半导体芯片中的集成电路，在该半导体芯片上沉积铜层。然而，该铜层会经受氧化，而氧化会阻碍后续的制造过程，如芯片键合（die bonding）、线键合（wire bonding）和模制。
发明内容
本发明提供了一种用于制造半导体器件的方法，方法包括：提供半导体基板；以及通过在该半导体基板上沉积金属颗粒而在该半导体基板上形成金属层，其中该金属颗粒包含由第一金属材料制成的核和包围该核的壳，该壳由抗氧化的第二金属材料制成。
在一种实施方式中，该第一金属材料包含铜和铝中的至少一种。
在一种实施方式中，该第二金属材料包含银、金、钯、钛、钽和铌中的至少一种。
在一种实施方式中，该第二金属材料是贵金属。
在一种实施方式中，该金属颗粒的直径大于300nm。
在一种实施方式中，该半导体基板包含功率集成电路。
在一种实施方式中，该方法进一步包括在制造该金属层之后将该半导体基板切割成独立的半导体芯片。
在一种实施方式中，沉积该金属颗粒包括产生等离子体射流，并将该等离子体射流与包含该金属颗粒的载气混合。
在一种实施方式中，该等离子体射流在反应室中与该载气混合，其与该等离子体射流的产生物理分离。
在一种实施方式中，该方法进一步包括将接合线（bond wire）直接附接于该金属层上。
在一种实施方式中，该方法进一步包括将该半导体基板附接于具有面向金属载体的该金属层的该金属载体。
在一种实施方式中，该第一金属材料的热膨胀系数高于该第二金属材料的热膨胀系数。
在一种实施方式中，该第一金属材料的热膨胀系数低于第二金属材料的热膨胀系数。
在一种实施方式中，该金属层形成一个或多个接触垫。
在一种实施方式中，进一步包括在该半导体基板中制造贯通孔（透孔或穿透孔，through hole），并且用该金属颗粒填充该贯通孔。
在一种实施方式中，该方法进一步包括在该金属层上沉积一层焊料。
本发明还提供了一种用于制造半导体芯片的方法，该方法包括：提供半导体晶圆；通过等离子体在该半导体晶圆上沉积金属颗粒而在该半导体晶圆上形成金属层，其中该金属颗粒包含由铜和铝中的至少一种制成的核和包围该核的壳，该壳由银、金、钯、钛、钽和铌中的至少一种制成；以及切割该半导体晶圆，从而分开该半导体芯片。
本发明还提供了一种用于制造半导体基板中的通孔（via）的方法，该方法包括：提供半导体基板；在该半导体基板中制造贯通孔；和在该贯通孔中沉积金属颗粒，其中该金属颗粒包含由第一金属材料制成的核和包围该核的壳，该壳由抗氧化的第二金属材料制成。
本发明还提供了一种半导体器件，其包含：包含第一电极的半导体芯片；和施加于该半导体芯片的该第一电极的金属颗粒，其中该金属颗粒包含由第一金属材料制成的核和包围该核的壳，该壳由抗氧化的第二金属材料制成。
在一种实施方式的半导体器件中，该半导体芯片包含第一主表面和与该第一主表面相对的第二主表面，该第一电极被布置在该第一主表面上而该第二电极被布置在该第二主表面上。
在一种实施方式的半导体器件中，进一步包含施加于该半导体芯片的该第二电极的另外的金属颗粒，其中该另外的金属颗粒包含由第一金属材料制成的核和包围该核的壳，该壳由抗氧化的第二金属材料制成。
在一种实施方式中，该半导体器件进一步包含金属载体和接合线，其中施加于该第一电极的该金属颗粒附着于该金属载体，而施加于该第二电极的该另外的金属颗粒附着于该接合线。
在一种实施方式的半导体器件中，该半导体芯片是功率MOSFET、IGBT、JFET、功率双极晶体管和功率二极管中的一种。
在一种实施方式的半导体器件中，该第一金属材料包含铜和铝中的至少一种，而该第二金属材料包含银、金、钯、钛、钽和铌中的至少一种。
在一种实施方式中，该半导体器件进一步包含嵌入该半导体芯片的封装材料和该封装材料中的填充有该金属颗粒的贯通孔。
附图说明
包括附图以提供对实施方式的进一步理解，附图包括在本说明书中并构成说明书的一部分。附图示出了实施方式，并且与描述一起用于解释实施方式的原理。容易理解其他实施方式和实施方式的许多预期优点，因为通过参考以下的详细说明将使它们变得更好理解。附图的元件相对于彼此不必是按比例的。相似的附图标记代表相应的相似部件。
图1A-图1B示意性地示出了在半导体基板上沉积金属层的方法的一种实施方式的截面图；
图2示意性地示出了包括核和壳的金属颗粒的一种实施方式的截面图；
图3示出了各种金属颗粒的图像；
图4示意性地示出了涂覆有由金属颗粒制成的两个层的半导体基板的一种实施方式的截面图；
图5示意性地示出了具有由金属颗粒制成的接触垫的功率半导体芯片的一种实施方式的截面图；
图6示意性地示出了半导体基板和直接沉积在该半导体基板上的金属颗粒的一种实施方式的截面图；
图7示意性地示出了半导体基板和沉积在该半导体基板上的若干金属层的一种实施方式的截面图；
图8示意性地示出了半导体基板和沉积在该半导体基板上的焊接材料层的一种实施方式的截面图；
图9示意性地示出了等离子沉积装置的截面图；
图10示出了金属颗粒层的电子显微镜图像；
图11示出了金属颗粒层的光学图像；
图12示意性地示出了安装在载体上的半导体基板的一种实施方式的截面图；
图13示意性地示出了安装在载体上的半导体基板和附接在该半导体基板上的楔形接合物（wedge bond）的一种实施方式的截面图；
图14示意性地示出了安装在载体上的半导体基板和附接在该半导体基板上的钉形接合物（nail bond）的一种实施方式的截面图；
图15A-图15C示意性地示出了用于在基板中制造通孔的方法的一种实施方式的截面图；和
图16示意性地示出了包括堆叠在彼此顶部的两个封装件的器件的一种实施方式的截面图。
具体实施方式
以下参考附图详细说明，附图构成本发明的一部分，并且其中通过本发明实施的具体实施方式的说明的方式。在这方面，方向性的术语，如“顶部”、“底部”、“前面”、“后面”、“领先的”、“结尾的”等，通过参考所描述的图中的取向使用。因为实施方式的组件可以位于大量不同的取向，因此该方向性的术语用于举例说明目的而不是意在进行限制。应该理解，可以利用其他实施方式，并且在不脱离本发明范围的情况下可以做出结构上或逻辑上的改变。因此，以下的详细描述不应被认为是进行限制，本发明的范围由所附的权利要求限定。
除非有其他特别说明，否则应该理解本文中描述的各示例性实施方式的特征可能被彼此结合。
正如本说明书中使用的，术语“耦合的”和/或“电耦合的”并不意味着是指该元件必须是直接连接在一起的；在“耦合的”或“电耦合的”元件之间可以提供插入元件（intervening element）。
具有沉积在半导体基板的一个或多个表面上的多个金属层的半导体基板描述如下。在一种实施方式中，该半导体基板是由半导体材料制成的晶圆，如硅晶体或任何其他的适当的半导体材料。该半导体晶圆作为构建在半导体晶圆内和其上方的电子器件的基板，并经历许多微加工工艺步骤，例如掺杂、离子注入、蚀刻、各种材料的沉积以及图案化。最后，切割该半导体晶圆从而分离独立的半导体芯片。
在一种实施方式中，该半导体基板是半导体芯片。半导体芯片可以是不同的类型，可以通过不同的技术制造并且可以包括，例如，集成电路、电-光电路或电-机电路或无源电路。例如，可将集成电路设计为逻辑集成电路、模拟集成电路、混合信号集成电路、功率集成电路、记忆电路或集成无源电路。此外，可将半导体芯片构造为所谓的MEMS（微机电系统），并且可包括微机械结构，如桥、膜或舌结构。可将该半导体芯片构造为传感器或致动器，例如，压力传感器、加速传感器、旋转传感器、磁场传感器、电磁场传感器、传声器等。该半导体芯片不需要由特定的半导体材料制造，例如，Si、SiC、SiGe、GaAs，并且此外，该半导体芯片可以含有不是半导体的无机和/或有机材料，例如，绝缘体、塑料或金属。此外，该半导体芯片可以是封装的或未封装的。
尤其是，本发明可涉及具有垂直结构的半导体芯片，也就是说，该半导体芯片可以是以电流能够流动通过垂直于该半导体芯片的主表面的方向的半导体材料的方式制造的。具有垂直结构的半导体芯片可以具有多个电极（或接触垫），特别是在其两个主面上，也就是说，在其顶部侧和底部侧上。换句话说，具有垂直结构的半导体芯片具有有源顶部侧和有源底部侧。尤其是，功率半导体芯片可具有垂直结构。例如，该垂直功率半导体芯片可被构造为功率MOSFET（金属氧化物半导体场效应晶体管）、IGBTs（绝缘栅双极晶体管）、JFETs（结型栅场效应晶体管）、功率双极晶体管或功率二极管。举例而言，功率MOSFET的源极和栅极可位于一个主表面上，而该功率MOSFET的漏极则被布置在另一个主表面上。此外，以下描述的器件可包括集成电路，以控制该功率半导体芯片。
将金属颗粒沉积在半导体基板上以形成金属层。金属颗粒包括由第一金属材料制成的核和包围该核的壳。该壳由高度抗氧化的第二金属材料制成。尤其是，该第二金属材料在低于220°C的温度下是抗氧化的，或在一种可替代的实施方式中，200°C。尤其是，金属层在该半导体基板的电极上方形成。因此，在该半导体基板上形成的金属层使得能够与包括在该半导体基板中的集成电路形成电接触。金属层可形成接触垫，尤其是，外部接触垫。金属层的表面可以至少部分被暴露，即，未被其他材料所覆盖。该金属层的曝露表面可以用于芯片键合、线键合和/或模制。
图1A示意性地示出了半导体基板10的截面图，该半导体基板10具有第一主表面11和在第一主表面11对面的第二主表面12。在一种实施方式中，半导体基板10是半导体晶圆。在一种实施方式中，半导体基板10是通过切割半导体晶圆的方式由该半导体晶圆制成的半导体芯片。
图1B示意性地示出了施加于半导体基板10的第一主表面11的金属层13。该金属层13是通过在半导体基板10上沉积金属颗粒14制成的。每一个金属颗粒14包括由第一金属材料制成的核15和包围该核15的壳16。该壳16由高度抗氧化的第二金属材料制成。在一种实施方式中，第二金属材料在高达220°C的温度下是抗氧化的。在一种实施方式中，第二金属材料在高达200°C的温度下是抗氧化的。在一种实施方式中，金属层13的厚度d1范围为1μm至200μm。在一种实施方式中，该厚度d1大于200μm。
图2示意性地示出了用于制造在图1B中所示的金属层13的金属颗粒14之一的截面图。该金属颗粒14具有由第一金属材料制成的核15，其例如可以是铜或铝。核15可以完全由铜和铝中的一种构成。壳16可以充分地包围核15。在一种实施方式中，用于壳16的第二金属材料是贵金属。在一种实施方式中，该第二金属材料是银、金、钯、钛、钽和铌中的一种。由于第二金属材料是耐腐蚀性的并且遮蔽（shield）第一金属材料，因此核15通过壳16而抗腐蚀。
金属颗粒14可具有任何适当的形状，例如，为球形或大致为球形。金属颗粒14的形状不必遵循几何形状，并且对于不同的金属颗粒14可以是不同的。金属颗粒14的平均直径d2的范围可以为300nm至1μm，并且尤其是，从500nm至1μm的范围内。在一种实施方式中，金属颗粒14的平均直径d2大于1μm。核15的平均直径d3的范围可以是从100nm至1μm，尤其是，从100nm至500μm的范围。壳16的平均厚度d4的范围可以是从100nm至500nm。在一种实施方式中，核15的平均直径d3的范围为整个金属颗粒14的平均直径d2的20%至80%。
图3示出了具有不同形状和不同尺寸的各种金属颗粒14的图像。
图4示意性地示出了半导体基板10的截面图，其中金属层13被施加于第一主表面11而金属层19被施加于半导体基板10的第二主表面12。金属层13和19均通过在半导体基板10上沉积上文所述的金属颗粒14而产生。在一种实施方式中，金属层13和19分别具有范围为1μm至200μm的厚度d1和d5。在一种实施方式中，厚度d1和d5中的至少一个大于200μm。金属层13和19的表面粗糙度范围可以为300nm至500nm。该表面糙度可改善金属层13和19上的模制化合物层的粘附性。
在一种实施方式中，半导体基板10是由半导体材料（如硅晶体或任何其他的适合的半导体材料）制成的晶圆。半导体晶圆10的表面积可根据预定的晶圆直径标准化，例如4英寸、8英寸、10英寸或12英寸。半导体晶圆10的厚度可典型地在100μm至1500μm范围内变化，在具体应用中这些数值也可以更小或更大。例如，可通过打磨半导体晶圆10的背面使其变薄，降至范围为30μm至200μm的厚度。半导体晶圆10作为构建在半导体晶圆10内和其上方的电子器件的基板，并经历许多微加工工艺步骤，例如掺杂或离子注入、蚀刻、各种材料的沉积和图案化。最后，通过切割该半导体晶圆10而分离独立的半导体芯片。图4中所示的第一主表面11和第二主表面12可以分别是半导体芯片10的正面和背面。
金属层13和19的作用是形成与电极（或接触垫）的电接触，该电极（或接触垫）嵌入在半导体晶圆10中，这使得能够与包括在半导体晶圆10中的集成电路形成电接触。在一种实施方式中，将金属层13和/或19分别沉积在整个表面11和12上，而未对该金属层13和/或19进一步结构化（构造，structuring）。在一种实施方式中，金属层13和19中至少一个在其沉积后被结构化。例如，结构化可通过使用光刻工艺来进行。出于此目的，将光刻胶层印刷或旋涂于待结构化的金属层13、19的顶部上。通过掩模暴露于具有适合波长的光并随后显影，在光刻胶层中形成凹槽。随后在蚀刻过程中除去该金属层13、19通过该凹槽暴露的部分。然后，通过使用适当的溶剂揭除该光刻胶层。可制成具有任何期望的几何形状的结构化金属层13、19。
为了获得独立的半导体芯片，将半导体晶圆10分割，例如，通过切锯、激光消融、切割、蚀刻或任何其他适合的技术。
图5示意性地示出了由上文所述的工艺步骤获得的半导体芯片20的截面图。在一种实施方式中，半导体芯片20是功率二极管或功率晶体管，例如功率MOSFET、IGBTs、JFET或功率双极晶体管。半导体芯片20具有垂直结构，并在第一主表面11上具有第一负载电极21，以及在第二主表面12上具有第二负载电极22。而且，功率半导体芯片20在第一主表面11上可具有控制电极23。在图5中示例性示出的功率MOSFET的情况下，第一负载电极21和第二负载电极22分别是源极和漏极，而控制电极23是栅极。在操作过程中，可在负载电极21和22之间施加高达5V、50V、100V、500V或1000V或甚至更高的电压。施加于控制电极23的转换频率范围可以是从1kHz至100MHz，但是也可以在这个范围之外。
电极21-23被整合到半导体芯片20的半导体材料中。该半导体材料可在电极21-23的位置处在一定程度上被掺杂，以便产生导电性。将包括如上联系图2描述的金属颗粒14的金属层13和19分别沉积在半导体芯片20的第一主表面11和第二主表面12上。由于两个电极21和23位于第一主表面11上，因此在那里构造（structure）金属层13。由于电极22在整个第二主表面12上延伸，因此金属层19覆盖半导体芯片20的整个第二主表面12。如图5中所示的金属层13和19能够作为接触垫以便向嵌入在半导体芯片20中的集成电路提供电接入（electrical access）。
图6示意性地示出了半导体基板10的截面图，其中将包括金属颗粒14的金属层13直接沉积在半导体基板10的半导体材料上。暴露背向半导体基板10的金属层13的表面25，即没有其他金属沉积在表面25上。该表面25能够，例如，用于将半导体基板10附接于载体（如引线框架），或用于附接于接合线。
图7示意性地示出了金属层26和27被设置在半导体基板10和金属层13之间的半导体基板10上的截面图。金属层26可由包括铝或任何其他适合的金属或金属合金制成，并且可用来与半导体基板10的掺杂部分形成电接触。金属层27的功能是作为在焊接过程中保护半导体基板10的半导体材料的扩散阻挡层。金属层27的另一个功能是粘合层，其能够使金属层13粘附于半导体基板10。例如，金属层27可由钛、钨化钛（titaniumtungsten）、氮化钛或其他的适当的金属或金属合金构成。
图8示意性地示出了如图7中所示的具有沉积在第一主表面11上的金属层26、27和13的半导体基板10的截面图。与图7中的暴露金属层13的表面25的实施方式不同，在图8的实施方式中，表面25涂覆有焊接材料层28。例如，该焊接材料可由AuSn、AgSn、CuSn、Sn、AgIn和CuIn中的一种或多种构成。
也可将如上所述以及图6-图8中所示的金属层26-28施加于半导体基板10的第二主表面12。
可采用各种技术将如图2中所示的金属颗粒14沉积在半导体基板10上，例如，喷涂、印刷或扩散（dispensing）。在一种实施方式中，在沉积之后将热和/或压力施加于金属颗粒14，以改善金属层13的机械稳定性。在一种实施方式中，利用如图9中示意性示出的等离子沉积装置来沉积金属颗粒14。
等离子沉积装置由等离子体射流（或束）发生器30和与该等离子体射流发生器30物理分离的反应室31构成。
等离子体射流发生器30包括介电屏障（dielectric barrier）32（例如电绝缘管）、外电极33、和内电极34，其中外电极33同心地包围介电屏障32，内电极34至少部分地被容纳在介电屏障32中。等离子体射流发生器30的一端以等离子体头（plasma head）35结束。
在操作等离子体射流发生器30时，通过将适当的电压施加于两个电极33和34产生辉光放电。在图9中的箭头36指示的方向上提供工艺气体，从而产生等离子体射流37。等离子体射流37经由等离子体头35离开等离子体射流发生器30。
等离子体射流发生器30经由反应室31中的开口38连接到反应室31，从而允许等离子体射流37流入到反应室31中。开口38可抵靠等离子体头35的开口而被密封，以避免周围空气进入反应室31中。反应室31与等离子体射流37的产生物理分离。
反应室31具有入口39，该入口39允许将载气40吹入反应室31。将载气40引入反应室31中并与所产生的等离子体射流37混合，以便激活载气40或产生粒子束。活化的载气41经由出口42离开反应室31。将半导体基板10放置在适当的位置以使活化的载气41涂覆半导体基板10的表面。
如图9所示，可以将载气40的入口39横向地布置于等离子体射流37，以便将载气40引入反应室31中，从而使等离子体射流37形成漩涡（swirl）或发生偏离。
将包含如图2所示的金属颗粒14的载气40沉积在半导体基板10上。载气40中的气流和/或粒子流在反应室31中与等离子体射流37混合。从而等离子体射流37的大部分能量被转移至载气40中的气流和/或粒子流。因此，只有非常小部分等离子体射流37与半导体基板10的表面接触。
可将周围空气排除在反应室31之外，例如，通过施加合适的压力。这避免了不期望发生的周围空气、等离子体射流37和载气40之间的副反应。
如上所述的等离子体沉积方法使得能够制造等离子体沉积的金属颗粒14的金属层13和19。该等离子体沉积方法也被称为等离子体电刷方法（plasma brushing method）。当使用上文中提到的等离子体沉积方法时，金属颗粒14的速度和处理温度相对较低。将金属颗粒14设计成使得在等离子体沉积方法期间金属颗粒14不发生氧化。
图10是利用如上文所述的等离子沉积装置沉积的金属颗粒层的电子显微镜图像。通过聚焦离子束技术在金属颗粒层中产生孔。
图11是利用如上文所述的等离子沉积装置沉积的穿过金属颗粒层的部分的光学图像。从图9和图10可以看出，由于等离子体沉积，金属颗粒层表现出特定的孔隙率。
图12示意性地示出了如图1B所示的安装在载体50上的半导体基板10的截面图，该载体50具有其第一主表面11和面向载体50的金属层13。
载体50可以是任何形状、尺寸或材料。而且，可将载体50连接于其他载体50。为了在制造过程中分离载体50，可通过连接装置将载体50彼此连接。载体50的分离可能通过机械切锯、激光束、切割、冲压、碾磨、蚀刻或任何其他适当的方法实施。载体50可以是电传导性的。载体50可以完全由金属或金属合金制成，尤其是，铜、铜合金、铁镍、铝、铝合金、或其他的适当的材料。此外，载体50可镀覆有导电材料，例如铜、银、铁镍或镍磷。例如，载体50可是引线框架或引线框架的一部分。
在一种实施方式中，图12中示出的半导体基板10是通过金属层13与载体50电耦合的半导体芯片。
为了向载体50中加入金属层13，可以实施扩散焊接过程。在一种实施方式中，将焊接材料层沉积在金属层13上。通过热板供热或在烘箱中将载体50加热至高于该焊接材料的熔点的温度。使用能够拾取半导体基板10的拾放工具（pick-and-place tool）并且将其放置在加热的载体50上。在焊接处理期间，可将半导体基板10按压到载体50上持续一段适当的时间，该时间范围为10至200ms之间。
通过使用高熔融点的金属层13和载体50使得焊接材料形成耐高温和高机械稳定性中间金属相，从而在焊接的过程中，该焊接材料在能够经受高温的金属层13和载体50之间产生金属连接（金属接头，metallic joint）。在该过程中，低熔点的焊接材料完全转变，即它完全地变成中间金属相。随着焊接材料层的厚度增加，该过程是受控扩散的并且其持续（时间）增加。
在一种实施方式中，通过使用低温连接技术（LTJT）将半导体基板10连接于载体50。在这种情况下，能够省去焊接材料，并且可将金属层13直接放置在载体50的上表面上。因此，不必将温度升高至焊接材料的熔融温度。因此，利用低于例如300°C温度将金属层13附接于载体50。
包含在金属层13内的金属颗粒14的抗腐蚀壳16能够防止金属颗粒14的核15发生氧化。因此，可以利用铜或铝作为核材料，两者均有可能产生氧化表面。壳16确保金属层13不含有不期望的氧化物，这会增加接触电阻并由此减少导电性和导热性。
在一种实施方式中，金属颗粒14的核15的第一金属材料比壳16的第二金属材料具有更高的硬度。例如，该第一金属材料是铜，而第二金属材料是银或金。在一种实施方式中，第一金属材料具有比第二金属材料更低的硬度。在这种情况下，该第一金属材料是，例如，铜或铝，而第二金属材料是钯、钛、钽和铌中的一种。
在一种实施方式中，核15的第一金属材料比壳16的第二金属材料具有更高的热膨胀系数。例如，第一金属材料是铝，而第二金属材料是银、金、钯、钛、钽和铌中的一种。或者，第一金属材料是铜，而第二金属材料是金、钯、钛、钽和铌中的一种。在一种实施方式中，核15的第一金属材料比壳16的第二金属材料具有更低的热膨胀系数。例如，第一金属材料是铜，而第二金属材料是银。第一材料和第二材料的不同热膨胀系数使得能够影响半导体基板10和载体50之间的机械应力，其在温度循环中通常也具有不同的热膨胀系数。因此，机械应力会减少，或者，会增加。例如，在功率半导体芯片的漂移区中的应力增加导致由于导通电阻引起的功率损耗的减少。
图13示意性地示出了安装在如图12所示的载体50上的半导体基板10的截面图，以及，附接于沉积在半导体基板10的第二主表面12上的金属层19的楔形接合物51（参见图4）。在图13中示出的实施方式中，半导体基板10是半导体芯片，尤其是功率半导体芯片，载体50是引线框架。
楔形接合物51被直接附接于金属层19上。出于此目的，使用楔形或针状的接合工具将接合线的末端按压到该金属层19上。通过使用短的超声脉冲（short ultrasound impulse），然后将该接合线在该金属层19的表面上熔化并熔融在该金属层19的表面上。在接合线和金属层19之间形成电连接。然后将该楔形接合物从第一接合点移动到第二接合点，例如，定位于载体50的引脚（pin）或引线（lead）上。在此重复该接合过程，由此另外地切断接合线。
图13还示出了通过扩散焊接方法在半导体基板10和载体50之间的界面处制造的中间金属相52。
图14示意性地示出了类似于图13中示出的实施方式的安装在载体50上的半导体基板10的截面图。与图13不同，图14中示出的实施方式包括直接附接于金属层19上的钉形或球形接合物53。对于这种类型的接合技术，使用针状毛细管，通过该针状毛细管形成（feed）该接合线。将高电压的电荷施加于该接合线。这使得接合线在毛细管的尖端处熔化。由于该熔融金属的表面张力，该接合线的尖端形成钉形或球形。该钉形或球形快速地凝固，并且使该毛细管降低到通常被加热的金属层19的表面。然后将该毛细管向下压，并用所附接的换能器（transducer）施加超声能。组合的热、压力和超声能在接合线尖端处的钉状物或球状物和金属层19的表面之间形成焊接点（weld）。然后该接合线通过毛细管穿出，并将该毛细管从第一接合点移动到第二接合点处，例如，定位于载体50的引脚或引线上。在此重复该接合过程，由此另外地切断接合线。
图15A-图15C示意性地示出了一种实施方式的截面图，其中利用图2的金属颗粒14在基板中制造通孔。
图15A示意性地示出了基板60。在一种实施方式中，基板60是半导体基板，例如，半导体芯片。在一种实施方式中，基板60包括嵌入到封装材料中的半导体芯片，例如，模制化合物、层压材料或预浸渍材料。
图15B示意性地示出了在基板60中制造的贯通孔61。该贯通孔61从第一主表面62延伸到基板60的相对的第二主表面63。可通过利用激光消融、机械钻孔、蚀刻或任何其他适合的技术来制造贯通孔61。在基板60包括覆盖半导体芯片的封装材料的情况下，该贯通孔61可完全地贯通该封装材料。
图15C示意性地示出了将包括如上所述的核15和壳16的金属颗粒14填充到贯通孔61中以产生电导性通孔64的金属颗粒14。该通孔64从第一主表面62延伸到基板60的第二主表面63。此外，可在第一主表面62和/或第二主表面63上制造接触垫。可采用各种技术将金属颗粒14沉积在贯通孔61中，例如，喷涂、印刷、扩散或如上文所述和在图9中示出的等离子沉积。
图16示意性地示出了包括在在顶部彼此堆叠的两个封装件70和71的器件的截面图。封装件70和71中的每一个包括一个或多个半导体芯片。可将半导体芯片嵌入到封装材料中，例如，模制化合物、层压材料或预浸渍材料。封装件71包括填充有连同图15C一起的描述的金属颗粒14的若干通孔64。封装件70通过焊球72的方式与通孔64电耦合。此外，焊接球73附接于封装件71和通孔64的下表面。焊球73允许将封装件71安装在电路板上。
此外，尽管已经在若干种实施方式中的仅一种实施方式披露了本发明的实施方式的独特特征或方面，但这样的特征或方面可能与其他实施方式的一个或多种其个特征或方面相结合在任何给定的或具体应用中可以是期望的和有利的。而且，说明书或权利要求中使用的术语“包括”，“具有”，“与”，或它们的其他变形意味着类似于术语“包括”的包含性方式。而且，应当理解，本发明的实施方式可在离散电路中实施，部分地在集成电路或完全地集成电路或编程工具中实施。此外，例如，术语“示例性的”仅仅意味着作为举例，而不是最好的或最佳的。应理解，在本文中描述的特征和/或元件通过与相对于彼此以特定尺寸示出，目的是简化并且和容易理解，并且，实际尺寸可以与在本文中示出的显著不同。
虽然已经在本文中说明和描述了具体实施方式，但本领域普通技术人员应理解，在不脱离本发明范围的情况下，可以使用各种代替和/或等价的实施方式来代替所说明和描述的特定实施方式。本申请意图覆盖任何应用或本文中讨论的具体实施方式的变形。因此，这意味着本发明仅由权利要求和其等同替代限定。

Claims (25)

1.一种用于制造半导体器件的方法，所述方法包括：
提供半导体基板；和
通过在所述半导体基板上沉积金属颗粒而在所述半导体基板上形成金属层，其中所述金属颗粒包含由第一金属材料制成的核和包围所述核的壳，所述壳由抗氧化的第二金属材料制成。
2.根据权利要求1所述的方法，其中，所述第一金属材料包含铜和铝中的至少一种。
3.根据权利要求1所述的方法，其中，所述第二金属材料包含银、金、钯、钛、钽和铌中的至少一种。
4.根据权利要求1所述的方法，其中，所述第二金属材料是贵金属。
5.根据权利要求1所述的方法，其中，所述金属颗粒的直径大于300nm。
6.根据权利要求1所述的方法，其中，所述半导体基板包含功率集成电路。
7.根据权利要求1所述的方法，进一步包括在制造所述金属层之后将所述半导体基板切割成独立的半导体芯片。
8.根据权利要求1所述的方法，其中，沉积所述金属颗粒包括产生等离子体射流，并将所述等离子体射流与包含所述金属颗粒的载气混合。
9.根据权利要求8所述的方法，其中，使所述等离子体射流在反应室中与所述载气混合，其与所述等离子体射流的产生物理分离。
10.根据权利要求1所述的方法，进一步包括将接合线直接附接在所述金属层上。
11.根据权利要求1所述的方法，进一步包括将所述半导体基板附接至具有面向金属载体的所述金属层的金属载体。
12.根据权利要求1所述的方法，其中，所述第一金属材料的热膨胀系数高于所述第二金属材料的热膨胀系数。
13.根据权利要求1所述的方法，其中，所述第一金属材料的热膨胀系数低于第二金属材料的热膨胀系数。
14.根据权利要求1所述的方法，其中，所述金属层形成一个或多个接触垫。
15.根据权利要求1所述的方法，进一步包括在所述半导体基板中制造贯通孔，并且用所述金属颗粒填充所述贯通孔。
16.根据权利要求1所述的方法，进一步包括在所述金属层上沉积一层焊料。
17.一种用于制造半导体芯片的方法，所述方法包括：
提供半导体晶圆；
通过等离子体在所述半导体晶圆上沉积金属颗粒而在所述半导体晶圆上形成金属层，其中所述金属颗粒包含由铜和铝中的至少一种制成的核和包围所述核的壳，所述壳由银、金、钯、钛、钽和铌中的至少一种制成；和切割所述半导体晶圆，从而分开所述半导体芯片。
18.一种用于在半导体基板中制造通孔的方法，所述方法包括：
提供半导体基板；
在所述半导体基板中制造贯通孔；和
在所述贯通孔中沉积金属颗粒，其中所述金属颗粒包含由第一金属材料制成的核和包围所述核的壳，所述壳由抗氧化的第二金属材料制成。
19.一种半导体器件，包括：
包括第一电极的半导体芯片；和
施加于所述半导体芯片的所述第一电极的金属颗粒，其中所述金属颗粒包含由第一金属材料制成的核和包围所述核的壳，所述壳由抗氧化的第二金属材料制成。
20.根据权利要求19所述的半导体器件，其中，所述半导体芯片包括第一主表面和与所述第一主表面相对的第二主表面，所述第一电极被布置在所述第一主表面上而所述第二电极被布置在所述第二主表面上。
21.根据权利要求20所述的半导体器件，进一步包含施加于所述半导体芯片的所述第二电极的另外的金属颗粒，其中所述另外的金属颗粒包含由第一金属材料制成的核和包围所述核的壳，所述壳由第二金属材料制成。
22.根据权利要求21所述的半导体器件，进一步包含金属载体和接合线，其中施加于所述第一电极的所述金属颗粒附着于所述金属载体，而施加于所述第二电极的所述另外的金属颗粒附着于所述接合线。
23.根据权利要求19所述的半导体器件，其中，所述半导体芯片是功率MOSFET、IGBT、JFET、功率双极晶体管和功率二极管中的一种。
24.根据权利要求19所述的半导体器件，其中，所述第一金属材料包含铜和铝中的至少一种，而所述第二金属材料包含银、金、钯、钛、钽和铌中的至少一种。
25.根据权利要求19所述的半导体器件，进一步包含嵌入所述半导体芯片的封装材料和所述封装材料中的填充有所述金属颗粒的贯通孔。
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