CN102009946A - 制造包含微结构化或纳米结构化的元器件的构件的方法 - Google Patents

制造包含微结构化或纳米结构化的元器件的构件的方法 Download PDF

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CN102009946A
CN102009946A CN2010102738074A CN201010273807A CN102009946A CN 102009946 A CN102009946 A CN 102009946A CN 2010102738074 A CN2010102738074 A CN 2010102738074A CN 201010273807 A CN201010273807 A CN 201010273807A CN 102009946 A CN102009946 A CN 102009946A
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nano
parts
micro
structural
layer
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A·库格勒
R·埃伦普福特
M·布鲁恩德尔
F·哈格
F·桑德迈耶
U·肖尔茨
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Robert Bosch GmbH
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Robert Bosch GmbH
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Abstract

本发明涉及一种用于制造包含微结构化或纳米结构化的元器件的构件的方法,包括步骤:提供载体(1),其包括施加在载体(1)上的连接层(2),在连接层(2)的表面上施加另一个层(3),其中该另一个层(3)包括导电的区域,该另一个层(3)包括至少两个上下设置的不同的层并且在一个层中存在的导电区域面对着载体,在该另一个层(3)的顶面上施加至少一个微结构化或纳米结构化的元器件(4,4’),用包封材料(6)至少部分地包封微结构化或纳米结构化的元器件(4,4’)并且从连接层(2)上分离所获得的、包括包封材料(6),至少一个微结构化或纳米结构化的元器件(4,4’)和另一个层(3)的复合体。

Description

制造包含微结构化或纳米结构化的元器件的构件的方法
技术领域
本发明涉及一种用于制造包含微结构化或纳米结构化的元器件的构件的方法。该方法包括提供载体的步骤,该载体包括施加在载体上的连接层。此外该方法包括在连接层的表面上施加另一个层,其中该另一个层包括导电的区域,其中该另一个层包括至少两个相互上下设置的不同的层(子层)并且在一个层(子层)中存在的导电的区域面对着载体。此外本发明涉及一种按照该方法获得的构件和该构件的使用。
背景技术
传感器通常被封装在以冲裁栅条或衬底为基的包封壳(模制壳)中。这些包封壳可以是基于铜-塑料壳(铜-引线框)的衬底作为实施形式,其包括具有连接引脚的壳(带引线的壳)或者没有连接引脚的壳(不带引线的壳)。在此情况下,单个的传感器或ASIC(专用集成电路)或者被相互并列地或者相互上下地安置在衬底上,随后接着进行环绕浇铸过程。但是新型的无衬底的壳(框)被越来越多地研发。
芯片封装的一种变型被称为eWLB(Embedded Wafer Level Ball-Grid-Array(嵌入式晶圆级球栅阵列))。在此情况下,芯片以其有源面(工作面)装配到晶圆载体的暂时的支承箔上并且接着用模压材料包封。然后从支承箔上去除在该工艺中形成的所谓的塑料晶圆(reconstituted wafer(重构晶圆)),以便可以在有源面上进行再分布(重新布线(Umverdrahtung))。
为了再分布,应用标准薄层技术和材料。然后在为了再分布而制造的导通孔和它们相应的表面上配设焊阻漆并且通过锯切使元器件从塑料晶圆上各个分开,这种设计的缺陷是在浇铸(模塑)之后敏感的芯片表面处于敞露状态。因此必须应用昂贵的薄层技术,以便能够实施再分布。这在制造这种包含微结构化或纳米结构化的元器件的构件时要求一种净化室基础设施。
例如在US2004/0169264中描述了一种用于集成电路的配置(封装)结构和一种用于制造该集成电路的方法。其中元器件用一个填充层包封,随后在另一个步骤中接着施加一个有机层,使该有机层中形成导通孔并且与一个布线层连接。但这是有缺陷的,因为元器件以背面放置在衬底上并由此它们的工作面不被保护。
值得期望的是一种微结构化或纳米结构化的元器件的改进的制造方法,其中元器件在被施加上之后处于被保护状态并且同时借助于通常的工艺在后续过程中可以被接触。
发明内容
因此按照本发明建议一种用于制造包含微结构化或纳米结构化的元器件的构件的方法,包括步骤:
提供载体(支承板),包括施加在载体上的连接层;
在连接层的顶面上施加另一个层,其中该另一个层包括导电的区域,该另一个层包括至少两个上下设置的不同的层并且在一个层中存在的导电的区域面对着载体;
在该另一个层的顶面上施加至少一个微结构化或纳米结构化的元器件;
用包封材料至少部分地包封该微结构化或纳米结构化的元器件;
从连接层上分离所获得的、包括包封材料、至少一个微结构化或纳米结构化的元器件和该另一个层的复合体。
按照本发明的方法的一个优点是可以简化现有的eWLB方法。以符合工艺流程的方式,在分离的工艺步骤中实施复合体的分离,同时不使得微结构化或纳米结构化的元器件在被设置用于再分布的一侧上处于暴露状态,其中在下一个步骤中可以接着实施对构件的单个分割。这可以避开使用净化室技术设备。由此可以在净化室外面实施构件的制造。同样也可以得到加工形式的自由造型,因为它不是强制性地受晶片成形的束缚,其按照现有技术只能够在净化室中实施。同样也提供模塑方法的自由选择,因为可以使加工形式与模塑方法相适配。
在本发明的意义下的微结构化或纳米结构化的元器件尤其是具有在≥1nm至≤100μm范围中的内部结构尺寸的元器件。内部结构尺寸在此情况下是指在元器件内部的结构如例如牵条(Streben)、连接条(Stegen)或印刷电路走线(印刷导体)的尺寸。
该微结构化或纳米结构化的元器件可以具有被设置用于与另一个微结构化或纳米结构化的元器件电性接触的区域。这样的一个区域也可以称为有源面(工作表面)、连接垫或连接触头。这些微结构化或纳米结构化的元器件可以包括集成电路,传感器元件,被动元器件,陶瓷电容器,电阻或执行器等等。这些元器件然后形成一个系统,该系统在分割成单个之后具有独立的配置(封装结构)。
按照本发明的方法的第一步骤包含提供一个载体,其中该载体包括施加在该载体上的连接层。按照本发明,载体的材料例如可以选自包括陶瓷、金属或高熔融性塑料构成的组。金属可以从优质钢1.4034和/或1.4310的组中选取。在本方法中载体可以被用作批量技术的基础。
利用连接层可以将微结构化或纳米结构化的元器件以优选的布置方式固定在载体上。
连接层优选被均匀地施加在载体的顶面上。使用的连接层可以具有直到200℃的无分解的温度稳定性。在这种情况下,连接层也可以包括一个粘合膜。尤其是将连接层以离心涂镀的方式或者通过喷漆涂装方式涂覆在载体上面。此外可以通过对连接层进行印刷、气流喷射、配量撒布(dispenst)、层压、结构化或非结构化或者在涂覆之后结构化,将连接层涂覆到载体上面。连接层的层厚可以在≥0.25μm至≤200μm的范围中,优选在≥1μm至≤100μm的范围中,特别优选在≥2μm至≤10μm的范围中。
按照本发明的方法的另一个步骤包括在连接层的顶面上施加另一个层,其中该另一个层包括导电的区域,其中该另一个层包括至少两个上下设置的不同的子层并且在一个子层中存在的导电的区域面对着载体。为此优选连接层的至少一个部分区域与该另一个层接触。此时该层在本发明的意义下可以包括一个由至少两种不同的材料组成的层。在另一个变型方案中,其中一种材料可以嵌入另一种材料中。此时至少一种材料包括可导电的材料并且优选另一种材料包括绝缘材料。优选另一个层被如此地施加在连接层上,即使得导电的层接触连接层。这种布置的一个优点是,在分离(剥离)之后的一个较后的工艺步骤中可以对导电的区域实施直接的结构化。
接下来将至少一个微结构化或纳米结构化的元器件施加在所述另一个层的顶面上。此时微结构化或纳米结构化的元器件的至少一个部分区域与所述另一个层的顶面接触。此外尤其是微结构化或纳米结构化的元器件的有源面可以接触所述顶面。微结构化或纳米结构化的元器件的施加可以用自动装配机实施。附加地,可以通过对载体、元器件和/或连接层加热来方便微结构化或纳米结构化的元器件的施加。
所述另一个层可以被交联和/或硬化。例如这可以通过一个温度处理步骤或通过紫外线照射来实施。
按照本发明的另一个步骤涉及用包封材料至少部分地包封微结构化或纳米结构化的元器件。包封材料的其它名称也称为浇注材料、模塑混合物组分、浇铸材料、压铸材料、环铸材料、造型材料和/或压制材料。此外,包封材料可以具有填充材料。该填充材料用于调配材料特性。该包封材料尤其可以直接地包封微结构化或纳米结构化的元器件。包封材料可以通过加热进行交联和时效硬化。包封材料例如可以从环氧树脂、聚丙烯酸酯、聚甲醛和/或硅树脂的组中选取。
使用的包封材料有利地具有低的漏电特性、高的均匀性、低的折射指数、低的收缩度和/或低的导热系数。此外,使用的包封材料可以具有一种热膨胀系数,它可以与硅的热膨胀系数的值相差直至10倍的倍数,使用的包封材料也可以具有尤其是高的弹性模数和玻璃转变温度。
在本发明的范围中,用语“包封”在此包括环绕注塑、压铸、浇铸、层压的方法以及在使用英语专业术语情况下的模制造型(molding)、转移造型(transfer molding)和注射模塑(injection molding)、罐封(模封)(potting)、液体成型(liquid molding)、压缩模塑(compression molding)和片状模塑(sheetmolden)的方法。
在用包封材料进行包封之后接着例如可以加热获得的配置。所述获得的配置在此情况下是指由前面的方法步骤中获得的被包封的元器件。这个步骤也称为封胶后烘烤(或称为后固化)(PMC)(Post-Mold-Cure)步骤。在本发明内使用了造型材料所需要的PMC步骤,以便使造型材料实现硬化和最终交联。
按照本发明的方法的另一个步骤涉及从连接层上分离获得的复合体,该复合体包括包封材料、至少一个微结构化或纳米结构化的元器件和所述另一个层。分离是指可以将包封材料与微结构化或纳米结构化的元器件和另一个层一起从连接层上分开。为此尤其是为了从连接层上分离所述另一个层要施加的力应该小于从所述另一个层上分离包封材料而要施加的力。
接下来可以实施用于制造导通孔、另一个层的结构化和再分布(再布线)的通常的方法步骤。例如借助于激光实现在另一个层中制造导通孔。为此使用具有组合式激光系统的激光钻机。
在此之后可以借助于导电的层使导通孔金属化。作为导电的层为此尤其可以应用金属的导体和/或具有导电能力的聚合体。为此尤其可以在用激光器钻孔之后实施钻孔的清洗和金属化。接着可以用钯激活该表面,以便可以以化学方式施加上铜(层厚为0.5至0.8μm)。作为最后的步骤可以以电镀的方式施加上铜,其中可以使用所谓的脉冲电镀技术。
在按照本发明的方法的另一个方案中,在所述另一个层中,导电的区域包括铝层、铜层、银层、镍层、钯层、铬层、氮化钛层、可导电的聚合物和/或金层。这些材料除了它们的良好导电性和可结构化性以外还可以具有高的导热率系数,其可以良好地传导在运行期间形成的热量。
在另一种变型方案中,所述另一个层包括一个由铜、镍和金构成的复合体或者由铜、镍、钯和/或金钯构成的复合体。这个复合体可以被部分地预结构化。该复合体也可以例如包括一个在导电的区域上的掩模。有利地,所述另一个层尤其可以具有用于定位微结构化或纳米结构化的元器件的校准标记。在此情况下,这些校准标记可以是穿透的。在本发明的意义下这是指,这些校准标记被所述另一个层穿过并且由此不仅在面对着载体的一侧上而且在相对的一侧上都是敞开的。
在按照本发明的方法的另一个实施形式中,所述另一个层是覆铜的树脂箔。例如该箔可以对应于一种层叠在绝缘树脂上的铜箔,也称为RCC箔(resin-coated-copper foil(涂树脂铜箔))。树脂可以从环氧树脂或聚丙烯酸酯的组中选择。这种箔的一个优点是它可以作为复合材料在一个惟一的方法步骤中施加。由此可以简化工艺管理,因为可以同时在现有的方法中将箔施加到衬底上。在使用RCC箔的情况下在此处也具有优点,即可以由RCC箔保护微结构化或纳米结构化的元器件的有源面。
在按照本发明的方法的另一个实施形式中,微结构化或纳米结构化的元器件由包括微机电系统(MEMS)、专用集成电路(ASICS)、半导体元器件和/或传感器元件的组中选取。传感器元件最好可以是在加速度传感器、转速传感器、压力传感器、磁传感器、霍尔传感器、质量流量传感器、气体传感器、光学传感器、湿度传感器、介质传感器和/或多芯片模块中的组成部分。
例如半导体元器件可以选自包括有源像素传感器、电荷耦合器件(CCD)传感器、接触式图像传感器、Diac(交流电二极管)、数字像素传感器、电子倍增管CCD、光电四极管、门阵列、门极可关断(GTO)晶闸管、半导体继电器、半导体存储器、(晶体管)集成度(Integrationsgrad)、微处理器、神经形态芯片、光电耦合器、位置敏感器件、太阳能电池、电流反馈式运算放大器、半导体闸流管、可控硅调节器、可控硅四极管、可控硅塔、飞行时间传感器、压力传感器、加速度传感器、温度传感器、转速传感器、质量流量传感器、磁传感器、气体传感器、霍尔传感器、湿度传感器、沟槽技术和/或视频随机存取存储器(Video-RAM)的组。通过按照本发明的方法获得的好处是可以将多个传感器以节省空间的方式相互并排地布置,其中元器件的功能稳定性通过已经在过程中施加的含有导电的区域的另一个层得到改善。
按照本发明的方法的另一种变型方案包括方法步骤,在至少两个微结构化或纳米结构化的元器件的情况下,制造导通孔并且通过对覆铜树脂箔的再分布借助于覆铜树脂箔使元器件相互接触。微结构化或纳米结构化的元器件例如在它们与载体面对着的一侧上包括被设置用于接触的区域,例如连接垫或连接触头,其中这些区域至少部分地接触覆铜树脂箔。
按照本发明的方法最好包括制造导通孔的步骤,该导通孔穿过所述另一个层通到微结构化或纳米结构化的元器件的被设置用于接触的区域。通过激光钻孔和金属化工序可以制造出电性触头。此外,可以以化学的和/或物理的方式制造导通孔。尤其是可以通过化学蚀刻制造导通孔。RCC箔现在可以将相应的微结构化或纳米结构化的元器件相互连接起来。这些连接部分还可以以电镀的方式加强。
所述另一个层可以先用紫外线激光器打开并且该层接着可以用CO2激光器继续去除,直到达到微结构化或纳米结构化的元器件。该组合系统的优点是微结构化或纳米结构化的元器件不会受到CO2激光器损伤。
在按照本发明的方法的另一实施形式中,在用包封材料包封微结构化或纳米结构化的元器件期间,一个凸模至少部分地接触微结构化或纳米结构化的元器件。此时可以在用包封材料包封之后,在包封材料还没有硬化时,使凸模接触微结构化或纳米结构化的元器件。为此将凸模压入包封材料中。同样也可以在用包封材料包封之前使凸模接触微结构化或纳米结构化的元器件并且接着进行包封。由此可以在包封材料硬化之后在一个较后的工艺步骤中再去除凸模,从而可以建立介质接触微结构化或纳米结构化的元器件的通道。一个优点是,尤其是在再分布之后才可以去除凸模,从而微结构化或纳米结构化的元器件不会受到前面的方法步骤的损伤。
按照本发明的方法最好包括使构件各个分开的步骤。为此构件可以或者在再分布前或者在再分布后借助于锯子被各个分割开,以便获得独立的配置。由此可以实现灵活的工艺过程控制。
本发明的主题此外是一种通过按照本发明的方法获得的构件,包括由包封材料包围的微结构化或纳米结构化的元器件,其中微结构化或纳米结构化的元器件至少部分地接触另一个层,其中该另一个层包括至少一个导通孔,该导通孔通到微结构化或纳米结构化的元器件的被设置用于接触的区域并且该导通孔与一个导电的层电性地接触。微结构化或纳米结构化的元器件尤其可以从包括MEMS,ASIC的组中选取。所述构件有利地具有一个覆铜树脂箔,它可以在另一个步骤中被结构化。具有这种箔作为再分布基础的所述构件具有的优点是,它们尤其具有传感器的微型化封装。
在一个实施形式中,按照本发明的构件此外包括一个凹部,该凹部从外部穿过与微结构化或纳米结构化的元器件相邻接的材料并且一直达到微结构化或纳米结构化的元器件。备选地,该凹部可以附加地穿过包括所述可导电的区域的箔。由此例如可以使介质接近被封装的元器件如传感器。此时传感器可以是压力传感器、流体传感器和/或化学传感器等等。有利地,由此可以使间隙与外部介质进行联通,其中这可以有利地通过流体联通来实现。
本发明的另一个主题涉及所述构件在压力传感器、加速度传感器、温度传感器、转速传感器、质量流量传感器、磁传感器、气体传感器、霍尔传感器和/或湿度传感器中的使用。此时这些传感器是指完成的系统,其包括电子评估装置。通过按照本发明的方法例如可以制造成本更加有利的分析系统,因为按照本发明的方法可以插入到一个现有的方法中。同样有利的是,可以在使用多个具有不同功能的元器件下实现多功能传感器的制造并且这些元器件可以在利用批量加工工艺过程下生产。
附图说明
本发明依据以下的附图继续进行描述。附图所示:
图1是一个提供的载体,
图2是在施加RCC箔之后的步骤的视图,
图3是施加微结构化或纳米结构化的元器件的步骤的视图,
图4是在施加包封材料之后的步骤的视图,
图5是在分离之后的步骤的视图,
图6是在制造导通孔之后的步骤的视图,
图7是在导通孔金属化之后的步骤的视图,
图8是具有两个凹部的构件的视图。
具体实施方式
图1示出了一个提供的载体1,具有位于载体上的连接层2。连接层2此时平面地放置在载体1上。载体1的材料有利地是优质钢(不锈钢),尤其是在本情况下是优质钢1.4034。连接层2在本情况下包括尤其是以聚合物为基的材料。
图2示出了在连接层2上涂覆了另一个层3之后的状态。该另一个层3在本情况下应该是一个RCC箔3。RCC箔3此时包括一个环氧树脂层3a和一个铜层3b,如在放大的图中所示。在RCC箔3中含有的环氧树脂层3a位于铜层3b上面并且在这种情况下形成用于施加元器件的侧面。
在图3中施加上了微结构化或纳米结构化的元器件4和4’。在本例中,微结构化或纳米结构化的元器件4可以是MEMS而微结构化或纳米结构化的元器件4’可以是ASICS。此时元器件4,4’不仅在它们的形状上而且在它们的功能上都可以是不同的。微结构化或纳米结构化的元器件4,4’如此深地挤入到RCC箔3中,使得它们的接触部位完全被RCC箔3遮住。微结构化或纳米结构化的元器件4,4’被施加到RCC箔3的环氧树脂层3a上。元器件4,4’具有面对着载体1的接触部位5和5’,它们位于环氧树脂层3a内部,在此之后环氧树脂层3a被交联。
在下一个步骤中,浇铸图3中所示的配置结构。图4示出了包封材料6接触微结构化或纳米结构化的元器件4,4’的方式。接着可以加热到一个温度,在该温度下使包封材料6提高强度和硬化。
作为下一个步骤,从连接层2上分离包括包封材料6、微结构化或纳米结构化的元器件4,4’和RCC箔3的复合体。作为单个的复合体部分在图5中示出了埋入包封材料6中的微结构化或纳米结构化的元器件4,4’和RCC箔3。在从连接层2上分离之后RCC箔的铜层处于可自由接近的状态。
在去除了载体1和连接层2之后,实施结构化和再分布(布线)。此时在图6中示出了在一个激光钻孔工序之后的构件。为此需要通过RCC箔3的环氧树脂层3a和铜层3b的激光钻孔工序。该激光钻孔工序产生通向微结构化或纳米结构化的元器件4,4’的接触部位5,5’的导通孔7,7’。
图7示出了在金属化之后导通孔7,7’的状态。在此情况下,在金属化时可以使先前产生的导通孔7,7’的表面与导体8接触。在此例如可以对铜层3b实施电镀加强。此外铜层3b可以配设焊阻(Loetstopp)9,其中该焊阻还可以附加地被结构化。在再分布之后可以通过锯切将构件分开成单个的,如通过虚线表示的。
在图8中示出了分别带有一个凹部10和10’的构件。在该构件的左半部中,可以看见凹部10通过包封材料6一直延伸到微结构化或纳米结构化的元器件4。在右半部中可以看见穿过RCC箔3的凹部10’以及还没有被去除的凸模11。如果例如从图3开始,在用包封材料6包封微结构化或纳米结构化的元器件4,4’期间,使微结构化或纳米结构化的元器件4,4’与凸模11至少部分地接触,那么通过去除凸模11可以获得在图8中所示的凹部(空腔)10。

Claims (10)

1.用于制造包含微结构化或纳米结构化的元器件(4,4’)的构件的方法,包括步骤:
-提供载体(1),包括施加在载体(1)上的连接层(2);
-在连接层(2)的表面上施加另一个层(3),其中该另一个层(3)包括导电的区域,该另一个层(3)包括至少两个上下设置的不同的层并且在一个层中存在的导电的区域面对着载体;
-在该另一个层(3)的表面上施加至少一个微结构化或纳米结构化的元器件(4,4’);
-用包封材料(6)至少部分地包封微结构化或纳米结构化的元器件(4,4’);
-从连接层(2)上分离所获得的、包括包封材料(6)、至少一个微结构化或纳米结构化的元器件(4,4’)和另一个层(3)的复合体。
2.按照权利要求1所述的方法,其中在所述另一个层(3)中,所述导电的区域包括一个铝层、铜层、银层、镍层、钯层、铬层、氮化钛层、可导电的聚合物和/或一个金层。
3.按照权利要求1所述的方法,其中所述另一个层(3)是覆铜的树脂箔。
4.按照权利要求1所述的方法,其中所述微结构化或纳米结构化的元器件(4,4’)从包括微机电系统、专用集成电路、半导体元器件和/或传感器元件的组中选取。
5.按照权利要求1所述的方法,进一步包括制造导通孔(7,7’)的步骤,该导通孔穿过所述另一个层通到所述微结构化或纳米结构化的元器件(4,4’)的被设置用于接触的区域(5,5’)。
6.按照权利要求1所述的方法,其中在用包封材料(6)包封所述微结构化或纳米结构化的元器件(4,4’)期间,一个凸模(11)至少部分地接触所述微结构化或纳米结构化的元器件(4,4’)。
7.按照权利要求1所述的方法,进一步包括将构件各个分开的步骤。
8.通过按照权利要求1所述的方法获得的构件,包括由包封材料(6)包围的微结构化或纳米结构化的元器件(4,4’),其中所述微结构化或纳米结构化的元器件(4,4’)至少部分地接触另一个层,其中该另一个层(3)包括至少一个导通孔(7,7’),该导通孔通到所述微结构化或纳米结构化的元器件(4,4’)的被设置用于接触的区域并且该导通孔(7,7’)与一个导电的层电气地接触。
9.按照权利要求8所述的构件,进一步包括一个凹部(10),它从外部穿过与所述微结构化或纳米结构化的元器件(4,4’)相邻接的材料并且一直延伸到所述微结构化或纳米结构化的元器件(4,4’)。
10.按照权利要求8所述的构件在压力传感器、加速度传感器、温度传感器、转速传感器、质量流量传感器、磁传感器、气体传感器、霍尔传感器和/或湿度传感器中的使用。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104807855A (zh) * 2014-01-29 2015-07-29 先技股份有限公司 微机电气体感测装置
CN106945639A (zh) * 2015-12-18 2017-07-14 罗伯特·博世有限公司 刮水片装置
CN109579928A (zh) * 2018-11-23 2019-04-05 北京控制工程研究所 一种热式微流量测量传感器流道及密封结构
CN110371920A (zh) * 2019-07-12 2019-10-25 北京机械设备研究所 抑制ndir气体传感器振动敏感性的方法及装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011108981B4 (de) * 2011-08-01 2016-02-18 Gottfried Wilhelm Leibniz Universität Hannover Struktureinrichtung mit einem Bauelement, Vorrichtung zur Applikation des Bauelements, Verfahren zur Herstellung der Struktureinrichtung und Verfahren zur Applikation des Bauelements
DE102011114774A1 (de) * 2011-09-30 2013-04-04 Infineon Technologies Ag Bauelement mit Gehäuse
DE102011084537B4 (de) * 2011-10-14 2017-05-04 Robert Bosch Gmbh Ultraschallsensorarray
AT514074B1 (de) * 2013-04-02 2014-10-15 Austria Tech & System Tech Verfahren zum Herstellen eines Leiterplattenelements
US9630837B1 (en) * 2016-01-15 2017-04-25 Taiwan Semiconductor Manufacturing Company Ltd. MEMS structure and manufacturing method thereof
DE102016217452A1 (de) 2016-09-13 2017-10-26 Hahn-Schickard-Gesellschaft für angewandte Forschung e.V. Verfahren zur Herstellung eines Schaltungsträgers und einer elektrischen Schaltung
TWI746974B (zh) * 2019-05-09 2021-11-21 國立清華大學 熱電奈米感測器及其製造方法與應用方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040065638A1 (en) * 2002-10-07 2004-04-08 Bishnu Gogoi Method of forming a sensor for detecting motion
US20060057761A1 (en) * 2003-04-25 2006-03-16 Fujitsu Limited Method for fabricating microstructure and microstructure
US7445959B2 (en) * 2006-08-25 2008-11-04 Infineon Technologies Ag Sensor module and method of manufacturing same
CN101308803A (zh) * 2007-05-16 2008-11-19 英飞凌科技股份有限公司 半导体器件

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW544882B (en) 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
JP3914239B2 (ja) 2005-03-15 2007-05-16 新光電気工業株式会社 配線基板および配線基板の製造方法
DE102007022959B4 (de) 2007-05-16 2012-04-19 Infineon Technologies Ag Verfahren zur Herstellung von Halbleitervorrichtungen

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040065638A1 (en) * 2002-10-07 2004-04-08 Bishnu Gogoi Method of forming a sensor for detecting motion
US20060057761A1 (en) * 2003-04-25 2006-03-16 Fujitsu Limited Method for fabricating microstructure and microstructure
US7445959B2 (en) * 2006-08-25 2008-11-04 Infineon Technologies Ag Sensor module and method of manufacturing same
CN101308803A (zh) * 2007-05-16 2008-11-19 英飞凌科技股份有限公司 半导体器件

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104807855A (zh) * 2014-01-29 2015-07-29 先技股份有限公司 微机电气体感测装置
CN106945639A (zh) * 2015-12-18 2017-07-14 罗伯特·博世有限公司 刮水片装置
CN109579928A (zh) * 2018-11-23 2019-04-05 北京控制工程研究所 一种热式微流量测量传感器流道及密封结构
CN110371920A (zh) * 2019-07-12 2019-10-25 北京机械设备研究所 抑制ndir气体传感器振动敏感性的方法及装置
CN110371920B (zh) * 2019-07-12 2023-09-08 北京机械设备研究所 抑制ndir气体传感器振动敏感性的方法及装置

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