TW201109269A - Method for manufacturing component comprising a micro-structuralized or nano-structuralized structural element - Google Patents

Method for manufacturing component comprising a micro-structuralized or nano-structuralized structural element Download PDF

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Publication number
TW201109269A
TW201109269A TW099129573A TW99129573A TW201109269A TW 201109269 A TW201109269 A TW 201109269A TW 099129573 A TW099129573 A TW 099129573A TW 99129573 A TW99129573 A TW 99129573A TW 201109269 A TW201109269 A TW 201109269A
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Taiwan
Prior art keywords
layer
nanostructured
structural element
sensor
micro
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TW099129573A
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Chinese (zh)
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TWI549898B (en
Inventor
Andreas Kugler
Ricardo Ehrenpfordt
Mathias Bruendel
Frieder Haag
Frieder Sundermeier
Ulrike Scholz
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Bosch Gmbh Robert
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Publication of TW201109269A publication Critical patent/TW201109269A/en
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Publication of TWI549898B publication Critical patent/TWI549898B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00349—Creating layers of material on a substrate
    • B81C1/00357—Creating layers of material on a substrate involving bonding one or several substrates on a non-temporary support, e.g. another substrate
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F1/00—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow
    • G01F1/68—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by using thermal effects
    • G01F1/684—Structural arrangements; Mounting of elements, e.g. in relation to fluid flow
    • G01F1/6845—Micromachined devices
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    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
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    • G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
    • G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
    • G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Abstract

A method for manufacturing a component comprising a micro-structuralized or nano-structuralized structural element comprises the following steps: providing a carrier (1), wherein the carrier (1) includes a connecting layer (2) applied on the carrier (1); applying another layer (3) on an upper side of the connecting layer (2), wherein said another layer (3) includes a conductive zone and said another layer (3) comprises at least two different levels which are set on upper and lower sides, the conductive zone on one of the levels facing the carrier; applying at least one micro-structuralized or nano-structuralized structural element (4)(4') on said another layer (3); a least partially packaging the micro-structuralized or nano-structuralized element (4)(4') with a packaging material (6); and peeling the composite so obtained, including the packaging material (6), the at least one micro-structuralized or nano-structuralized structural element, and said another layer (2), off the connecting layer (2).

Description

201109269 六、發明說明： 【發明所屬之技術領域】 本發明關於一種製造包含一微構造化（mikrostrukturiert， 英：microstructured)或奈米構造化（nanostrukturiert，英： nano-structured )的構造元件（Bauelement )的構件 (Bauteil ) »此方法包含提供一載體（它包含一施在此載 體上的連接層）的步驟。此外，此方法包含將另一個層 (Schicht，英：layer)施在該連接層的上側，其中該另— 層包含導電的範圍，其中該另一層包含至少二個上下設置 的不同層次（Lage，英：stratum )，其中該住在一個層次 中的導電範圍朝向該載體，此外本發明還關於依此方法所 得的一種構件及其應用。 【先前技術】 感測器一般封裝（Verpacken )在以冲壓格（stanzgitter) 或基材為基礎的「包封殼體」（模殼體）中。它們可為以 一種銅-塑膠殼體〔銅-導線架（Leadframe)〕為基礎的基 材的實施方式，該基材包含具端子腳的殼體（有導線殼體） 或不具端子腳的殼體（無導線殼體）。在此，個別的感測 器或ASIC (因應用而異的積體電路）相鄰地或上下重疊地 封裝到該基材料上，錢接著作—道射出成形程序。但也 有越來越多的新式無基材的殼材被開發。 晶片封裝的一種變更例稱為eWLB ( Embedded wafer Leve Ball-Grid-Aray ’埋設之晶圓位準球格陣列）。在此， 晶片以其活性側到一晶圓載體的一暫時性載體膜上，然後 4 201109269 用一廢機物料（Pressmasse )作包封。在此程序產生所謂的 「塑膠晶圓」〔重組晶圓（reconstituted wafer)〕，然後 將它從載體膜拿掉，俾能在該活性側上形成配線 (Umverdrahtung ) 〇 要形成配線，係使用標準薄層技術與材料。那些為了 作配線所製的貫穿接點（Durchkontakt)以及其相關的面隨 後設以銲料阻擋漆（L6tstopplack )，並利用鑛切將構造元 件從該塑膠晶圓切分（vereinze]n )出來。這種構想的缺點 為：在鑄造（模製）之後，該敏感易損的晶片表面係露空 者’因此須使用繁複的薄層技術’俾能作配線。這點在製 造包含這種微構造化或奈米構造化的構造元件的構件時， 而要除塵空内構造（Reinraum-Infrastruktur)。 舉例而言’在美專利US 2004/0169264提到一種積體電 路用的°又置（封裝）構造以及其製造方法。在此’該構造 凡件用一充填層包封，然後在另一步驟中將一有機層施 乍貝穿接點（Durchkontaktierung，英：through-contact ) 2該層，並將它與—配線層連接。但這種作法有缺點， 每是因為該構造元件的後側倚在基材上之故。因此其活性 (aktiv)面不受保護。 ^人們希望有一種較佳的方法來製造微構造化或奈米構 $化的構k 7L件，其中該構造元件在施加後呈受保護的狀 W且可利用—般的程序在進一步的過程中作接點接觸。 【發明内容】 因此本發明的目的在提供一種製造包含一微構造化或 201109269 奈米構造化的構造元件的構件 --提供-載體，該載體包人包3以下步驟： 層； 3個施在該載體上的連接 -將另-個層施在該連接層的上側 含導電的範圍，其中該另一層包含至少;= 同層次，且其中該位在一層 h置的不 时 的導電的範圍朝向該載體； --將至少一個微構造化 該另一層； 未構&化的構造元件施在 -將該微構造化或奈米構造化的構 料至少部分地包封； 千用^封物 •-將所得到的複合物—包含該包封物料，該至少一 微構造化或奈求構造化的構造元件以及該另 連接層撕離。 《 從该 本發月的方法的一優點為：既有的方法可簡化。 依此程序，在撕離程序步驟中使可該複合物分離，而不會 使该微構造化或奈米構造化的構造元件之要設配線的那一 側露空’其中在隨後的步驟中可將該構件切分。這點使得 除塵室技術能不必使用。因此之故，可在一除塵室外製造 此構件。同樣，處理格式（Verarbeitungsf〇rmat)可作自由造 形’因為其造形不—定非和在晶圓成形作業鄉在—起不 可而依先則技術這種晶圓成形作業只能在除塵室中作。 同樣地帛製方法可自由選擇，這是因為處理格式可配人 模製方法。 13 依本發明，微構造化或奈米構造化的構造元件的内部 構造尺寸特別是在從y奈米到微米的範圍》在此’ 201109269 内部構造尺寸」一詞指在構造元件内的構造（例如桁樑、 框條或導線路）的尺寸。 6玄微構造化或奈米構造化的構造元件可包含一範圍， 它用於與另一微構造化或奈米構造化的構造元件作導電式 接觸。這種範圍也稱「活性面」、端子墊片（Anschluj5pad) 或端子接點。這些微構造化或奈米構造化的構造元件還可 包含積體電路、感測器元件、被動構造元件、陶瓷電容器、 電阻或動作器，這些構造元件再造成一種系統，該系統在 切分後具有一獨立的設置（封裝）。 本發明的方法的第一步驟包括提供一載體，其中該載 體包含一個施在載體上的連接層，依本發明，舉例而言， 載體的材料可由以下之物選出：陶瓷、金屬或高熔點塑膠。 金屬可由不銹鋼i.4034及/或K4W0選出。載體可在此方 法中虽作批次技術（Batchtechologie )用的基礎使用。 利用連接層可將該微構造化或奈米構造化的構造元件 以較佳的設置方式固定在載體上。 該連接層宜均勻地施在載體上側，所用的連接層可在 高達200°C的溫度仍保持穩定而不會分解 也可包含一粘著膜，特別是該連接層可^ 或利用喷漆方式施覆。此外，該連接層^ 方法係將它印刷、噴墨、流霜. 。在此，該連接層201109269 VI. Description of the Invention: [Technical Field] The present invention relates to a structural element (Bauelement) which comprises a microstructural (microstructured) or nanostructured (nanostrukturiert, nano-structured) Bauteil » This method comprises the step of providing a carrier comprising a tie layer applied to the carrier. Furthermore, the method comprises applying another layer (Schicht, layer) to the upper side of the connection layer, wherein the other layer comprises a conductive range, wherein the other layer comprises at least two different levels (Lage, English: stratum), wherein the conductive range living in one level faces the carrier, and the present invention also relates to a member obtained by the method and its application. [Prior Art] The sensor is generally packaged (Verpacken) in an "encapsulated case" (mold case) based on a stamping grid or a substrate. They may be embodiments of a substrate based on a copper-plastic housing (Leadframe) comprising a housing with terminal legs (with wire housing) or a housing without terminal legs Body (wireless housing). Here, individual sensors or ASICs (integrated circuits that differ depending on the application) are packaged adjacent to each other or stacked on top of each other on the base material. However, more and more new baseless shell materials have been developed. A variation of the chip package is called eWLB (Embedded Wafer Grid-Aray). Here, the wafer is on its active side onto a temporary carrier film of a wafer carrier, and then 4 201109269 is encapsulated with a waste material (Pressmasse). In this process, a so-called "plastic wafer" (reconstituted wafer) is produced, and then it is removed from the carrier film, and a wiring can be formed on the active side (Umverdrahtung). Thin layer technology and materials. The through-contacts (Durchkontakt) made for wiring and their associated faces are then provided with a solder barrier paint (L6tstopplack), and the structural elements are cut from the plastic wafer by means of a metal cut. The disadvantage of this concept is that after casting (molding), the surface of the sensitive and fragile wafer is exposed to the air, so it is necessary to use complicated thin layer technology. This is done in the case of a component comprising such a microstructured or nanostructured structural element, but a deindustable interior structure (Reinraum-Infrastruktur). For example, U.S. Patent No. 2004/0169264, the entire disclosure of which is incorporated herein by reference in its entire entire entire entire entire entire entire entire entire entire entire disclosure Here, the structure is encapsulated with a filling layer, and then in another step, an organic layer is applied to the joint, and the wiring layer is bonded to the wiring layer (Durchkontaktierung, through-contact). connection. However, this practice has drawbacks, each because the back side of the structural element rests on the substrate. Therefore, its active (aktiv) surface is not protected. It is desirable to have a preferred method of fabricating a microstructuring or nanostructured structure, wherein the structural element is protected after application and can be processed in a further process. In the contact contact. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a component-providing carrier for the manufacture of a structural element comprising a micro-structured or 201109269 nanostructure, the carrier comprising the following steps: layer; 3 application Connection on the carrier - applying another layer to the upper side of the connection layer containing a conductive range, wherein the other layer comprises at least; = the same level, and wherein the position of the bit at a layer of h from time to time is directed toward the a carrier; - at least one micro-structured the other layer; an unconstructed &amplified structural element applied - at least partially encapsulates the micro-structured or nano-structured material; - the resulting composite - comprising the encapsulating material, the at least one microstructured or neatly constructed structural element and the further joining layer are torn away. An advantage of the method from this month is that the existing method can be simplified. According to this procedure, the composite can be separated during the tear-off procedure without leaving the side of the micro-structured or nano-structured structural element to be wired, which is in a subsequent step. The member can be cut. This makes the dust chamber technology unnecessary. Therefore, the member can be manufactured outside a dust collection room. Similarly, the processing format (Verarbeitungsf〇rmat) can be freely shaped 'because it is not shaped and not in the wafer forming operation, the wafer forming operation can only be done in the dust chamber. . The same method of tanning is freely selectable because the processing format can be fitted with a human molding method. 13 In accordance with the invention, the internal structural dimensions of the microstructured or nanostructured structural elements are particularly in the range from y nanometers to micrometers. The term "internal structural dimensions" herein refers to the construction within the structural elements ( For example, the dimensions of the truss, frame or guide. A metaphysical or nanostructured structural element may comprise a range for conducting conductive contact with another microstructuring or nanostructured structural element. This range is also called "active surface", terminal spacer (Anschluj5pad) or terminal contact. These micro-structured or nano-structured structural elements may also comprise integrated circuits, sensor elements, passive construction elements, ceramic capacitors, resistors or actuators, which in turn create a system that is after dicing Has a separate setup (package). The first step of the method of the invention comprises providing a carrier, wherein the carrier comprises a tie layer applied to the carrier, and according to the invention, for example, the material of the carrier can be selected from the group consisting of ceramic, metal or high melting point plastics. . The metal can be selected from stainless steel i.4034 and/or K4W0. The vector can be used as a basis for batch technology (Batchtechologie) in this method. The microstructured or nanostructured structural elements can be secured to the carrier in a preferred arrangement by means of a tie layer. The connecting layer should be uniformly applied to the upper side of the carrier, and the connecting layer used can be stable at a temperature of up to 200 ° C without decomposition or an adhesive film, in particular, the connecting layer can be applied by painting. cover. In addition, the connection layer method prints, inks, and sheds frost. Here, the connection layer

201109269 中該另-層包含導電的範圍，其中該另—層包括至少二個 上下設置的不同層次，且其中在一層， 層_人中的導電範圍朝向 該載體。為此，該連接層的至少一個部分範圍宜與該另一 層接層。在此，依本發明，此層可包含一個由至少2種不 同材料構造的層。纟另一變更例中可將一種材料埋設到另 -材料中。在此’ i少-種材料包含一導電材料，而另一 材料包含-絕緣材料，該另一層施在連接層上的上的方式 宜使該導電層與連接層接觸。這種設置的—優點為，在撕 離後一以後的程序步驟，該導電的範圍可作一道直接的 造化作業。 然後將至少一微構造化或奈米構造化的構造元件施在 該另一層的上側。在此，該微構造化或奈米構造化構造元 :與該另一層的上側接觸。此外特別是可使該微構造化或 奈米構造化的構造元件的活性面與該上側接觸。微構造化 或奈米構造化的構造元件的施加作業可利用一自動施加器 實施。此外，該微構造化或奈来構造化的構造元件的施加 作業可藉著將載體、構造元件及，或連接層加熱而變得更 容易。 此另一層可作交聯及/或硬化。舉例而言這點可利 用一道溫度步驟或用uv照射達成。 本發明另一步驟係將該微構造化或奈米構造化的構造 元件用—包封物料（Umhiillmasse )至少部分地包封。此包 十物料的其他名稱還有「铸件物料（Vergussmasse，英：cast maSS)」、「模複合成分（Moldcompound-Komponente)」、 缚 物料（Vergieflmasse，英：casting mass)」、「射 201109269 出「壓機物料（Spritzpressmasse)」、「射出成形物料」、 :模物料」及/或壓機物料（Pressmasse)。此外該包封物 料可有填充料。這些填充料用於配合材料性質包封物料 特別可將一種微構造化或奈米構造化的構造元件包封此 包封物料可藉加熱而交聯及硬化。舉例而言，包封物料可 由乂下之物選出：環氧樹脂、聚丙稀酸酯、聚氧甲又及/ 或矽力康。 所用的包封物料宜具有低潛變流（Kriechstrom，英： weep fl0w )性質、高均勻性、低折射指數、低收縮（以七⑺爪訂） 及/或低導熱係數《此外，所用的包封物料的熱膨脹係數 可和矽的熱膨脹係數的值有十倍的差，同樣，所用的包封 物料可特別具有高彈性模數及高玻璃過渡溫度。 在本發明的範疇中，「包封」一詞指射出成形、射出 壓製（Spmzpressen )、鑄造、層疊、以及使用英文的行話 moldmg (模製）、transferm〇lding(轉模製）、injecti〇n molding (射出成形）、potting〔罐成形（罐燒）〕、 molding (液體模製）、compression molding (壓模製）及 sheetmolden (片模製）。 在用包封物料包封之後，舉例而言，接著可將所得的 設置（Anordnung，英：arrangement)加熱，在此，「所得 的设置」一詞指由前面方法步驟得到之包封的構造元件， 此步驟也稱「後模固化」（Post-Mold-Cure, PMC)步驟， 對於模料所需的PMC步驟在本發明中使用，以使模料硬化 及終交聯。 本發明的方法的另一步驟係將所得的複合物--包含 201109269 包封物料，該至少一微構造&或奈米構造化的構造元件， 以及其他的層一一從連接層撕離◊「撕離」表示，該包 物料可連同該微構造化或奈米構造化的構造元件及的 層一齊從連接層撕離。為此，特別是用於將其他層從連接 層撕離所要施的力量，比將包封物料從其他層撕離所要施 的力量更小。 然後可作習知之用於作貫穿接點、以及將另一層構造 化、以及作配線的一般方法步驟。舉例而言，可利用雷射 在另一層中製造貫穿接點，為此可使用一種具有—組合的 雷射系統的雷射穿孔機。 接著，舉例而言，可利用一導電層將貫穿接點鍍上金 屬，為此’特別可用金屬導及/或導電聚合物當作導電層。· 為此’特別是在雷射鑽孔後，將鑽孔清理並鍍金屬。然後 可將表面用鈀活化，俾能用化學方式將銅（層厚度〇 5 — 〇 8 微米）鍍上去。最後的步驟，可將電解銅施上去，其中可 使用所謂的脈波電鍍（Puls-Plating )技術。 在本發明的方法的另一特點中，在該另一中該導電的 I巳圍包含一鋁層、銅層、銀層、鎳層、把層、鉻層、氮化 鈦層、導電的聚合物及/或一種金屬。這些材料除了有良 好導電性及可構造化性外，還有高導熱係數，它們可使在 操作時產生的熱順利導離。 在另一變更例中，該另一層可包含一種複合物，由鋼、 鎳或金構成，或包含由銅、鎳、鈀及/或金構成的複合物， 此複合物可部分地作預構造化，同樣地’舉例而言’該複 合物可在導電範圍上包含一光罩。此另一層宜可具特別的 10 201109269 放S°整‘ °己」以將該微構造化或奈米構造化的構造元件作 放置二在此’該調整標記可為貫穿者。在此，依本發明「貫 穿」-詞表示該標記貫穿過該另一層，因此在朝向載體的 那一側及相反側都是露空者。 „發明的方法的另一實施例中，該另一個層為鍍銅 :呀月曰膜舉例而言，此膜可為一個層疊在絕緣樹脂上的 5 匕也可稱 RCC 膜（Resin:c〇ated-Copper)，樹脂可 由：氧樹脂或聚丙烯酸酿選出。這種膜的優點& :它可呈 -材料方式用單一道方法步驟施覆。因此，可將程序簡 化，這是因為可在既有的方法中將膜一齊施在一基材上之 欠此處在使用RCC膜時還有一優點，即該微構造化或 微奈米化的構造元件的活性面可利用該RCC膜保護。 在本發明方法的另一實施例，該微構造化或奈米構造 化的構造元件由以下之物選出：冑電機械系統、依應用而 異（AnWendungsspezifisch，英：appIicati〇n spec出c)的積 體電路、半導體構造元件及/或感測器元件。 該感測器元件宜可為加速度感測器、轉速感測器、磁 感測器、《爾感測器、質量流感測器、氣體感測器、光學 感測器、濕度感測器、介質感測器及/或多晶片模組的構 件。 舉例而言，半導體構造元件可從以下之物選出：主動 像素感測器（Active Pixel Sensor)、電荷耦合裝置（CCD) 感測器、接觸影像感測器DIA (交流電二極體）、數位像素 感測器、電子乘法管（電子乘法）CCD、光閘流體、閘陣列 (Gate Array)、閘關掉（Gate_Turn_〇ff) (GT〇)閉流體、 201109269 半導體繼電器、半導體儲存器、積分級、微處理機、神經 圖（Neuromorpho )晶片、光耦合器、位置敏感裝置、太陽 電池、電池回耦的操作放大器、閘流體、閘流體調整器、 閘流體四極（Thyristortetrode )、閘流體塔（Thyristorturm )、 飛越時間（Time-of-flight)感測器、壓力感測器、加速度 感測器、濕度感測器、轉速感測器、質量流感測器、磁感 測器、氣體感測器、霍爾感測器、濕度感測器、渠溝（Trench ) 技術及/或視訊RAM (讀寫記憶體）。利用本發明的方法 有一優點’即：可很節省空間地將數個感測器相鄰設置， 其中由於在程序中已施覆該含有導電範圍的另一層，故該 構造元件的功能改善。 本發明方法的另一變更例包含一方法步驟：在至少二 個微構造化或奈米構造化的構造元件的場合製造一貫穿接 點’並將該二元件利用此鍍銅的樹脂膜互相接觸，其方法 係將該樹脂膜作配線。舉例而言，此微構造化或奈米構造 化的構造元件之朝向載體的那一側包含用於接觸的範圍， 例如一端子墊片（Anschluflpad )或端子接點，其中這些範 圍至少部分地和該鍍銅的樹脂膜接觸。 本發明的方法宜更包含製造一貫穿接點的步驟，該貫 穿接點穿過該另一個層到該微構造化或奈米構造化的構造 70件的一範圍，該範圍用於作接觸。 利用一道雷射鑽孔及鍍金屬層程序可製造該電接點。 此外，貫穿接點可用化學方式及/或物理方式製造。特別 疋貫穿接點可用化學蝕刻製造。此時Rcc膜可將相關的微 構造化或微奈米化的構造元件互相連接，這種連接部還可 12 201109269 利用電鍍補強。 該另一層可先用一種紫外線雷射光切開，然後該層可 利用c〇2雷射進一步除去直到該微構造化或奈米構造化的 構造元件為止。這種組合的系統的優點為：該微構造化或 奈米構造化的構造元件不會被C02雷射損壞。 在本發明的方法的另一實施例，在將該微構造化或奈 米構造化的構造元件用一包封物料包封時，一個壓模 (Stempel)與該微構造化或奈米構造化的構造元件至少部 分地接觸。在此，如果在用包封物料包封後，該包封物料 尚未硬化，則該壓模可與該微構造化或奈米構造化的構造 兀件接觸。為此’該壓模可壓入該包封物料進去。同樣地， 該壓模可與該微構造化或奈構造化的構造元件在用包封物 料包封前接觸，然後在其上作包封。因此可在包封物料硬 化後在-以後的程序步驟中㈣模再拿掉，如此可使介質 有通路能到達該微構造化或奈米構造化的構造 =二其一優點為：特別是可在配線以後才將壓模拿掉， 因此該微構造化或奈米# 、 的方法步驟損害。 中的構造7°件不會受到先前 此外本發明的一栌 包含一個被…為一種由上述方法得到的構件， 、A _杜 ^封物料包圍的微構造化或奈米構造化的椹 二件，其中該微構造化或奈米構造 的： :層至少部分地接觸。其中該另一層包含至一另 以與该微構造化或 貫穿接點 盆中構造化的構造元件的範圍接觸，且 ”甲。亥貝穿接點與一導 吗丧觸且 造化或奈米構造化構！ Γ導電式接觸。特別是該微構 几件可由以下之物選出：MEMS、 13 201109269 ASIC。此構件宜具有一鍍銅的樹脂膜，它在進一步的步驟 中可作構造化。此構件（它具有此膜當作配線的基礎）的 優點為：它特別具有感測器的小型化的封裝。 在一實施例中，依本發明的構件更包含一空腔，該空 腔從外側穿過一種材料（該材料鄰界到該微構造化或奈米 構造化的構造元件），i-直貫穿到該微構造化或奈米構 造化的構造元件為止。如果不用此方 < (或者除了用此方 式外同時另外）也可使該空腔貫穿過該包含導電範圍的膜 過去。如此，舉例而言，可使介質有通路，英：< 可到達包裝過的構造元件（如感測器）。在此該感測器可 為：壓力感測器、流體感測器及/或化學感測器。如此可 有利地使中間空間與外介質相通，其中特別是㈣一種流 體相通而達成此點。 本發明另一標的為一種 壓力感測器、加速度感測器 質量流感測器、磁感測器、 或濕度感測器。在此，「感 包含一分析電子電路《舉例 生產更廉價的分析系統，因 既有的方法中，同樣地可達 功能的數個構造元件而製造 程序產生這些構造元件。 上述的構件的應用，其係用在 、溫度感測器 '轉速感測器、 氣體感測器、霍爾感測器及/ 測器」表示製成的系統，它們 而言’利用本發明的方法，可 為本發明的方法可一齊帶入一 到一種優點：可使用具有不同 多功能感測器，且可利用批次 本發明兹配合以下圖式進一步說明 【實施方式】 14 201109269 圖1顯示—提供的載體⑴’它具有位於載體⑴上的連 接層（2)。在此，連接層（2)平平地倚在載體⑴上。載體⑴ 的材料宜為不錄鋼，在此處的情形特別是不⑽I·。 在此處的情形’連接層(2)特別包含以聚合物為基礎的材料。 圖2顯示將另-層（3)施加到連接層⑺上以後的狀態。 在此處的情形’該另一層須為一 Rcc膜(3)。在此，咖膜 (3)包含-環氧樹脂層（3a)及一銅層如放大圖所示，在咖 膜⑺中所含的環氧樹脂層（33)倚在銅層（3b)上且在此情形 中形成用於施構造元件的那一側。 圖3中，將微構造化或奈米構造化的構造元件（4)及（4，） 施加，在此财，該微構造化或奈米構造化的構造元件⑷ 可為MEMS’而該微構造化或奈米構造化的構造元件（4，）可 為ASIC。在此，構件（4)與（4’）的形狀與功能可以不同。該 微構迨化或奈米構造化的構造元件（4)(4，）進入Rcc膜〇)的The further layer in 201109269 comprises a range of electrical conductivities, wherein the further layer comprises at least two different levels arranged one above the other, and wherein the conductive range in one layer, the layer_person, faces the carrier. To this end, at least one portion of the tie layer is preferably in contact with the other layer. Here, according to the invention, this layer may comprise a layer constructed of at least two different materials. In another variation, one material may be embedded in another material. Here, the material comprises a conductive material, and the other material comprises an insulating material, and the other layer is applied on the connecting layer in such a manner that the conductive layer is in contact with the connecting layer. The advantage of this arrangement is that the range of electrical conduction can be used as a direct manufacturing operation after a subsequent step of tearing. At least one micro-structured or nano-structured construction element is then applied to the upper side of the other layer. Here, the microstructural or nanostructured structural element is in contact with the upper side of the other layer. Furthermore, in particular, the active surface of the microstructured or nanostructured structural element can be brought into contact with the upper side. The application of the microstructural or nanostructured structural elements can be carried out using an automatic applicator. Furthermore, the application of the microstructured or nanostructured structural elements can be made easier by heating the carrier, the structural elements and, or the tie layer. This other layer can be crosslinked and/or hardened. This can be achieved, for example, by a temperature step or by uv irradiation. A further step of the invention is to at least partially enclose the microstructured or nanostructured structural element with an encapsulating material (Umhiillmasse). Other names for this package include "casting materials (Vergussmasse, English: cast maSS), "Moldcompound-Komponente", "Vergieflmasse (English: casting mass)", "shooting 201109269" Press material (Spritzpressmasse), "Injection forming material", : Mold material" and / or press material (Pressmasse). In addition, the encapsulating material may have a filler. These fillers are used in conjunction with the nature of the material to encapsulate the material. In particular, a microstructural or nanostructured structural element can be encapsulated. The encapsulating material can be crosslinked and hardened by heating. For example, the encapsulating material can be selected from the underarms: epoxy, polyacrylate, polyoxymethylene and/or piricon. The encapsulating material used should have a low latent flow (Kriechstrom, English: weep fl0w) properties, high uniformity, low refractive index, low shrinkage (with seven (7) claws) and / or low thermal conductivity "In addition, the package used The thermal expansion coefficient of the sealing material can be ten times different from the value of the thermal expansion coefficient of the crucible. Similarly, the encapsulating material used can have a particularly high modulus of elasticity and a high glass transition temperature. In the context of the present invention, the term "encapsulation" refers to injection molding, injection compression (Spmzpressen), casting, lamination, and use of English jargon mold (molding), transferm〇lding (transformation), injecti〇 n molding (injection molding), potting (can forming), molding (liquid molding), compression molding (molding), and sheetmolden (sheet molding). After encapsulation with the encapsulating material, for example, the resulting arrangement (Anordnung, English) can then be heated, where the term "obtained setting" refers to the encapsulating structural element obtained from the previous method steps. This step is also referred to as the "Post-Mold-Cure" (PMC) step, and the PMC step required for the mold is used in the present invention to harden and finally crosslink the mold. Another step of the method of the present invention is to obtain the resulting composite comprising the 201109269 encapsulating material, the at least one microstructured & or nanostructured structural element, and other layers being peeled off from the tie layer one by one. "Tear away" means that the package material can be peeled off from the tie layer together with the microstructured or nanostructured structural elements and layers. For this reason, in particular, the force to be applied to tear the other layers away from the joining layer is less than the force required to tear the enveloping material away from the other layers. Conventional method steps for making through-contacts, constructing another layer, and wiring can then be used. For example, a laser can be used to make a through-contact in another layer, for which a laser perforator with a combined laser system can be used. Next, for example, a conductive layer may be used to plate the through contacts with a metal, for which a particularly useful metal conductive and/or conductive polymer is used as the conductive layer. · For this purpose, especially after laser drilling, the holes are cleaned and metallized. The surface can then be activated with palladium, which can be chemically plated with copper (layer thickness 〇 5 - 〇 8 microns). In the final step, electrolytic copper can be applied, in which a so-called Pulse-Plating technique can be used. In another feature of the method of the present invention, in the other of the conductive layers, the conductive layer comprises an aluminum layer, a copper layer, a silver layer, a nickel layer, a handle layer, a chromium layer, a titanium nitride layer, and a conductive polymerization. And / or a metal. In addition to good electrical conductivity and structurability, these materials also have high thermal conductivity, which allows the heat generated during operation to be smoothly conducted away. In another variation, the other layer may comprise a composite consisting of steel, nickel or gold, or a composite of copper, nickel, palladium and/or gold, which may be partially pre-structured The same, 'for example' the composite may comprise a reticle over the conductive range. This additional layer may have a special 10 201109269 S° integral to allow the microstructuring or nanostructured structural elements to be placed here. The adjustment mark may be a through. Here, the term "through" in the present invention means that the mark passes through the other layer, and therefore is exposed on the side facing the carrier and on the opposite side. In another embodiment of the method of the invention, the other layer is copper plated: the ruthenium film, for example, the film may be a 5 匕 or RCC film laminated on an insulating resin (Resin:c〇 ated-Copper), the resin can be selected from: oxy resin or polyacrylic acid. The advantages of this film &: it can be applied in a single-method step in a material-wise manner. Therefore, the procedure can be simplified because it can be In the prior art, it is also advantageous to apply the film to a substrate. The use of the RCC film also has the advantage that the active surface of the microstructured or micro-nanostructured structural element can be protected by the RCC film. In a further embodiment of the method according to the invention, the microstructuring or nanostructured structural element is selected from the following: an electromechanical system, depending on the application (AnWendungsspezifisch, English: appIicati〇n spec c) The integrated circuit, the semiconductor structural component and/or the sensor component. The sensor component may be an acceleration sensor, a rotational speed sensor, a magnetic sensor, a sensor, a mass detector, a gas. Sensor, optical sensor, humidity sensing The components of the dielectric sensor and/or the multi-chip module. For example, the semiconductor construction component can be selected from the following: an active pixel sensor (Active Pixel Sensor), a charge coupled device (CCD) sensor, Contact image sensor DIA (AC diode), digital pixel sensor, electronic multiplication tube (electronic multiplication) CCD, shutter fluid, gate array (Gate Array), gate off (Gate_Turn_〇ff) (GT 〇) Closed fluid, 201109269 Semiconductor relays, semiconductor storage, integration stages, microprocessors, Neuromorpho wafers, optocouplers, position sensitive devices, solar cells, battery-coupled operational amplifiers, thyristors, thyristors Regulator, thyristor quadrupole, Thyristorturm, Time-of-flight sensor, pressure sensor, acceleration sensor, humidity sensor, speed sensor, Quality flu detector, magnetic sensor, gas sensor, Hall sensor, humidity sensor, Trench technology and/or video RAM (read and write memory). The method has the advantage that a plurality of sensors can be arranged adjacently in a space-saving manner, wherein the function of the structural element is improved since the other layer containing the conductive range has been applied in the program. A further variant comprises a method step of producing a through-contact in the case of at least two microstructured or nanostructured structural elements and contacting the two elements with the copper-plated resin film. The resin film is used as a wiring. For example, the side of the microstructured or nanostructured structural element facing the carrier includes a range for contact, such as a terminal spacer (Anschluflpad) or a terminal contact. Wherein these ranges are at least partially in contact with the copper plated resin film. The method of the present invention preferably further comprises the step of making a through-contact through the other layer to a range of the microstructured or nanostructured structure 70 for contact. The electrical contacts can be fabricated using a laser drilling and metallization procedure. Furthermore, the through joints can be made chemically and/or physically. In particular, the through-contact can be made by chemical etching. At this time, the Rcc film can interconnect the related micro-structured or micro-nanostructured structural elements, and the joint can also be reinforced by electroplating. The other layer can be first cut with an ultraviolet laser light which can then be further removed by a c〇2 laser until the microstructured or nanostructured structural element. The advantage of this combined system is that the microstructuring or nanostructured construction elements are not damaged by the C02 laser. In a further embodiment of the method of the invention, a stamper (Stempel) and the micro-structured or nano-structured when the micro-structured or nano-structured structural element is encapsulated with an encapsulating material The structural elements are at least partially in contact. Here, if the encapsulating material has not been hardened after encapsulation with the encapsulating material, the stamp can be in contact with the micro-structured or nano-structured structural element. To this end, the stamper can be pressed into the encapsulating material. Likewise, the stamper can be contacted with the microstructuring or na[iota] structured structural element prior to encapsulation with the encapsulating material and then encapsulated thereon. Therefore, after the encapsulating material is hardened, the mold can be removed again in the subsequent step (four), so that the medium can have access to the micro-structured or nano-structured structure = two advantages are: The stamper is removed after wiring, so the method steps of the micro-structuring or nano-, damage. The structural 7° member in the prior art is not subject to the prior art invention comprising a member which is obtained by the above method, and a micro-structured or nano-structured member surrounded by the A_DU material. Where the microstructural or nanostructured:: the layer is at least partially in contact. Wherein the other layer is in contact with a range of structural elements that are structured in the micro-structured or penetrating basin, and "A. Haibei crossings are in contact with a conductive or nanostructure化 Γ Γ conductive contact. In particular, the microstructure can be selected from the following: MEMS, 13 201109269 ASIC. This component should have a copper-plated resin film, which can be constructed in a further step. The advantage of the component, which has the film as the basis for the wiring, is that it has, in particular, a miniaturized package of the sensor. In one embodiment, the component according to the invention further comprises a cavity which is worn from the outside. Passing a material (the material is adjacent to the microstructured or nanostructured structural element), i- straight through the microstructured or nanostructured structural element. If this is not used (or In addition to this, in addition to this, it is also possible to pass the cavity through the film containing the conductive range. Thus, for example, the medium can be made to have a passage, and: can reach the packaged structural element (such as Detector). The sensor can be: a pressure sensor, a fluid sensor, and/or a chemical sensor. This advantageously allows the intermediate space to communicate with the external medium, wherein in particular (iv) a fluid communication to achieve this. Another indication of the invention is a pressure sensor, an accelerometer mass influx detector, a magnetic sensor, or a humidity sensor. Here, "the sensing includes an analytical electronic circuit", for example, to produce a cheaper analytical system, These structural elements are produced by the manufacturing process due to several structural elements that are equally functional in the existing method. The application of the above-mentioned components is used in, temperature sensor 'speed sensor, gas sensor "Hall sensor and / /" means a system made, which means that by using the method of the present invention, the method of the present invention can be brought together to one advantage: a different multifunctional sensing can be used. The present invention is further illustrated with the following figures. [Embodiment] 14 201109269 Figure 1 shows a carrier (1) provided with a tie layer (2) on a carrier (1). Here, the connecting layer (2) rests flat on the carrier (1). The material of the carrier (1) is preferably not recorded, and in this case, in particular, it is not (10) I·. In the case here, the connecting layer (2) specifically comprises a polymer-based material. Fig. 2 shows a state after the other layer (3) is applied to the connection layer (7). In the case here, the other layer must be an Rcc film (3). Here, the coffee film (3) comprises an epoxy resin layer (3a) and a copper layer as shown in an enlarged view, and the epoxy resin layer (33) contained in the coffee film (7) is placed on the copper layer (3b). And in this case the side for applying the construction element is formed. In Fig. 3, structural elements (4) and (4,) which are microstructured or nanostructured are applied, and in this case, the microstructural or nanostructured structural element (4) may be MEMS' and the micro The structural or nanostructured structural element (4,) can be an ASIC. Here, the shapes and functions of the members (4) and (4') may be different. The microstructured deuterated or nanostructured structural element (4) (4,) enters the Rcc film

深度，使得其接點位置（5)(5，）完全被RCC膜（3)蓋住。在RCC 膜（3)的環氧樹脂層（3a)上施加該微構造化或奈米構造化的 構造元件（4)(4’）。構造元件（4)(4’）具有朝向載體（1)的接點位 置（5)及（5 )。匕們位在環氧樹脂層（3a)内。然後，使環氧樹 脂層（3a)交聯。 在隨後步驟中，鑄造圖3中所示的設置。圖4顯示， 該包封物料（6)如何與該微構造化或奈米構造化的構造元件 接觸，然後可加熱到一溫度，在此溫度該包封物料（6)固化 及硬化。 下一步驟係將該複合物〔它包含包封物料、微構造 化或奈米構造化構造元件（4)(4，）、和RCC膜〕從連接層（2) 15 201109269 撕離。在圖5中，顯示該埋人包封物料⑹中的微構造化或 奈米構造化的構造元件（4)(4，）和該RCC膜（3)呈單一之複合 件形式，從連接層（2)撕離後，R C C膜的銅層可自由地探及。 在載體（1)和連接層（2)拿掉後，作構造化和配線的作 業。在此在圖6中顯示雷射鑽孔過程後的構件。為此需作 一道雷射鑽孔過程穿過RCC膜（3)的環氧樹脂層㈣和rcc 膜（3)的銅層（3b)，此雷射鑽孔過程產生一貫穿接點（7)(7，） 通到微構造化或微㈣構造化的構造元件⑷(4’）的接點位 置。 ” 圖7顯示鍍金屬後，貫穿接點（7)(7，）的表面與一導線 接觸。舉例而言，在此將銅層（3b)作電鑛補強。此外，銅層 (叫可設有-銲料阻擋件（9)，其中該銲料阻擋件還可另外作 構造化。作過配線後，可藉切鋸將構件切分，這點係用虛 線表示。 圖8顯示具有各一空腔（10)及（1〇，）的單獨構件，在構件 :土半部可看到一空腔(10)穿過包封物料⑹—直到該微構 &化或奈米構造化的構件（4)(4，）為止，在其右邊可 腔 UO，）穿過 RCC 膜（3)。 【圖式簡單說明】 圖1係一提供的載體； 圖2係在施加RCC膜後的步驟的示圖. 圖3係§亥微構造化或奈米構造化的播冰_ u _ 冉16兀件的施加步 示圖； 圖4係在施加包封物料後的步驟的示圖. 201109269 圖5係在撕離後的步驟的示圖； 圖6係在製造貫穿接點後的步驟的示圖； 圖7係在貫穿接點鍍金屬後的步驟的示圖； 圖8係具有二個空腔的構造的構件的示圖。 【主要元件符號說明】 (1) 載體 (2) 連接層 (3) 另一層（RCC膜） (3a) 環氧樹脂層 (3b) 銅層 (4)(4，） 構造元件 (5)(55) 接點位置 (6) 包封物料 (7)(75) 貫穿接點 (8) 導線 (9) 銲料阻擋件 (10)(105) 空腔 17The depth is such that its contact position (5) (5,) is completely covered by the RCC film (3). The microstructured or nanostructured structural element (4) (4') is applied to the epoxy layer (3a) of the RCC film (3). The structural element (4) (4') has contact locations (5) and (5) towards the carrier (1). They are located in the epoxy layer (3a). Then, the epoxy resin layer (3a) is crosslinked. In the subsequent steps, the settings shown in Fig. 3 are cast. Figure 4 shows how the encapsulating material (6) is in contact with the microstructuring or nanostructured structural element and can then be heated to a temperature at which the encapsulating material (6) solidifies and hardens. The next step is to tear the composite [which contains the encapsulating material, the microstructured or nanostructured construction element (4) (4,), and the RCC film] from the tie layer (2) 15 201109269. In Fig. 5, the microstructuring or nanostructured structural element (4) (4,) and the RCC film (3) in the buried encapsulating material (6) are shown in the form of a single composite, from the connecting layer. (2) After peeling off, the copper layer of the RCC film can be freely probed. After the carrier (1) and the connection layer (2) are removed, the construction and wiring work is performed. The components after the laser drilling process are shown here in FIG. To do this, a laser drilling process is required to pass through the epoxy layer (4) of the RCC film (3) and the copper layer (3b) of the rcc film (3). This laser drilling process produces a through joint (7). (7,) The position of the joint to the structural element (4) (4') of the microstructural or micro (4) structure. Figure 7 shows the surface of the through joint (7) (7,) being in contact with a wire after metallization. For example, the copper layer (3b) is used for electric ore reinforcement. In addition, the copper layer can be set. There is a solder stopper (9), wherein the solder stopper can be additionally structured. After the wiring is made, the member can be divided by a sawing saw, which is indicated by a broken line. 10) and (1〇,) separate components, in the component: soil half can see a cavity (10) through the encapsulating material (6) - until the micro- & or nano-structured component (4) (4,), on the right side of the cavity UO,) through the RCC film (3). [Simplified schematic] Figure 1 is a carrier provided; Figure 2 is a diagram of the steps after the application of the RCC film. Figure 3 is a diagram showing the application of the ice-forming _ u _ 冉 16 element of the § hai micro-structured or nano-structured; Figure 4 is a diagram showing the steps after applying the encapsulating material. 201109269 Figure 5 is tearing Figure 6 is a view showing the steps after the through-contact is made; Figure 7 is a view showing the steps after metallization through the contacts; Figure 8 has two steps; Diagram of the components of the cavity structure. [Description of main component symbols] (1) Carrier (2) Connection layer (3) Another layer (RCC film) (3a) Epoxy layer (3b) Copper layer (4) (4 ,) Construction Element (5) (55) Contact Position (6) Encapsulation Material (7) (75) Through Contact (8) Wire (9) Solder Barrier (10) (105) Cavity 17

Claims (1)

201109269 七、申請專利範圍：201109269 VII. Patent application scope: 1.—種掣、α "· * (4)(4’）的構佴 _·提供 上的連接層（2);1.—The structure of the species, α "· * (4) (4') _· provides the connection layer (2); 其中該位在一層次的導電的範園朝甸 __將另 層（3)包含導電的範圍 設置的不同層次，且 該載體； 一個微構造化或奈米構造化的構造元件 ⑷(4’）施在該另一層（3); -將该微構造化或奈米構造化的構造元件（4)(4，）用/ 包封物料（6)至少部分地包封； 一 一將所得到的複合物一一包含該包封物料（6)，該炱少 微構這化或奈米構造化的構造元件以及該另一層（3)一一 從該連接層（2)撕離。 2·如申請專利範圍第1項之方法，其中： 在該另一層（3)中該導電的範圍包含一鋁層、銅層、銀 層鎳層 '鈀層、鉻層、氮化鈦層、導電的聚合物及/或 —金屬。 3. 如申請專利範圍第1項之方法，其中： 該另一個層（3)為鍍銅的樹脂膜。 4. 如申請專利範圍第1項之方法，其中： 物選出： 5亥微構造化或奈米構造化的構造元件（4)(4，）由以下之 微電機械系統、依應用而異的積體電路、半導體 201109269 構造元件及/或感測器元件。 5. 如申請專利範圍第丨項之方法，其中： 更包含製造-貫穿接點⑺(7，)的步驟，穿過該另—個層 到該微構造化或奈米構造化的構造元件（4)(4，）的— (5)(5，），該範圍用於作接觸。 6. 如申請專利範圍第1項之方法，其中： 在該將該微構造化或奈米構造化的構造元件⑷⑷）用 -包封物料（6)包封時，—個壓模與該微構造化或奈米心 化的構造元件（4)(4，）至少部分地接觸。 & 7 ·如申請專利範圍第1項之方法，其中： 更包含將該構造元件切分的步驟。 8’種由申請專利範圍第i項的方法得到的構件，包含 一個被一包封物料（6)包圍的微構造化或奈米構造化的構2 元件’其中該微構造化或奈米構造化的構造元= (4)(4’)與一另一層至少部分地接觸，其中該另一層⑷⑹ 包含至少-貫穿接點⑺(7’)，以與該微構造化或奈米構造化 的構造元件⑷(4，）的範圍接觸，1其中該貫穿接點⑺(7，） 與一導電層作導電式接觸。 9.如申請專利範圍第8項之構件，其中： 更包含一空腔（10)，該空腔（10)從外側穿過—種材料〔該 材料鄰界到該微構造化或奈米構造化的構造元件（4)(4，）〕， 且一直貫穿到該微構造化或奈米構造化的構造元件（4)(4，) 為止。 10.一種如申請專利範圍第8項的構件的應用，其係用 在壓力感測器、加速度感測器、溫度感測器、轉速感測器、 201109269 質量流感測器、磁感測器、氣體感測器、霍爾感測器及 或濕度感測器。 八、圖式： (如次頁） 20Where the bit is in a layer of conductive Fanyuan Chaodian __ the other layer (3) contains different levels of the conductive range set, and the carrier; a micro-structured or nano-structured structural element (4) (4' Applying the other layer (3); - at least partially encapsulating the microstructured or nanostructured structural element (4) (4) with / encapsulating material (6); The composite comprises one of the encapsulating material (6), the structural element which is reduced in microfabrication or nanostructured and the further layer (3) being peeled off from the connecting layer (2). 2. The method of claim 1, wherein: in the another layer (3), the conductive range comprises an aluminum layer, a copper layer, a silver layer nickel layer, a palladium layer, a chromium layer, a titanium nitride layer, Conductive polymer and / or - metal. 3. The method of claim 1, wherein: the other layer (3) is a copper plated resin film. 4. For the method of claim 1 of the patent scope, wherein: the material is selected: 5 Hai micro-structured or nano-structured structural elements (4) (4,) are different from the following micro-electromechanical systems, depending on the application. Integrated circuit, semiconductor 201109269 construction component and / or sensor component. 5. The method of claim 2, wherein: further comprising the step of manufacturing-through joint (7) (7,), passing the other layer to the microstructured or nanostructured structural element ( 4) (4,) - (5) (5,), this range is used for contact. 6. The method of claim 1, wherein: when the microstructuring or nanostructured structural element (4) (4) is encapsulated with an encapsulating material (6), a stamper and the micro The structural or nano-centered structural elements (4) (4,) are at least partially in contact. & 7 The method of claim 1, wherein: the step of dividing the structural element is further included. 8's member obtained by the method of claim i, comprising a microstructural or nanostructured 2 element surrounded by an encapsulating material (6) wherein the microstructuring or nanostructure Constructive element = (4) (4') at least partially in contact with a further layer, wherein the other layer (4) (6) comprises at least - a through joint (7) (7') to be structured with the microstructured or nanostructured The range of construction elements (4) (4,) is in contact, 1 wherein the through contacts (7) (7,) are in conductive contact with a conductive layer. 9. The component of claim 8 wherein: further comprising a cavity (10) passing through the material from the outside (the material boundary to the microstructure or nanostructure) The structural elements (4)(4,)] are passed through the microstructured or nanostructured structural elements (4)(4,). 10. An application of a component according to claim 8 for use in a pressure sensor, an acceleration sensor, a temperature sensor, a rotational speed sensor, a 201109269 mass influenza detector, a magnetic sensor, Gas sensor, Hall sensor and or humidity sensor. Eight, the pattern: (such as the next page) 20
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DE102011114774A1 (en) * 2011-09-30 2013-04-04 Infineon Technologies Ag Sensor component e.g. gas sensor component integrated in e.g. ball grid array package, has conductive layer that is made to contact with sensor chip by electrical contacts of conductive layer
DE102011084537B4 (en) * 2011-10-14 2017-05-04 Robert Bosch Gmbh Ultrasonic sensor array
AT514074B1 (en) 2013-04-02 2014-10-15 Austria Tech & System Tech Method for producing a printed circuit board element
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US9630837B1 (en) * 2016-01-15 2017-04-25 Taiwan Semiconductor Manufacturing Company Ltd. MEMS structure and manufacturing method thereof
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