TWI767992B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a first semiconductor die, a first encapsulant surrounding the first semiconductor die, and a first redistribution structure formed on the first semiconductor die and the first encapsulant. The semiconductor device further includes a second semiconductor die, a second encapsulant surrounding the second semiconductor die, and a second redistribution structure formed on the second semiconductor die and the second encapsulant. The semiconductor device also include a conductive via electrically connecting the first redistribution structure to the second redistribution structure.

Description

Semiconductor device and method of manufacturing the same

Various aspects of the present disclosure relate to semiconductor devices and methods of manufacturing the same.

Semiconductor packaging protects integrated circuits or chips from physical damage and external stress. In addition, the semiconductor package may provide thermally conductive paths to efficiently remove heat generated in the wafer, and also provide electrical connections to other components (such as printed circuit boards), for example. Materials used for semiconductor packaging typically include ceramics or plastics, and form factors have evolved from ceramic flat mount and dual in-line packages to pin grid arrays and pinless wafer carrier packages, among others.

Other limitations and disadvantages of known and conventional approaches will become apparent to those skilled in the art by comparing such a system with some aspects of the present disclosure as set forth in the remainder of this application with reference to the accompanying drawings .

Aspects of the present invention provide a semiconductor device including: a first semiconductor die, a first surface thereof, a second surface opposite to the first surface of the first semiconductor die, and a first surface formed on the first semiconductor die a first bond pad of the first surface of a semiconductor die; a first encapsulant surrounding the first semiconductor die and including a first bond adjacent to the first surface of the first semiconductor die a surface; a first redistribution structure formed on the first surface of the first semiconductor die and the first surface of the first encapsulation; a second semiconductor die including a first surface, a second surface relative to the first surface of the second semiconductor die, and a second surface formed on the second semiconductor die a second bond pad of the first surface of the two redistribution structures formed on the first surface of the second semiconductor die and the first surface of the second encapsulation; and conductive vias extending through the first The encapsulation and the second encapsulation electrically connect the first redistribution structure to the second redistribution structure.

Another aspect of the present invention provides a semiconductor device including: a first semiconductor die including bond pads; a first encapsulant surrounding the first semiconductor die and exposing the first semiconductor die the bond pads; a first redistribution structure formed on the first semiconductor die and the first encapsulation and electrically connected to the bond pads of the first semiconductor die; a second semiconductor die including bond pads; a second encapsulation surrounding the second semiconductor die and exposing the bond pads of the second semiconductor die; a second redistribution structure formed in the bond pads on the second semiconductor die and the second encapsulation and electrically connected to the second semiconductor die; and conductive vias electrically connecting the first redistribution structure is sexually connected to the second redistribution structure.

Yet another aspect of the present invention provides a semiconductor device including: a first semiconductor die; a first encapsulation surrounding the first semiconductor die; and a first redistribution structure formed on the first semiconductor die a semiconductor die and on the first encapsulation; a second semiconductor die; a second encapsulation surrounding the second semiconductor die; a second redistribution structure formed on the second semiconductor on the die and the second encapsulation; and a conductive via electrically connecting the first redistribution structure to the second redistribution structure.

100‧‧‧Semiconductor device

110‧‧‧First semiconductor die

111‧‧‧First surface

112‧‧‧Second surface

113‧‧‧Third surface

114‧‧‧Bond pads

120‧‧‧First Encapsulation

120A‧‧‧First Encapsulation

121‧‧‧First surface

122‧‧‧Second surface

123‧‧‧Third surface

130‧‧‧First Redistribution Structure

131‧‧‧Metal layer

132‧‧‧Dielectric layer

133‧‧‧Conduction through hole

134‧‧‧Opening

140‧‧‧Second semiconductor die

141‧‧‧First surface

142‧‧‧Second surface

143‧‧‧Third surface

144‧‧‧Bond pads

150‧‧‧Second Encapsulation

150A‧‧‧Second Encapsulation

151‧‧‧First surface

152‧‧‧Second surface

153‧‧‧Third surface

160‧‧‧Second Redistribution Structure

161‧‧‧Metal layer

162‧‧‧Dielectric layer

170‧‧‧Conductive Vias

180‧‧‧Adhesive layer

190‧‧‧External Interconnect Structure

199‧‧‧Sawing Tools

210‧‧‧First Carrier

211‧‧‧First Temporary Adhesive Layer

220‧‧‧Second carrier

221‧‧‧Second temporary adhesive layer

300‧‧‧Semiconductor devices

380‧‧‧Adhesive layer

400‧‧‧Semiconductor Devices

410‧‧‧Encapsulation

The accompanying drawings and detailed description use the same reference numerals to refer to the same and/or similar elements.

FIG. 1 is a cross-sectional view illustrating a semiconductor device according to example embodiments of the present disclosure.

FIG. 2 is a flowchart of a method of fabricating the semiconductor device according to the example embodiment of FIG. 1 .

3A to 3J are cross-sectional views illustrating a method of fabricating the semiconductor device according to the example embodiment of FIG. 1 .

4 is a cross-sectional view of a semiconductor device according to another example embodiment of the present disclosure.

5A to 5C are cross-sectional views illustrating a method of fabricating the semiconductor device according to the example embodiment of FIG. 4 .

6 is a cross-sectional view of a semiconductor device according to yet another example embodiment of the present disclosure.

FIG. 7 is a cross-sectional view illustrating a method of manufacturing the semiconductor device of FIG. 6 .

The various aspects of the present disclosure may be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments of the present disclosure are provided so that this disclosure will be thorough and complete, and will convey various aspects of the disclosure to those skilled in the art.

In the drawings, the thickness of laminations and regions are exaggerated for clarity. Here, the same reference numerals refer to the same elements herein. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when element A is referred to as being "connected to" element B, element A can be directly connected to element B or intervening elements C may be present and element A and element B are indirectly connected to each other.

The terminology used herein is for the purpose of describing particular examples only and is not intended to limit the present disclosure. As used herein, the singular forms are also intended to include the plural forms unless the context clearly dictates otherwise. It will be further understood that the terms "comprising" and/or "comprising" when used in this specification designate the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more Presence of other features, integers, steps, operations, elements, components and/or groups thereof or add.

It will be understood that, although the terms first, second, etc. may be used herein to describe various components, elements, regions, layers and/or sections, these components, elements, regions, layers and/or sections should not be limited by restricted by these terms. These terms are only used to distinguish one component, element, region, layer and/or section from another. Thus, for example, a first element, element, region, layer and/or section discussed below could be termed a second element, a first element, a first section, and/or a first section without departing from the teachings of the present invention. Two elements, second regions, second layers and/or second sections.

For ease of description, spatially relative terms such as "below", "below", "below", "above", "above", etc. are used herein to describe The relationship of one element or feature to another element or feature (as shown). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the accompanying figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and thus the spatially relative descriptors used herein may be interpreted.

Furthermore, the term "coplanar" and similar terms are used herein to refer to two surfaces that lie in the same plane. Coplanar surfaces may be adjacent or contiguous to each other; however surfaces that are not adjacent and/or non-contiguous may also be coplanar. For example, gaps, voids, and/or other structures may be inserted between the coplanar surfaces. Again, due to manufacturing tolerances, thermal expansion, etc., there may be slight deviations in co-planarity. This deviation can cause one surface to be slightly higher than the other, creating a step-off (eg, rising or falling) between the surfaces. As used herein, the term "coplanar" includes a stepped surface that ranges between 0 and 7 microns.

Various embodiments of the present disclosure provide a semiconductor device and a method of fabricating the same, which can implement a three-dimensional (3D) system package including a sensor through a wafer-level process.

Various embodiments of the present disclosure also provide a semiconductor device and a method of fabricating the same, which can realize a very thin three-dimensional (3D) package including a sensor.

Various embodiments of the present disclosure also provide a semiconductor device and a manufacturing method thereof, which can be used in a fingerprint sensor, an optical sensor, or a tire pressure sensor.

According to various embodiments of the present disclosure, a semiconductor device may include: a first semiconductor die including a first surface, a second surface opposite the first surface, and a first die bond pad formed on the first surface; a second surface an encapsulation surrounding the first semiconductor die and including a first surface adjacent to the first surface; a first redistribution structure formed on the first surface of the first semiconductor die and the first encapsulation on a first surface of the object; a second semiconductor die including a first surface, a second surface opposite the first surface, and a second die bond pad formed on the first surface; a second encapsulation, which surrounding the second semiconductor die and including a first surface adjacent to the first surface; a second redistribution structure formed on the first surface of the second semiconductor die and the first surface of the second encapsulation and conductive vias extending through the first and second encapsulations to electrically connect the first and second redistribution structures to each other.

Furthermore, according to various embodiments of the present disclosure, a semiconductor device may include: a first semiconductor die including a first die bond pad; a first encapsulation exposing the first die bond pad and surrounding the first semiconductor die die; a first redistribution structure formed on the first semiconductor die and the first encapsulation and connected to the first die bond pad; a second semiconductor die including a second die bond pad; Two encapsulations exposing the second die bond pads and surrounding the second semiconductor die; a second redistribution structure formed on the second semiconductor die and the second encapsulation and connected to the second die bond pads; and conductive vias that electrically connect the first redistribution structure and the second redistribution structure to each other.

Furthermore, according to various embodiments of the present disclosure, a semiconductor device may include: a first semiconductor die; a first encapsulation surrounding the first semiconductor die; and a first redistribution structure formed on the first semiconductor die and on the first encapsulation; the second semiconductor die; the second encapsulation, which surrounds the second a semiconductor die; a second redistribution structure formed on the second semiconductor die and the second encapsulation; and a conductive via electrically connecting the first redistribution structure and the second redistribution structure to each other.

As described above, according to various embodiments of the present disclosure, a semiconductor device and a method for fabricating the same can be provided, which can realize a three-dimensional (3D) system package including a sensor through a wafer-level process. That is, according to various embodiments of the present disclosure, a first semiconductor die (eg, a logic die, etc.) for which a first encapsulation is formed and determined to be good is mounted on a first carrier, and a second The encapsulation is formed and a second semiconductor die (eg, a sensor die, etc.) determined to be good is mounted on a second carrier. Next, in a state where the first encapsulation and the second encapsulation are adhered to each other, conductive vias and redistribution structures are formed. Finally, individual devices are formed by a sawing process, enabling 3D system packaging including sensors using wafer-level processes.

Furthermore, according to various embodiments of the present disclosure, a semiconductor device and a method of fabricating the same can be provided, which can realize a very thin three-dimensional (3D) system package including a sensor. That is, a first semiconductor die (eg, a logic die, etc.) and a second semiconductor die (eg, a sensor die, etc.) are close to each other to be then vertically stacked, and thin re- A distribution structure (rather than a relatively thick circuit board) is formed on the surfaces of the first and second semiconductor dies by a fan-out method, thereby enabling a very thin three-dimensional (3D) package including the sensor. While various embodiments use the thin redistribution structures provided by the fan-out approach, other embodiments may alternatively use prefabricated circuit boards.

Furthermore, according to various embodiments of the present disclosure, a semiconductor device and a manufacturing method thereof can be provided, which can be used in a fingerprint sensor, an optical sensor, or a tire pressure sensor. In particular, according to various embodiments of the present disclosure, various sensors and processors are integrated into a single package, thereby reducing overall system size and minimizing power consumption.

Referring to FIG. 1 , a cross-sectional view of a semiconductor device 100 according to example embodiments of the present disclosure is shown. As illustrated in FIG. 1 , semiconductor device 100 may include: one or more first semiconductor die 110; first encapsulation 120; first redistribution structure 130; second semiconductor die 140; second encapsulation 150; second redistribution structure 160; and conductive via 170. In addition, the semiconductor device 100 may further include: an adhesive layer 180 adhering the first encapsulant 120 and the second encapsulant 150 to each other. The semiconductor device 100 may further include a plurality of external interconnect structures 190 connected to the first redistribution structure 130 or the second redistribution structure 160 .

Each of the one or more first semiconductor dies may have a substantially flat first surface 111 and a substantially flat second surface 112 opposite the first surface 111 . Each first semiconductor die 10 may further have: a substantially flat third surface 113 connecting the first surface 111 and the second surface 112 to each other; and at least one bonding pad 114 formed on the first surface 111 .

The first surface 111 may further include a passivation layer. In particular, the first surface 111 may correspond to the surface of the passivation layer. Furthermore, the first surface 111 may correspond to an active area, and the second surface 112 may correspond to an inactive area of a circuit integrated in the first semiconductor die 110 .

As shown, the one or more first semiconductor dies 110 may include a plurality of first semiconductor dies that are configured to be horizontally spaced apart from each other by a predetermined distance. Therefore, the third surfaces 113 of the first semiconductor die 110 may be disposed to face each other. Furthermore, for example, the first semiconductor die 110 may include one or more integrated circuits selected from the group consisting of logic circuits, microcontroller units, memories, digital signal processors, network processors, power management units , audio processors, RF circuits, wireless baseband systems on chip processors, and application-specific integrated circuits and their equivalents.

The first encapsulation 120 may include a substantially flat first surface 121 adjacent to and coplanar with the first surface 111 and surrounding the first semiconductor die 110 . The first encapsulation 120 may further include a substantially flat second surface 122 opposite the first surface 121 . The first encapsulation 120 may also include a third surface 123 connecting the first surface 121 and the second surface 122 to each other.

The second surface 122 of the first encapsulant 120 may be spaced apart from the second surface 112 of the first semiconductor die 110 by a predetermined distance in the vertical direction. In particular, the first encapsulant 120 may have a predetermined thickness in a substantially vertical direction opposite to the second surface 112 of the first semiconductor die 110 .

In some embodiments, the first encapsulant 120 may include non-conductive materials such as resins, organic resins, inorganic fillers, curing agents, catalysts, coupling agents, colorants, flame retardants, epoxy encapsulant resins, Polymer composites, filled polymers, epoxy resins, filled epoxy acrylates (such as silica or other inorganic materials), molding compounds, silicone and/or resin impregnated B-stages (B-stage) prepreg film, etc. These features of the first encapsulation 120 can also be applied to the second encapsulation 150 and any other encapsulations described herein.

The first redistribution structure 130 may be formed on the first surface 111 of the first semiconductor die 110 and the first surface 121 of the first encapsulant 120 by a fan-out method. In particular, the first redistribution structure 130 may include one or more metal layers 131 that electrically connect the bond pads 114 and the conductive vias 170 to each other. The first redistribution structure 130 may further include one or more dielectric layers 132 . In one embodiment, the first redistribution structure 130 includes a plurality of metal layers 131 and a plurality of dielectric layers 132 vertically stacked on each other, such that the dielectric layers 132 are interposed between the metal layers 131 and the metal layers 131 are interposed with each other. Electrical isolation. The first redistribution structure 130 may further include a plurality of conductive vias 133 , each of which passes through the respective dielectric layers 132 and electrically interconnects the metal layers 131 separated by the respective dielectric layers 132 .

In some embodiments, each metal layer 131 and/or conductive via 133 may include at least one conductive material selected from the group consisting of: copper (Cu), copper alloy, aluminum (Al), aluminum alloy, Gold (Au), Gold Alloy, Platinum (Pt), Platinum Alloy, Silver (Ag), Silver Alloy, Nickel (Ni), Nickel Alloy, Tin (Sn), Tin Alloy, Palladium (Pd), Palladium Alloy, Chromium ( Cr), chromium alloys and their equivalents. In addition, each dielectric layer 132 may include at least one dielectric material selected from the group consisting of: polyimide (PI), benzocyclobutene (BCB), polybenzoxazole ( PBO), bismaleimide (BT), phenolic resin, epoxy encapsulant compound, epoxy encapsulant resin or equivalents thereof. These features of the first redistribution structure 130 can be applied equally to the second redistribution structure 160 described below.

The second semiconductor die 140 may include: a substantially flat first surface 141; a substantially flat second surface 142 opposite to the first surface 141; and connecting the first surface 141 and the second surface 142 to each other Connected substantially flat third surface 143 . The second semiconductor die 140 may further include bonding pads 144 formed on the first surface 141 .

The first surface 141 may include a passivation layer. In particular, the first surface 111 may correspond to the surface of the passivation layer. Furthermore, the first surface 141 may correspond to an active area (eg, a sensing area), and the second surface 142 may correspond to an inactive area of a circuit integrated in the second semiconductor die 140 . Furthermore, the passivation layer of the first surface 141 can protect the sensing area from the external environment.

In this embodiment, the second semiconductor die 140 may include sensing circuits such as, for example, fingerprint sensors, optical sensors, pressure sensors, accelerometers, gyroscope sensors, and MEMS (micro Electromechanical systems) device or its equivalent. As such, the second semiconductor die 140 may include a corresponding sensing area on the first surface 141, such as, for example, a fingerprint sensing area, a light sensing area, a pressure sensing area, an acceleration sensing area, or a gyration sensing area. measurement area.

The second encapsulant 150 may include a substantially planar first surface 151 adjacent to and coplanar with the first surface 141 of the second semiconductor die 140 and surrounding the second semiconductor die 140 . The second encapsulation 140 may further include a substantially flat second surface 142 opposite the first surface 151 and a third surface 153 connecting the first surface 151 and the second surface 152 to each other. The second surface 152 of the second encapsulant 150 may be spaced apart from the second surface 142 of the second semiconductor die 140 by a predetermined distance in the vertical direction. In particular, the second encapsulant 150 may have a predetermined thickness in a substantially vertical direction opposite to the second surface 142 of the second semiconductor die 140 .

Furthermore, the physicochemical characteristics of the second encapsulation 150 may be the same, similar or different from the first encapsulation 120 . As an example, the modulus of the second encapsulation 150 may be smaller than the modulus of the first encapsulation 120 . More particularly, the elastic force of the second encapsulation 150 may be greater than the elastic force of the first encapsulation 120 . As a result, the second encapsulation 150 can withstand externally applied mechanical impact and pressure without breaking due to its shape change. This characteristic is particularly advantageous for safely protecting the semiconductor device 100 when the second semiconductor die 140 is exposed to the external environment.

Meanwhile, the second surface 122 of the first encapsulation 120 and the second surface 152 of the second encapsulation 150 may be adhered to each other. In an example embodiment, the adhesive layer 180 may be interposed between the second surface 122 of the first encapsulation 120 and the second surface 152 of the second encapsulation 150 . In such embodiments, the adhesive layer 180 may include a heat-curable epoxy adhesive, a heat-curable epoxy double-sided adhesive, or an equivalent thereof.

As shown, the first semiconductor die 110 and the second semiconductor die 140 may be separated from each other by a predetermined distance in the vertical direction by the first encapsulation 120 and the second encapsulation 150 . As such, the second surface 112 of the first semiconductor die 110 and the second surface 142 of the second semiconductor die 140 may be spaced apart from each other in the vertical direction due to the interposed first encapsulation 120 and the second encapsulation 150 . predetermined distance.

The second redistribution structure 160 may be formed on the first surface 141 of the second semiconductor die 140 and the first surface 151 of the second encapsulant 150 by a fan-out method. Similar to the first redistribution structure 130 , the second redistribution structure 160 may include one or more metal layers 161 that electrically connect the bond pads 144 to the conductive vias 170 . The second redistribution structure 160 may further include one or more dielectric layers 162 . In one embodiment, the second redistribution structure 160 includes a plurality of metal layers 161 and a plurality of dielectric layers 162 vertically stacked on each other, such that the dielectric layers 162 are interposed between the metal layers 161 and connect the metal layers 161 to each other. Electrical isolation. The second redistribution structure 160 may further include a plurality of conductive vias (not shown), each conductive via passing through a respective dielectric layer 162 and electrically connecting the metal layers 131 separated by the respective dielectric layers 162 Sexual interconnection.

As shown, the first surface 111 of the first semiconductor die 110 may be completely covered by the first redistribution structure 130 . However, unlike the first surface 111 , the first surface 141 of the second semiconductor die 140 may not be completely covered by the second redistribution structure 160 . In particular, the second redistribution structure 160 exposes the sensing region of the first surface 141 to the environment outside the semiconductor device. Therefore, the sensing circuit of the second semiconductor die 140 can sense the external environment through the sensing area without being hindered by the second redistribution structure 160 . Furthermore, the side surface of the first redistribution structure 130 , the third surface 123 of the first encapsulation 120 , the side surface of the adhesive layer 180 , the third surface 153 of the second encapsulation 150 , and the second redistribution The side surfaces of the new distribution structure 160 may be coplanar.

The conductive via 170 may electrically connect the first redistribution structure 130 and the second redistribution structure 160 to each other. To this end, the conductive via 170 may extend through the first encapsulation 120 , the adhesive layer 180 and the second encapsulation 150 and electrically connect the metal layer 131 of the first redistribution structure 130 to the second redistribution structure Metal layer 161 of 160 . In some embodiments, an organic insulating layer or an inorganic insulating layer may be interposed between the conductive via 170 and each of the first encapsulation 120 , the adhesive layer 180 and the second encapsulation 150 . Furthermore, the conductive via 170 may include at least one conductive material selected from the group consisting of: copper (Cu), copper alloy, aluminum (Al), aluminum alloy, gold (Au), gold alloy, platinum (Pt) ), platinum alloys, silver (Ag), silver alloys, nickel (Ni), nickel alloys, tin (Sn), tin alloys, palladium (Pd), palladium alloys, chromium (Cr), chromium alloys, and their equivalents.

Because the first semiconductor die 110 and the second semiconductor die 140 are electrically connected to each other through the conductive via 170 , the first semiconductor die 110 can process signals sensed from the second semiconductor die 140 . The first semiconductor die 110 may further transmit the processed signals to external devices via one or more external interconnect structures 190 .

The external interconnection structure 190 may be formed on the first redistribution structure 130 or the second redistribution structure 160 . For example, if the first redistribution structure 130 is to be mounted on an external device, the external interconnection structure 190 may be electrically connected to the metal layer 131 of the first redistribution structure 130 . Alternatively, if the second redistribution structure 160 is to be mounted on an external device, the external interconnection structure 190 may be electrically connected to the metal layer 161 of the second redistribution structure 160 . FIG. 1 illustrates the external interconnect structure 190 formed on the first redistribution structure 130 .

Additionally, each external interconnect structure 190 may include metal posts, metal posts with solder caps, solder bumps, solder balls, bumps, lands, flexible circuit boards, and equivalents thereof. In particular, external interconnect structures 190, such as metal posts, solder bumps, solder balls, or pads, may allow the semiconductor device 100 to be positioned close to the external device to which it is connected. In contrast, external devices such as flexible circuit boards The external interconnect structures 190 may be fabricated to have various shapes and lengths, and may allow the semiconductor device 100 to be positioned farther from external devices than, for example, bumps or pads.

As described above, the semiconductor device 100 according to an embodiment of the present disclosure can simultaneously accommodate the first semiconductor die 110 for processing signals and the second semiconductor die 140 for sensing signals in a minimum volume space. More specifically, the semiconductor device 100 may provide a very thin 3D package including a sensor using a first semiconductor die 110 (eg, a logic die, etc.) and a second semiconductor die 140 (eg, a sensor) dies, etc.) are vertically stacked between the thin first and second redistribution structures 130 and 160 to obtain a relatively thin semiconductor device 100 .

In example embodiments, the stacking of the first semiconductor die 110 and the second semiconductor die 140 can reduce the horizontal area of the semiconductor device 100 by about 40% to 60% compared to conventional semiconductor devices. In addition, compared with the conventional semiconductor device, the first redistribution structure 130 and the second redistribution structure 160 formed by the fan-out method can reduce the vertical thickness of the semiconductor device 100 by about 30% to 40%. In addition, since the area and thickness of the semiconductor device 100 are reduced, the power consumption of the semiconductor device 100 is reduced while the processing speed is improved.

Referring to FIG. 2, a flowchart of an example method of fabricating semiconductor device 100 is shown. As illustrated in FIG. 2, the example fabrication method may include the steps of: attaching a first semiconductor die to a first carrier and forming a first encapsulation (step S1); attaching a second semiconductor die to a first on the two carriers and form a second encapsulation (step S2); attach the first encapsulation and the second encapsulation to each other (step S3); remove the first carrier (step S4); form conductive vias ( step S5); forming a first redistribution structure (step S6); removing the second carrier (step S7); forming a second redistribution structure (step S8); forming an external interconnect structure (step S9); and sawing ( Step S10).

The order of the above steps may be changed according to the particular example embodiment of the manufacturing method. For example, step S2 may be performed first and step S1 may be performed next. Alternatively, step S1 and step S2 may be performed simultaneously. In another example embodiment, step S7 may be performed first and step S5 can then be executed. In yet another example embodiment, step S8 may be performed first and step S6 may be performed next.

Referring to FIGS. 3A to 3J , cross-sectional views illustrating a method of fabricating the semiconductor device 100 are illustrated. In particular, FIG. 3A illustrates attaching the first semiconductor die 110 on the first carrier 210 and forming the first encapsulation 120 according to step S1 . In particular, the first temporary adhesive layer 211 may be formed on the first carrier 210 , and the first semiconductor die 110 may be attached on the first temporary adhesive layer 211 . Furthermore, the first encapsulation 120 may be molded on the first semiconductor die 110 disposed on the first temporary adhesive layer 211 , so that the first encapsulation 120 surrounds and covers the first semiconductor die 110 and the first temporary adhesive layer 211 .

In some embodiments, the first carrier 210 may include glass, low-quality silicon wafers, metals (eg, copper, aluminum, stainless steel, nickel, etc.), ceramics (eg, aluminum oxide, silicon carbide, aluminum nitride, zirconia, etc.) etc.) and their equivalents. The first carrier 210 may be surface-treated to allow the first temporary adhesive layer 211 to have proper adhesion. In an example embodiment, the first carrier 210 may have a surface roughness of about 2 μm or less, and may have a diameter between 200 mm and 300 mm, which is similar to standard semiconductor wafer dimensions. In addition, the first carrier 210 may, for example, be ground only in a specific direction to facilitate removal/stripping of the first temporary adhesive layer 211 from the first carrier in a subsequent step. For example, the first carrier 210 may have an anodized surface. For example, the first carrier 210 may comprise a metal alloy capable of operating to withstand large temperature changes without deformation and exhibiting minimal surface corrosion over time. These features of the first carrier 210 can also be applied to the second carrier 220 described below.

The first temporary adhesive layer 211 (or adhesive film) may, for example, comprise a heat sensitive double-sided tape, which adheres the first semi-semiconductor die 110 (eg, sawed or singulated die) to the first carrier 210 . In some embodiments, the first temporary adhesive layer 211 may comprise a thermally releasable tape that exhibits reduced adhesion at temperatures in the range of about 90°C to about 200°C. Such thermally releasable tapes may include foam adhesives, polyether films, and base adhesives sandwiched between backing layers, such as for example at REVALPHA's Adhesive tape manufactured by Nitto Denko under the product name. As an example, a thermally peelable tape may include a polyester liner about 75 μm thick, a base adhesive about 10 μm thick, a polyester film about 40 μm thick, a foam adhesive about 50 μm thick, and a polyester liner about 40 μm thick.

In some embodiments, the first temporary adhesive layer 211 can withstand temperature changes and can maintain its adhesion at elevated temperatures during subsequent processes (eg, semiconductor die attach and/or encapsulation) at elevated temperatures force. Additionally, the first temporary adhesive layer 211 can withstand compressive loads during subsequent semiconductor die attach and/or encapsulation processes. For example, the attached first semiconductor die 110 during this compression process (eg, in the step of attaching the semiconductor die) preferably penetrates the first temporary bond as little as possible The plane of layer 211, thereby maintaining flatness or coplanarity between the die surface and the encapsulate surface. These features of the first temporary adhesive layer 211 can also be applied to the second temporary adhesive layer 221 described below.

As shown in FIG. 3A , the bond pads 114 and the first surface 111 of the first semiconductor die 110 may be directly attached to the first temporary adhesive layer 211 . Furthermore, the bonding pads 114 and the first surface 111 of the first semiconductor die 110 do not need to penetrate excessively into the first temporary adhesive layer 211 or press the first temporary adhesive layer 211 . In addition, the first encapsulant 120 may be formed to surround the first semiconductor die 110 disposed on the first temporary adhesive layer 211 . Therefore, the first surface 111 of the first semiconductor die 110 and the first surface 121 of the first encapsulation 120 become coplanar with each other. In some embodiments, the first encapsulation 120 may be formed by compression molding (eg, processes using liquids, powders, and/or films), vacuum molding, transfer molding, injection molding, and the like.

Furthermore, the first encapsulant 120 may have a predetermined thickness with the second surface 122 offset in a substantially vertical direction from the second surface 112 of the first semiconductor die 110 . In particular, the second surface 122 of the first encapsulation 120 may be spaced apart from the second surface 112 of the first semiconductor die 110 by a predetermined distance in the vertical direction. However, in some cases, the predetermined area of the first encapsulant 120 may be removed by a mechanical and/or chemical polishing process. This removal can cause the second surface 122 of the first encapsulation 120 and the first half The second surfaces 112 of the conductor die 110 are coplanar.

Only two first semiconductor dies 110 are attached and molded on the first carrier 210 and the first temporary adhesive layer 211 as depicted in FIG. 3A . However, in some embodiments, many more first semiconductor dies 110 (eg, 10 to 100) may be horizontally aligned, attached and molded on the first carrier 210 and the first temporary adhesive layer 211 on.

As illustrated in FIG. 3B , step S2 may include attaching the second semiconductor die 140 onto the second carrier 220 and forming the second encapsulation 150 . More particularly, the second temporary adhesive layer 221 may be formed on the second carrier 220 , and the second semiconductor die 140 may be attached to the second temporary adhesive layer 221 . Furthermore, the second encapsulant 150 may be molded on the second semiconductor die 140 disposed on the second temporary adhesive layer 221 such that the second encapsulant 150 surrounds and covers the second semiconductor die 140 and the second temporary adhesive layer 221 . These features of the second temporary adhesive layer 221 may be the same or similar to the first temporary adhesive layer 211 and the first carrier 210 described above.

In some embodiments, the first surface 141 and the bond pads 144 of the second semiconductor die 140 may be directly attached to the second temporary adhesive layer 221 . Furthermore, the bonding pads 144 and the first surface 141 of the second semiconductor die 140 do not need to penetrate excessively into the second temporary adhesive layer 221 or press the second temporary adhesive layer 221 . In addition, the second encapsulant 150 may be formed to surround the second semiconductor die 140 disposed on the second temporary adhesive layer 221 . Therefore, the first surface 141 of the second semiconductor die 140 and the first surface 151 of the second encapsulant 150 are coplanar with each other.

In addition, the second encapsulant 150 may have a predetermined thickness, wherein the second surface 152 is offset in a substantially vertical direction from the second surface 142 of the second semiconductor die 140 . In particular, the second surface 152 of the second encapsulant 150 may be spaced apart from the second surface 142 of the second semiconductor die 140 by a predetermined distance in the vertical direction. However, in some cases, the predetermined area of the second encapsulant 150 may be removed by a grinding and/or etching process. This removal may cause the second surface 152 of the second encapsulant 150 to be coplanar with the second surface 142 of the second semiconductor die 140 .

There is only one second semiconductor die 140 attached and molded on the second carrier 220 and the second temporary adhesive layer 221 as depicted in FIG. 3B . However, in some embodiments, many more second semiconductor dies 140 (eg, 5 to 50) may be horizontally aligned, attached and molded on the second carrier 220 and the second temporary adhesive layer 221 on.

As illustrated in FIG. 3C, step S3 may include attaching the first encapsulation 120 and the second encapsulation 150 to each other. To this end, an adhesive layer 180 may be interposed between the first encapsulation 120 and the second encapsulation 150 so that the first encapsulation 120 and the second encapsulation 150 are adhered to each other. More particularly, the second surface 122 of the first encapsulation 120 and the second surface 152 of the second encapsulation 150 may be adhered to each other with the adhesive layer 180 interposed therebetween.

In some embodiments, the adhesive layer 180 may be cured by applying a temperature in the range of about 100°C to about 200°C and a pressure in the range of 1 MPa to 100 MPa. In particular, after the adhesive layer 180 is interposed between the first encapsulation 120 and the second encapsulation 150, the first encapsulation 120 and the second encapsulation 150 may be positioned on the upper mold and the lower mold ( each with a heater mounted thereon). Next, a temperature in the range of about 100°C to about 200°C and a pressure in the range of 1 MPa to 100 MPa may be applied via the upper and lower molds.

Meanwhile, the operating temperature of the die attach and encapsulation process is preferably lower than the temperature at which the first and second temporary adhesive layers 211 and 221 are peeled off. For example, if the first temporary adhesive layer 211 and the second temporary adhesive layer 221 are peeled at a temperature of about 200°C, the operating temperature of the die attach and encapsulation process is preferably below about 200°C .

In addition, for ease of handling, the first temporary adhesive layer 211 and the second temporary adhesive layer 221 may be peeled off at different temperatures. For example, if the first temporary adhesive layer 211 is peeled off at about 190°C, the second temporary adhesive layer 221 may be peeled off at about 200°C. In this embodiment, after the first temporary adhesive layer 211 is peeled off, the second semiconductor die 140 and the second encapsulant 150 may remain attached to the second temporary adhesive layer 221 . In particular, the second temporary layer 221 may be formed between the conductive via 170 and the first redistribution junction The adhesion is maintained during the formation of the structure 130, thereby preventing the second semiconductor die 140 and the second encapsulant 150 from being polluted by the external environment.

As illustrated in FIG. 3D , step S4 may include removing the first carrier 210 and the first temporary adhesive layer 211 from the first semiconductor die 110 and the first encapsulant 120 . To this end, the first temporary adhesive layer 211 may be heated until the first carrier 210 is separated from the first semiconductor die 110 and the first encapsulant 120 . After heating the first temporary adhesive layer 211 , the first carrier 210 and the first temporary adhesive layer 211 are peeled off and removed from the first semiconductor die 110 and the first encapsulant 120 . In particular, the first temporary adhesive layer 211 need not remain on the first surface 111 of the first semiconductor die 110 and the first surface 121 of the first encapsulant 120 . As described above, the first carrier 210 may be ground in a specific direction. This grinding may cause the first temporary adhesive layer 211 to remain adhered to the first carrier while releasing its adhesion to the first semiconductor die 110 and the first encapsulation 120 .

As shown, after removing the first temporary adhesive layer 211, the first surface 111 of the first semiconductor die 110 and the first surface 121 of the first encapsulant 120 are coplanar with each other and exposed. In particular, the removal of the first temporary adhesive layer 211 exposes the first surface 111 (eg, the first die passivation layer) and the bond pads 114 of the first semiconductor die 110 to the environment outside the semiconductor device 100 .

As illustrated in FIG. 3E , step S5 may include forming conductive vias 170 extending through the first encapsulation 120 , the adhesive layer 180 and the second encapsulation 150 . In example embodiments, a laser beam, mechanical drilling, or chemical etching are used to form through holes that extend through the first encapsulant 120 , the adhesive layer 180 , and the second encapsulant 150 . Furthermore, the through hole may be filled with a conductive material to form a conductive via 170 in the through hole. In particular, conductive vias 170 may be formed in the vias using various processes such as, for example, electroless plating, electroplating, or sputtering. In some embodiments, the insulating layer may be formed in the vias using organic and/or inorganic materials, and then conductive vias 170 may be formed on the inner surface of the insulating layer. Regardless, conductive vias may include copper (Cu), copper alloys, aluminum (Al), aluminum alloys, gold (Au), gold alloys, platinum (Pt), platinum alloys, silver (Ag), silver alloys, nickel ( Ni), nickel alloys, tin (Sn), tin alloys, palladium (Pd), palladium Alloys, Chromium (Cr), Chromium Alloys and Equivalents.

As illustrated in FIG. 3F , step S6 may include forming the first redistribution structure 130 on the first surface 111 of the first semiconductor die 110 and the first surface 121 of the first encapsulant 120 by a fan-out method . In particular, the metal layer 131 of the first redistribution structure 130 may be formed to electrically connect the bond pads 114 of the first semiconductor die 110 to the conductive vias 170 . To this end, the metal layer 131 may be formed on the first surface 111 of the first semiconductor die 110 and the first surface 121 of the first encapsulation 120 by electroless plating, electroplating or sputtering. The metal layer 131 can be further patterned or routed by a subsequent photolithography etching process.

Also, a dielectric layer 132 may be formed on the first surface 111 of the first semiconductor device 110 , the first surface 121 of the first encapsulant, and the patterned metal layer 131 . In particular, the dielectric layer 132 may be formed using various processes such as spin coating, spray coating, deep coating, and the like. As shown, the first redistribution structure 130 may have a multi-layer structure. In particular, the first redistribution structure 130 may include a plurality of metal layers 131 and dielectric layers 132 vertically stacked with each other. Furthermore, the first redistribution structure may include a plurality of conductive vias 133 passing through the respective dielectric layers 132 to electrically interconnect the metal layers 131 separated by the respective dielectric layers 132 . FIG. 3F illustrates an embodiment of the first redistribution structure 130 including three metal layers 131 and three dielectric layers 132 . However, other embodiments of the first redistribution structure 130 may include different numbers of metal layers 131 and/or dielectric layers 132 .

FIG. 3F further depicts openings 134 formed in the bottommost dielectric layer 132 . In particular, the openings 134 may be formed using a photolithography process or other processes. Furthermore, each opening 134 may expose a predetermined area of the metal layer 131 . Such exposure may allow the external interconnect structure 190 to be electrically connected to exposed areas of the metal layer 131 .

As illustrated in FIG. 3G , step S7 may include removing the second carrier 220 and the second temporary adhesive layer 221 from the second semiconductor die 140 and the second encapsulant 150 . In particular, the second temporary adhesive layer 221 may be heated until the adhesion between the second carrier 220 and the second semiconductor die 140 and the second encapsulant 150 compounds are removed or reduced. After heating, the second carrier 220 and the second temporary adhesive layer 221 may be separated from the second semiconductor die 140 and the second encapsulant 150 . Such removal may expose the first surface 141 of the second semiconductor die 140 , the first surface 151 of the second encapsulant 150 , and the surface of the conductive via 170 to the environment outside the semiconductor device 100 . Again, this removal may cause the surfaces of the first surface 141 , the first surface 151 and the conductive via 170 to be coplanar with each other.

As illustrated in FIG. 3H , step S8 may include forming the second redistribution structure 160 on the first surface 141 of the second semiconductor die 140 and the first surface 151 of the second encapsulant 150 by a fan-out method . In particular, the metal layer 161 of the second redistribution structure 160 can electrically connect the bonding pads 144 of the second semiconductor die 140 to the conductive vias 170 . Furthermore, a second dielectric layer 162 may be formed on the first surface 141 of the second semiconductor device, the first surface 151 of the second encapsulant, and the metal layer 161 . As illustrated, the second redistribution structure 150 includes a single metal layer 161 and a single dielectric layer 162 . However, in other embodiments, the second redistribution structure 160 may comprise a multilayer structure similar to the first redistribution structure 130 described above. As a result of the above process, the first redistribution structure 130 and the second redistribution structure 160 can be electrically connected to each other through the conductive via 170 .

As described above, the first redistribution structure 130 and the second redistribution structure 160 are formed in-situ via a fan-out method. However, in various embodiments, the first redistribution structure 130 and/or the second redistribution structure 160 may be formed using a printed circuit board or other pre-built structure rather than via an in-situ fan-out method.

As further illustrated in FIG. 3H , the second redistribution structure 160 may expose the sensing region of the first surface 141 of the second semiconductor die 140 to the environment outside the semiconductor device 100 . In particular, the second redistribution structure 160 does not need to cover the sensing area of the first surface 141 of the second semiconductor die 140 to allow direct sensing of external phenomena via the sensing area. In some embodiments, a protective member or layer may be further attached to the second redistribution structure 160 and the first surface 141 of the second semiconductor die 140 to protect the sensing area of the first surface 141 from the external environment influences.

As illustrated in FIG. 3I , step S9 may include forming an external interconnect structure 190 that is electrically connected to the first redistribution structure 130 . In particular, forming interconnect structure 190 may include forming one or more metal pillars, solder bumps, solder balls, bumps, pads, or flexible circuit boards that are electrically connected to The area of metal layer 131 exposed by opening 134 in 132 . In an exemplary embodiment, the external interconnect structure 190 is attached to the first redistribution structure 130 . However, in some embodiments, an external interconnect structure 190 may be attached to the second redistribution structure 160 in place of or in addition to the first redistribution structure 130 .

As illustrated in FIG. 3J , step S10 may include sawing the first redistribution structure 130 , the first encapsulation 120 , the adhesive layer 180 , the second encapsulation 150 , and the second redistribution structure 160 with a sawing tool 199 , to provide individual semiconductor devices 100 . In particular, the semiconductor device 100 may be fabricated by arranging a plurality of devices 110 in a strip or matrix structure to increase productivity. Sawing, dicing, or other singulation processes may be performed at the end of the manufacturing process to separate integrated devices into individual semiconductor devices 100 .

Thermally peelable tapes such as temporary adhesive layers 211 and 221 have been described in the embodiments exemplified in this disclosure. However, UV peelable tapes can also be used as the temporary adhesive layers 211 and 221 . In this embodiment, carriers 210 and 220 may be formed of a transmissive material, such as glass, and UV radiation may pass through the transmissive material to peel or reduce adhesion.

Referring to FIG. 4, a cross-sectional view of a semiconductor device 300 according to example embodiments of the present disclosure is shown. Since the semiconductor device 300 illustrated in FIG. 4 is similar to the semiconductor device 100 in FIG. 1 , the following will focus on the differences between the semiconductor devices.

Unlike the semiconductor device 100 , the second surface 112 of the first semiconductor die 110 of the semiconductor device 300 may be adhered to the second surface 142 of the second semiconductor die 140 by an adhesive layer 380 . As illustrated in FIG. 1 , the semiconductor device 100 includes an encapsulant material having a predetermined thickness between the second surface 112 of the first semiconductor die 110 and the second surface 122 of the first encapsulant 120 and the second semiconductor Die 140 There is a predetermined thickness of encapsulant material between the second surface 142 of the second encapsulant 150 and the second surface 152 of the second encapsulant 150 . However, in the semiconductor device 300 illustrated in FIG. 4 , the second surface 112 of the first semiconductor die 110 and the first surface 121 of the first encapsulant 120 are coplanar, and the second surface 112 of the second semiconductor die 140 is coplanar. The second surface 142 and the second surface 152 of the second encapsulation 150 are coplanar. Therefore, the semiconductor device 300 can achieve a more elongated profile than the semiconductor device 100 .

Referring to FIGS. 5A to 5C , cross-sectional views illustrating a method of fabricating the semiconductor device 300 are illustrated. As illustrated in FIG. 5A, after attaching the first semiconductor die 110 to the first carrier 210 and forming the first encapsulation 120, the first encapsulation 120 may be subjected to a grinding and/or etching process. This process may cause the second surface 112 of the first semiconductor die 110 and the second surface 122 of the first encapsulant 120 to be coplanar with each other. Furthermore, this process can expose the second surface 112 of the first semiconductor die 110 and the second surface 122 of the first encapsulant 120 to the environment outside the semiconductor device 300 .

As illustrated in FIG. 5B , after attaching the second semiconductor die 140 to the second carrier 220 and forming the second encapsulation 150 , the second encapsulation 150 may undergo grinding and/or etching processes, resulting in The second surface 142 of the second semiconductor die 140 and the second surface 152 of the second encapsulant 150 are coplanar with each other. In particular, this process may expose the second surface 142 of the second semiconductor die 140 and the second surface 152 of the second encapsulant 150 to the environment outside the semiconductor device 300 .

As illustrated in FIG. 5C , an adhesive layer 380 may be interposed between the first semiconductor die 110 and the second semiconductor die 120 . In particular, the adhesive layer 380 can adhere the second surface 112 of the first semiconductor die 110 and the second surface 122 of the first encapsulation 120 to the second surface 142 of the second semiconductor die 140 and the second encapsulation Second surface 152 of 150 . That is, the second surface 142 of the second semiconductor die 140 may be substantially adhered to the second surface 112 of the first semiconductor die 110, and the second surface 152 of the second encapsulant 150 may be substantially adhered to the second surface 122 of the first encapsulation 120 .

After that, a heating and pressing process may be performed to further integrate the first semiconductor die 110 , the first encapsulation 120 , the second semiconductor die 140 and the second encapsulation 150 through the adhesive layer 380 . Furthermore, after completing the above-described processes, the fabrication method may include several subsequent processes to obtain the semiconductor device of FIG. 4 . For example, the method may further include forming the first redistribution structure 130 , forming the conductive via 170 , forming the second redistribution structure 160 , and forming the external interconnect structure 190 in a manner similar to the fabrication method of the semiconductor device 100 .

Referring to FIG. 6, a cross-sectional view of a semiconductor device 400 according to example embodiments of the present disclosure is shown. Since the semiconductor device 400 illustrated in FIG. 6 is similar to the semiconductor device 300 illustrated in FIG. 4 , the following will focus on the differences between the semiconductor devices 300 and 400 .

As illustrated in FIG. 6 , the first semiconductor die 100 of the semiconductor device may be attached to the second semiconductor die 140 by the first encapsulation 120A and/or the second encapsulation 150A. A boundary between the first encapsulation 120A and/or the second encapsulation 150A need not be noticed or need to exist. More particularly, the first encapsulation 120A and the second encapsulation 150A may be integrated to form a single encapsulation 410 .

In addition, the second surface 112 of the first semiconductor die 110 and the second surface 142 of the second semiconductor die 140 may be spaced apart from each other by a predetermined distance. In particular, the resin material of the first encapsulation 120A and/or the second encapsulation 150A may be interposed between the second surface 112 of the first semiconductor die 110 and the second surface 142 of the second semiconductor die 140 . In some embodiments, the resin and filler material may be interposed together between the second surface 112 of the first semiconductor die 110 and the second surface 142 of the second semiconductor die 140 .

Although FIG. 6 depicts a portion of the encapsulant 410 between the first semiconductor die and the second semiconductor die, in some embodiments the second surface 112 of the first semiconductor die 110 may be directly adhered to the second The second surface 142 of the semiconductor die 140 is in or in contact with the second surface 142 of the second semiconductor die 140 . More particularly, the silicon surface of the first semiconductor die 110 may be directly adhered to or in direct contact with the silicon surface of the second semiconductor die 140 .

Since there is no interfacial surface or adhesive layer at the boundary between the first encapsulation 120A and the second encapsulation 150A, moisture is prevented from penetrating into the interfacial surface or adhesive layer. In addition, due to the bounds The surface or adhesive layer is not externally observed between the first encapsulant 120A and the second encapsulant 150A, so the semiconductor device 400 may enjoy an improved or more visually pleasing product appearance.

Referring to FIG. 7, a cross-sectional view of a method of manufacturing a semiconductor device 400 is illustrated. As illustrated in FIG. 7 , the fabrication method may include encapsulating the first semiconductor die 110 disposed on the first carrier 210 with the first encapsulation 120A (or the first prepreg) at the B-stage. The method may further include encapsulating the second semiconductor die 140 disposed on the second carrier 220 by the second encapsulation 150A (or the second prepreg) in the B-stage. The method may also include adhering the first encapsulation 120A and the second encapsulation 150A to each other. In one embodiment, the first encapsulation 120A and the second encapsulation 150A in the B-stage are semi-cured and flexible. As such, the first encapsulation 120A and the second encapsulation 150A may adhere to each other when appropriately heated and pressurized. In this manner, the first encapsulation 120A and the second encapsulation 150A may be integrated into a single encapsulation 140 without a boundary line existing therebetween. Accordingly, the first encapsulation 120A and the second encapsulation 150A may be adhered to each other, and the first semiconductor die 110 and the second semiconductor die 140 may be in contact with each other.

As described above, the first encapsulation 120A and the second encapsulation 150A may be heated and pressurized. Such heat and pressure may cause the B-staged first and second encapsulants 120A and 150A to undergo a phase change into the C-staged first and second encapsulants 120A and 150A (also That is, into a single encapsulation 410). In particular, a temperature ranging from about 100°C to about 200°C and a pressure ranging from about 1 MPa to about 100 MPa can be applied to the first and second encapsulants 120A and 150A to form the integrated, cured encapsulant 410 .

After completing the processes described above, the method may include several subsequent processes to obtain the semiconductor device 400 . In particular, the method may include forming the first redistribution structure 130 , forming the conductive via 170 , forming the second redistribution structure 160 , and forming the external interconnect structure 190 in a manner similar to the method of fabricating the semiconductor device 100 .

The present disclosure provides exemplary embodiments. The scope of the present disclosure is not limited by these exemplary embodiments restricted. Numerous changes (such as structural changes, dimensions, types of materials, and manufacturing processes), whether explicitly pointed out or implied by the description, can be effected by those skilled in the art in view of the present disclosure.

100‧‧‧Semiconductor device

110‧‧‧First semiconductor die

111‧‧‧First surface

112‧‧‧Second surface

113‧‧‧Third surface

114‧‧‧Bond pads

120‧‧‧First Encapsulation

121‧‧‧First surface

122‧‧‧Second surface

123‧‧‧Third surface

130‧‧‧First Redistribution Structure

131‧‧‧Metal layer

132‧‧‧Dielectric layer

133‧‧‧Conduction through hole

140‧‧‧Second semiconductor die

141‧‧‧First surface

142‧‧‧Second surface

143‧‧‧Third surface

144‧‧‧Bond pads

150‧‧‧Second Encapsulation

151‧‧‧First surface

152‧‧‧Second surface

153‧‧‧Third surface

160‧‧‧Second Redistribution Structure

161‧‧‧Metal layer

162‧‧‧Dielectric layer

170‧‧‧Conductive Vias

180‧‧‧Adhesive layer

190‧‧‧External Interconnect Structure

Claims (20)

A semiconductor device comprising: an underlying semiconductor die including a bottom surface, a top surface relative to the bottom surface of the underlying semiconductor die, and a first surface on the bottom surface of the underlying semiconductor die bond pads; an underlying encapsulation surrounding the underlying semiconductor die, wherein the underlying encapsulation includes a bottom surface adjacent to the bottom surface of the underlying semiconductor die; an underlying redistribution structure where on the bottom surface of the underlying semiconductor die and on the bottom surface of the underlying encapsulation, wherein the underlying redistribution structure includes an underlying metal layer and an underlying dielectric layer, wherein the underlying metal layer has an underlying a metal layer top side and a lower metal layer bottom side, and wherein the lower dielectric layer covers the lower metal layer bottom side; an upper semiconductor die including a top surface, the top relative to the upper semiconductor die a bottom surface of the surface and a second bond pad on the top surface of the upper semiconductor die; an upper encapsulation over the top surface of the lower encapsulation, the upper encapsulation surrounding the upper encapsulation the upper semiconductor die, wherein the upper encapsulation includes a top surface adjacent to the top surface of the upper semiconductor die; an upper redistribution structure that is between the top surface and the upper semiconductor die. on the top surface of the upper encapsulation, wherein the upper redistribution structure includes an upper metal layer and an upper dielectric layer, wherein the upper metal layer has an upper metal layer top side and an upper metal layer bottom side, and wherein the upper dielectric layer covers the upper metal layer top side; and conductive vias extending through the lower encapsulation and the upper encapsulation and connecting the lower redistribution structure to the an upper redistribution structure, wherein the conductive via includes a single conductive structure through at least a portion of the lower encapsulation and at least a portion of the upper encapsulation; and an adhesive layer that adheres the upper semiconductor die to the underlying semiconductor die, wherein the An adhesive layer contacts at least one of the bottom surface of the upper semiconductor die and the top surface of the lower semiconductor die. The semiconductor device of claim 1, wherein the adhesive layer further adheres the top surface of the lower encapsulation to the bottom surface of the upper encapsulation. The semiconductor device of claim 1, wherein: the upper semiconductor die comprises one of: a fingerprint sensor, an optical sensor, a pressure sensor, an accelerometer, a gyroscope sensor, and a microelectromechanical system ( MEMS) device. The semiconductor device of claim 1, further comprising: an external interconnect structure coupled to the underlying redistribution structure, wherein the external interconnect structure comprises one of: a metal post, a solder bump, a solder ball , pads and flexible circuit boards. The semiconductor device of claim 1, wherein: the underlying redistribution structure comprises: a first metal layer on the bottom surface of the underlying semiconductor die and on the bottom surface of the underlying encapsulation , the first metal layer connects the first bond pads of the underlying semiconductor die to the conductive vias; and a first dielectric layer on the first metal layer; and the upper A redistribution structure includes a second metal layer on the top surface of the upper semiconductor die and the top surface of the upper encapsulation, the second metal layer connecting the upper semiconductor die The second bond pads of the are connected to the conductive vias; and a second dielectric layer on the second metal layer. The semiconductor device of claim 5, wherein the conductive via connects the first metal layer of the lower redistribution structure to the second metal layer of the upper redistribution structure. The semiconductor device of claim 5, further comprising an external interconnect structure coupled to the first metal layer of the underlying redistribution structure. The semiconductor device of claim 1, wherein: the upper semiconductor die includes a sensing circuit configured to sense a phenomenon via a sensing region of the top surface of the upper semiconductor die; the overlying redistribution structure includes one or more metal layers; metal from the one or more metal layers does not extend over the sensing region of the top surface of the overlying semiconductor die; and all The sensing circuit is configured to sense, without the obstruction of the metal of the one or more metal layers, via the sensing region and the overlying redistribution structure of the overlying semiconductor die. Describes the phenomenon of the environment outside the semiconductor device. The semiconductor device of claim 1, further comprising an insulating layer interposed between the conductive via and each of the lower encapsulation and the upper encapsulation. The semiconductor device of claim 1, wherein the top surface of the underlying semiconductor die is coplanar with the top surface of the underlying encapsulation. A semiconductor device comprising: an upper semiconductor die including bond pads on a top side of the upper semiconductor die; a lower semiconductor die including bond pads on a bottom side of the lower semiconductor die , wherein the top side of the lower semiconductor die is below the bottom side of the upper semiconductor die; an encapsulation that contacts and surrounds the upper semiconductor die and the lower semiconductor die, the encapsulation the top side of the encapsulation exposes the bond pads of the upper semiconductor die, and the bottom side of the encapsulation exposes the bond pads of the lower semiconductor die; an upper redistribution structure over the upper semiconductor on the top side of the die and the encapsulation, wherein the overlying redistribution structure includes an overlying metal layer and an overlying dielectric layer, wherein the overlying The metal layer has an upper metal layer top side and an upper metal layer bottom side, wherein the upper dielectric layer covers the upper metal layer top side, and wherein the upper metal layer is connected to the upper semiconductor die a bond pad; an underlying redistribution structure below the underlying semiconductor die and the encapsulation and connected to the bond pad of the underlying semiconductor die, wherein the underlying redistribution structure includes an underlying metal layer and an underlying dielectric layer, wherein the underlying metal layer has an underlying metal layer top side and an underlying metal layer bottom side, and wherein the underlying dielectric layer covers the underlying metal layer bottom side; and through the encapsulation The conductive via, wherein the upper end of the conductive via is coupled to the upper redistribution structure and the lower end of the conductive via is coupled to the lower redistribution structure. The semiconductor device of claim 11, wherein the encapsulation includes an encapsulation upper portion surrounding the upper semiconductor die and an encapsulation lower portion surrounding the upper semiconductor die. The semiconductor device of claim 11, wherein the encapsulant is interposed between the bottom side of the upper semiconductor die and the top side of the lower semiconductor die. The semiconductor device of claim 11, wherein the bottom of the upper semiconductor die is directly adhered to the top side of the lower semiconductor die. The semiconductor device of claim 11, further comprising an external interconnect structure coupled to the underlying redistribution structure. The semiconductor device of claim 12, wherein the encapsulation upper portion and the encapsulation lower portion are integrated and form a single integrated encapsulation. The semiconductor device of claim 12, wherein the encapsulation upper portion and the encapsulation lower portion are integrated and there is no discernible boundary between the encapsulation upper portion and the encapsulation lower portion . The semiconductor device of claim 11, wherein the bottom side of the upper semiconductor die contacts the top side of the lower semiconductor die. A semiconductor device includes: an upper semiconductor die including an upper die top side and an upper die bottom side; an upper encapsulation layer including a first encapsulation material surrounding the upper semiconductor die, the upper a bottom side of an encapsulation layer is coplanar with a bottom side of the upper die; an upper redistribution structure is above the upper encapsulation layer and coupled to the upper semiconductor die, wherein the upper redistribution structure includes an upper metal layer and an upper dielectric layer, wherein the upper metal layer has an upper metal layer top side and an upper metal layer bottom side, wherein the upper dielectric layer covers the upper metal layer top side; a lower semiconductor die, which including a top side of the lower die and a bottom side of the lower die; a lower encapsulation layer including a second encapsulation material surrounding the lower semiconductor die, the top side of the lower encapsulation layer and the top of the lower die side coplanar; an underlying redistribution structure below the underlying encapsulation layer and coupled to the underlying semiconductor die, wherein the underlying redistribution structure includes an underlying metal layer and an underlying dielectric layer, wherein the underlying a metal layer having a lower metal layer top side and a lower metal layer bottom side, and wherein the lower dielectric layer covers the lower metal layer bottom side; and conductive vias coupling the upper redistribution structure to the A lower redistribution structure, the conductive via includes a sidewall having a copper material, the sidewall spanning the interface between the upper encapsulation layer and the lower encapsulation layer. The semiconductor device of claim 19, wherein the upper encapsulation is adhered to the lower encapsulation.

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