KR20090085206A - Wafer level package and manufacturing method thereof - Google Patents

Abstract

A wafer level package and a manufacturing method thereof are provided to reduce the whole thickness of a package while being low prices without a substrate. In a wafer level package and a manufacturing method thereof, a chip(130) is mounted in a metal wiring(120a), and a mold(150) is formed on the metal wiring part in order to protect the chip. An external connection member(170) is electrically connected to the lower part of the metal wiring. A wafer level package includes at least more than one a chip, and a wafer level package includes a passive element formed on the metal wiring on which the chip is not formed.

Description

Wafer level package and manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer level package and a method for manufacturing the same, and more particularly, to a wafer level package and a method for manufacturing the package without the substrate, thereby achieving a thinner and lower cost package.

One of the major trends in the semiconductor industry today is to miniaturize semiconductor devices whenever possible. The demand for miniaturization is particularly prominent in the semiconductor chip package industry. A package is a form in which a plastic circuit or a microchip is sealed with a plastic resin or ceramic to be mounted on an actual electronic device.

Conventional typical packages have a much larger size than integrated circuit chips embedded therein. Therefore, reducing the size of the package to the chip size level was one of the concerns of package technicians.

Against this background, a new type of package recently developed is a chip scale package (also called a chip size package). In particular, a wafer level chip scale package is characterized in that packages are assembled and manufactured in a batch in a wafer state, unlike a typical package manufacturing method in which packages are assembled on an individual chip basis.

The development of semiconductor integrated circuit chips has led to the development of package technology, which continues to achieve high density, high speed, miniaturization and thinning. In particular, in terms of the structural aspect of the package device, the development from the pin insert type (through hole mount type) to the surface mount type (surface mount type) has increased the mounting density on the circuit board, and recently bare Active research is being conducted on chip size packages (CSPs) that can reduce the size of packages to chip level while maintaining the characteristics of bare chips in the package state.

Among chip size packages, a type of solder balls formed after rerouting or redistribution of chip pads on a chip surface is called a wafer level chip scale package (WLCSP). The wafer level chip size package is a chip or die mounted directly on the circuit board in a manner called a flip chip, and solder balls formed on the chip's rerouted circuit are bonded to the conductive pad of the circuit board. . At this time, the solder pad is also formed in the conductive pad to form a junction with the solder ball of the package.

In recent years, various chip size package (CSP) technologies, which are small enough to have a small difference in the size of a semiconductor chip and a package, have begun to emerge. .

Along with this, wafer level package technology, which completes all assembly processes in a wafer state in which a chip is not cut, is in the spotlight as the next generation CSP technology. While semiconductor assembly processes to date have been performed after cutting a wafer into individual chips, wafer-level package technology uses die bonding, wire bonding, and molding in the state of a wafer where several chips are attached. After a series of assembly processes such as), it is cut and produced immediately.

1 to 4 are cross-sectional views sequentially showing a method of manufacturing a wafer level package according to the prior art.

First, as shown in FIG. 1, the metal pad 12 is formed on the substrate 10 having the wiring 10a formed therein.

Next, as shown in Figure 2, by mounting the chip 14 in a flip chip bonding method via the conductive adhesive 11 on the upper surface of the substrate 10, the substrate 10 and the chip 14 Are electrically connected to each other. Here, the chip 14 may be mounted in a wire bonding method or the like instead of the flip chip bonding method.

3, a mold 16 covering the chip 14 is formed on the substrate 10. The mold 16 serves to protect the chip 14, the wiring 10a, and the like from an external environment.

Thereafter, as shown in FIG. 4, a solder ball 18 is formed on the lower portion of the substrate 10 to be electrically connected to the wiring 10a.

In the conventional wafer level package described above, the chip 14 is mounted on the substrate 10 to be fabricated. Here, the substrate 10 serves as an important variable for determining the thickness of the package, and there is a problem that it is difficult to achieve a thin package due to the thickness of the substrate 10. In addition, even when the package 10 is manufactured by thinly fabricating the substrate 10 itself, there is a problem that a defect such as a warpage phenomenon may occur during the process of handling the substrate 10 or during the molding process.

In addition, since the cost of the substrate 10 itself is large among the material cost of the package, there is a problem in that the cost of the package is limited.

Accordingly, the present invention was devised to solve the above-mentioned disadvantages and problems raised in the above-described prior art, and an object of the present invention is to manufacture a package without a substrate, thereby making the package thinner and lowering the cost. It is to provide a package and a method of manufacturing the same.

Wafer-level package according to a first embodiment of the present invention for achieving the above object, a plurality of metal wiring spaced at a predetermined interval; A chip mounted on the metal wiring; A mold formed on the metal wiring to protect the chip; And an external connection member electrically connected to a lower portion of the metal wire.

Here, at least one chip formed on the chip is characterized in that it further comprises.

In addition, the chip is not characterized in that it further comprises a passive element formed on the metal wiring.

In addition, the mold is characterized in that extending to the space between the metal wiring.

In addition, the redistribution layer formed between the metal wiring is characterized in that it further comprises.

In addition, the redistribution layer is characterized in that consisting of a single layer or multiple layers.

The chip may be mounted in a wire bonding method or a flip chip bonding method.

In addition, the external connection member is characterized in that the solder ball.

In addition, a wafer level package according to a second embodiment of the present invention for achieving the above object is a chip; A mold protecting the chip; A conductive adhesive formed under the chip; And an external connection member electrically connected to a lower portion of the conductive adhesive.

Here, the redistribution layer formed between the conductive adhesive is characterized in that it further comprises.

In addition, the redistribution layer is characterized in that consisting of a single layer or multiple layers.

In addition, it characterized in that it further comprises an underfill formed on both sides of the chip.

In addition, the conductive adhesive is characterized in that consisting of ACF (Anisotropic Conductive Film).

In addition, the external connection member is characterized in that the solder ball.

In addition, a method of manufacturing a wafer level package according to a first embodiment of the present invention for achieving the above object comprises the steps of: forming a release layer on a substrate; Forming a metal layer on the release layer; Mounting a chip on the metal layer; Forming a mold to protect the chip on the metal layer; Peeling the release layer and the substrate from the metal layer; Patterning the metal layer to form a metal wiring; And forming an external connection member under the metal wire to be electrically connected to the metal wire.

In addition, another method of manufacturing a wafer-level package according to a first embodiment of the present invention for achieving the above object comprises the steps of: forming a release layer on a substrate; Forming a metal layer on the release layer; Patterning the metal layer to form a metal wiring; Mounting a chip on the metal wiring; Forming a mold on the metal wiring to protect the chip; Peeling the release layer and the substrate from the metal wiring; And forming an external connection member under the metal wire to be electrically connected to the metal wire.

Here, the substrate is characterized in that it is made of any one selected from the group consisting of glass, crystalline, polymer, ceramic, and metal.

In addition, the release layer is characterized in that consisting of an adhesive (adhesive) or tape (tape), the release layer is characterized in that the peelable through any one selected from the group consisting of UV, laser, heat and chemical treatment. .

In addition, the metal layer is characterized in that formed by any one process selected from the group consisting of PVD, CVD and plating.

The chip may be mounted in a wire bonding method or a flip chip bonding method.

In addition, the mold is characterized in that formed by any one process selected from the group consisting of molding (spin coating), spin coating (lamination) and screen printing (screen printing).

In addition, the external connection member is characterized in that the solder ball.

The method may further include forming a metal wiring by patterning the metal layer; Thereafter, forming a redistribution layer between the metal wires; characterized in that it further comprises.

In addition, the redistribution layer is characterized in that consisting of a single layer or multiple layers.

In addition, peeling the release layer and the substrate from the metal wiring; Thereafter, forming a redistribution layer between the metal wires; characterized in that it further comprises.

In addition, a method of manufacturing a wafer level package according to a second embodiment of the present invention for achieving the above object comprises the steps of: forming a release layer on a substrate; Mounting a chip on the release layer under the presence of a conductive adhesive; Forming a mold to protect the chip on the release layer; Peeling the release layer and the substrate from the mold; And forming an external connection member electrically connected to the conductive adhesive under the conductive adhesive.

Here, the step of mounting the chip on the release layer through the conductive adhesive; Thereafter, forming an underfill on both sides of the chip; characterized in that it further comprises.

In addition, peeling the release layer and the substrate from the mold; Thereafter, forming a redistribution layer between the conductive adhesive; characterized in that it further comprises.

As described above, according to the wafer level package and the manufacturing method thereof according to the present invention, the package can be thinned by manufacturing the package without the substrate. In addition, the price of the substrate, which occupies a large portion of the material cost of the package does not enter the manufacturing cost, there is an advantage that the package can be lowered.

Matters relating to the operational effects including the technical configuration for the above object of the wafer-level package and the manufacturing method thereof according to the present invention will be clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

Example  One

First, a wafer level package according to a first embodiment of the present invention will be described in detail with reference to FIG. 5.

5 is a cross-sectional view illustrating a wafer level package according to a first embodiment of the present invention.

As shown in FIG. 5, the wafer level package according to the first embodiment of the present invention includes a plurality of metal wires 120a spaced apart from each other by a predetermined interval, and a chip 130 mounted on the metal wires 120a. And a mold 150 formed on the metal wire 120a to protect the chip 130, and an external connection member 170 electrically connected to the lower part of the metal wire 120a.

A redistribution layer 160 may be further formed between the metal lines 120a. Here, the redistribution layer 160 may be made of a single layer or may be made of a multilayer.

As illustrated in the drawing, the chip 130 may be mounted in a wire bonding method using the wire 140 or in a flip chip bonding method (not shown).

At this time, the wire 140 is for the electrical connection between the chip 130 and the metal wiring 120a, which is generally made of gold (Au).

The external connection member 170 may be made of a solder ball (solder ball) or the like.

As described above, since the substrate is not included in the wafer level package, the overall thickness of the package can be significantly reduced. In addition, since the price of the substrate, which occupies a large portion of the material cost of the package, does not enter the manufacturing cost, there is an advantage of lowering the price of the package.

6 to 8 are cross-sectional views illustrating various modified examples of the wafer level package according to the first embodiment of the present invention.

First, as shown in FIG. 6, at least one chip 130 may be further formed on the chip 130, and as shown in FIG. 7, the metal on which the chip 130 is not formed. The passive element 135 may be further formed on the wiring 120a.

That is, in the wafer level package according to the present invention, although the chip 130 formed therein may be configured as a single chip, the function may be diversified by adding a multichip or a passive element.

In addition, as illustrated in FIG. 8, the mold 150 may extend to a space between the metal wires 120a. In this case, since the material of the mold 150 is formed between the metal wires 120a, the material of the mold 150 may be partially applied to the redistribution layer 160.

Next, a method of manufacturing a wafer level package according to the first embodiment of the present invention will be described in detail with reference to FIGS. 9 to 17.

9 to 17 are cross-sectional views sequentially illustrating a method of manufacturing a wafer level package according to a first embodiment of the present invention.

First, as shown in FIG. 9, the peeling layer 110 is formed on the board | substrate 100. FIG.

The substrate 100 may be made of glass, crystalline, polymer, ceramic, metal, or the like.

The release layer 110 may be formed of an adhesive or tape, which is preferably peelable through any one selected from the group consisting of UV, laser, heat, and chemical treatment.

Next, as shown in FIG. 10, the metal layer 120 is formed on the release layer 110. The metal layer 120 may be formed by a physical vapor deposition (PVD), a chemical vapor deposition (CVD), or a plating process.

Next, as shown in FIG. 11, the chip 130 is mounted on the metal layer 120. As illustrated in the drawing, the chip 130 may be mounted using a wire bonding method using the wire 140, or may be mounted using a flip chip bonding method (not shown).

Here, at least one chip 130 may be further formed on the chip 130 as illustrated in FIG. 6, or as shown in FIG. 135 may be further formed.

Next, as shown in FIG. 12, a mold 150 is formed on the metal layer 120 to protect the chip 130 and the wire 140. The mold 150 may be formed by a process such as molding, spin coating, lamination, or screen printing.

Thereafter, as shown in FIG. 13, the peeling layer 110 and the substrate 100 are peeled from the metal layer 120. Since the peeling layer 110 can be peeled off by UV, laser, heat, or chemical treatment as described above, the peeling layer 110 is removed from the metal layer 120 through such UV, laser, heat, or chemical treatment. ), The substrate 100 can be removed.

Next, as shown in FIG. 14, the metal layer 120 is patterned to form a metal wire 120a electrically connected to the chip 130 and the like.

Then, as shown in FIG. 15, a redistribution layer 160 is formed between the metal lines 120a. The redistribution layer 160 may be formed of a photoresist (PR) or the like. The redistribution layer 160 may be formed as a single layer or a multilayer, and the process of forming the redistribution layer 160 may be omitted.

Next, as illustrated in FIG. 16, an external connection member 170 is formed under the metal wire 120a to be electrically connected to the metal wire 120a. The external connection member 170 may be made of a solder ball or the like.

Next, as shown in FIG. 17, each package is cut | disconnected along the scribe line (not shown) of the completed package at the wafer level state.

As described above, the wafer level package manufactured according to the present invention, unlike a package containing a conventional substrate, because the substrate itself is not included in the finished package, it can significantly reduce the overall thickness of the package The price of the package can also be lowered.

Meanwhile, the wafer level package according to the first embodiment of the present invention described above may also be manufactured by the method described below.

Next, another method for manufacturing a wafer level package according to the first embodiment of the present invention will be described below with reference to FIGS. 18 to 22.

18 to 22 are process cross-sectional views sequentially shown to explain another method of manufacturing a wafer level package according to a first embodiment of the present invention.

First, as shown in FIGS. 9 and 10, the release layer 110 and the metal layer 120 are sequentially formed on the substrate 100. As described above, the substrate 100 may be made of glass, crystalline, polymer, ceramic, or metal. The release layer 110 may be formed of an adhesive or a tape that can be peeled through UV, laser, heat, or chemical treatment. In addition, the metal layer 120 may be formed by a PVD, CVD, or plating process.

18, the metal layer 120 is patterned to form a metal wiring 120a.

Next, as shown in FIG. 19, a redistribution layer 160 is formed between the metal lines 120a. The redistribution layer 160 may be formed of a single layer or multiple layers, and the process of forming the redistribution layer 160 may be omitted.

On the other hand, when the process of forming the redistribution layer 160 is omitted, the redistribution layer 160 peels the peeling layer 110 and the substrate 100 from the metal wiring 120a which is one of the processes described later. After the process (refer FIG. 22), it may form between the said metal wiring 120a. In this case, a package as shown in FIG. 8 described above, that is, a package 150 may be manufactured, in which a mold 150 is extended to a space between some metal wires 120a. In this case, the redistribution layer 160 may also be manufactured. May be omitted.

As described above, when the mold 150 is also formed between the metal wires 120a, the material of the mold 150 may be partially applied to the redistribution layer 160.

Next, as shown in FIG. 20, the chip 130 is mounted on the metal wiring 120a. As illustrated in the drawing, the chip 130 may be mounted using a wire bonding method using the wire 140, or may be mounted using a flip chip bonding method (not shown).

Next, as shown in FIG. 21, a mold 150 is formed on the metal wire 120a to protect the chip 130 and the wire 140. The mold 150 may be formed by a process such as molding, spin coating, lamination, or screen printing.

Then, as shown in FIG. 22, the peeling layer 110 and the board | substrate 100 are peeled from the said metal wiring 120a.

Then, as shown in the above 16 and 17, after forming the external connection member 170, for example, solder ball electrically connected to the metal wiring 120a below the metal wiring 120a (Fig. 16), each package is cut along the scribe line (not shown) of the completed package in the wafer level state (see FIG. 17).

As described above, according to another manufacturing method of the wafer level package according to the first embodiment of the present invention, a patterning process is performed immediately after forming the metal layer 120 to form the metal wiring 120a, and the metal wiring 120a. After the chip 130 is mounted on the top, the mold 150 is formed.

In this case, since the patterning process for forming the metal wiring 120a is performed before the mounting process of the chip 130, there is an advantage in that the position adjustment when the mounting of the chip 130 is performed.

In addition, after the redistribution layer 160 is formed between the metal wires 120a on the substrate 100, the chip 130 is mounted, the mold 150 is formed, and then the substrate 100 is removed. By manufacturing the furnace package, it is possible to enable a function check of the redistribution layer 160 like the substrate 100, thereby contributing to yield improvement.

Example  2

A second embodiment of the present invention will be described with reference to FIG. 23. However, the description of the same parts as those of the first embodiment of the configuration of the second embodiment will be omitted, and only the configuration that is different from the second embodiment will be described in detail.

23 is a cross-sectional view showing a wafer level package according to the second embodiment of the present invention.

As shown in FIG. 23, the wafer level package according to the second embodiment of the present invention may include a chip 130, a mold 150 protecting the chip 130, and a lower portion of the chip 130. It comprises a conductive adhesive 200, and an external connection member 170 that is electrically connected to the lower portion of the conductive adhesive 200.

A redistribution layer 160 is formed between the conductive adhesives 200. The redistribution layer 160 may be formed of a single layer or multiple layers. On the other hand, the redistribution layer 160 may not be formed.

In addition, underfills 210 are formed at both sides of the chip 130. The underfill 210 serves to supplement the adhesive strength of the chip 130, which may not be formed.

The conductive adhesive 200 is preferably made of an anisotropic conductive film (ACF).

The external connection member 170 may be made of a solder ball or the like.

The wafer level package according to the second embodiment of the present invention does not include the metal wiring 120a formed in the wafer level package according to the first embodiment, and the chip 130 is attached to the conductive adhesive 200. It is electrically connected to the external connection member 170 by.

That is, in the wafer level package according to the second embodiment of the present invention, even if there is no metal wiring 120a, the flip chip may be connected to the external connection member 170 by the conductive adhesive 200 under the chip 130. Only the wafer level package including the bonding chip 130 may be applied.

Since the wafer level package according to the second embodiment of the present invention as described above does not include a substrate as in the wafer level package according to the first embodiment of the present invention, the package can be reduced in thickness by reducing the thickness of the package. In addition, since the price of the substrate does not enter the manufacturing cost, the price of the package can be reduced.

In addition, in the second embodiment of the present invention, since the process of forming the metal wiring 120a is not required, the number of processes can be reduced.

A method of manufacturing a wafer level package according to a second embodiment of the present invention will be described in detail with reference to FIGS. 24 to 31. However, the description of the same parts as those of the first embodiment of the configuration of the second embodiment will be omitted, and only the configuration that is different from the second embodiment will be described in detail.

24 to 31 are process cross-sectional views sequentially illustrating a method of manufacturing a wafer level package according to a second embodiment of the present invention.

First, as shown in FIG. 24, the release layer 110 is formed on the substrate 100.

Then, as shown in FIG. 25, the chip 130 is mounted on the release layer 110 with the conductive adhesive 200 interposed therebetween. The conductive adhesive 200 is preferably made of an anisotropic conductive film (ACF).

Next, as shown in FIG. 26, underfills 210 are formed on both sides of the chip 130. The underfill 210 serves to complement the adhesive strength of the chip 130, and the process of forming the underfill 210 may be omitted.

Next, as shown in FIG. 27, a mold 150 that protects the chip 130 is formed on the release layer 110.

Then, as shown in FIG. 28, the release layer 110 and the substrate 100 are peeled from the mold 150.

Next, as shown in FIG. 29, a redistribution layer 160 is formed between the conductive adhesives 200. The process of forming the redistribution layer 160 may be omitted.

Thereafter, as shown in FIG. 30, an external connection member 170, for example, a solder ball, is electrically formed at the lower portion of the conductive adhesive 200 to be electrically connected to the conductive adhesive 200.

Next, as shown in FIG. 31, each package is cut | disconnected along the scribe line (not shown) of the package completed in the wafer level state.

As described above, since the wafer level package manufactured according to the second embodiment of the present invention does not include a substrate as in the wafer level package according to the first embodiment, the package can be made thinner and lower in cost.

In addition, the manufacturing method of the wafer level package according to the second embodiment of the present invention is applicable only to the package of the flip chip bonding method using the conductive adhesive 200, the wafer level according to the first embodiment of the present invention. The metal layer 120 forming process and the patterning process of the metal layer 120 in the package manufacturing method may be omitted, thereby reducing the overall number of processes.

Preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and various substitutions, modifications, and changes within the scope without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It will be possible, but such substitutions, changes and the like should be regarded as belonging to the following claims.

1 to 4 are sectional views sequentially shown to explain a method of manufacturing a wafer level package according to the prior art.

Fig. 5 is a sectional view showing a wafer level package according to the first embodiment of the present invention.

6 through 8 are cross-sectional views illustrating various modifications of the wafer level package according to the first embodiment of the present invention.

9 to 17 are process cross-sectional views sequentially shown to explain a method of manufacturing a wafer level package according to a first embodiment of the present invention.

18 to 22 are cross-sectional views sequentially showing to explain another method of manufacturing a wafer level package according to the first embodiment of the present invention.

Fig. 23 is a sectional view showing a wafer level package according to the second embodiment of the present invention.

24 to 31 are process sectional views sequentially shown to explain a method of manufacturing a wafer level package according to a second embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: substrate 110: release layer

120: metal layer 120a: metal wiring

130: chip 140: wire

150: mold 160: redistribution layer

170: external connection member 200: conductive adhesive

210: Underfill

Claims (29)

A plurality of metal wires spaced at a predetermined interval; A chip mounted on the metal wiring; A mold formed on the metal wiring to protect the chip; And An external connection member electrically connected to a lower portion of the metal wire; Wafer level package comprising a. The method of claim 1, And at least one chip formed on the chip. The method of claim 1, And a passive element formed on the metal line where the chip is not formed. The method of claim 1, And the mold extends to a space between the metal lines. The method of claim 1, And a redistribution layer formed between the metal lines. The method of claim 5, The redistribution layer is a wafer level package, characterized in that consisting of a single layer or multiple layers. The method of claim 1, The chip is a wafer-level package, characterized in that mounted on the wire bonding method or flip chip bonding method. The method of claim 1, The external connection member is a wafer level package, characterized in that the solder ball. chip; A mold protecting the chip; A conductive adhesive formed under the chip; And An external connection member electrically connected to a lower portion of the conductive adhesive; Wafer level package comprising a. The method of claim 9, And a redistribution layer formed between the conductive adhesives. The method of claim 10, The redistribution layer is a wafer level package, characterized in that consisting of a single layer or multiple layers. The method of claim 9, Wafer level package further comprises an underfill formed on both sides of the chip. The method of claim 9, The conductive adhesive is a wafer-level package, characterized in that made of an anisotropic conductive film (ACF). The method of claim 9, The external connection member is a wafer level package, characterized in that the solder ball. Forming a release layer on the substrate; Forming a metal layer on the release layer; Mounting a chip on the metal layer; Forming a mold to protect the chip on the metal layer; Peeling the release layer and the substrate from the metal layer; Patterning the metal layer to form a metal wiring; And Forming an external connection member under the metal wire to be electrically connected to the metal wire; Method of manufacturing a wafer level package comprising a. Forming a release layer on the substrate; Forming a metal layer on the release layer; Patterning the metal layer to form a metal wiring; Mounting a chip on the metal wiring; Forming a mold on the metal wiring to protect the chip; Peeling the release layer and the substrate from the metal wiring; And Forming an external connection member under the metal wire to be electrically connected to the metal wire; Method of manufacturing a wafer level package comprising a. The method according to claim 15 or 16, The substrate is a method of manufacturing a wafer-level package, characterized in that made of any one selected from the group consisting of glass, crystalline, polymer, ceramic and metal. The method according to claim 15 or 16, The release layer is a wafer level package manufacturing method, characterized in that consisting of an adhesive (adhesive) or tape (tape). The method of claim 18, And the release layer is peelable through any one selected from the group consisting of UV, laser, heat, and chemical treatments. The method according to claim 15 or 16, And the metal layer is formed by any one process selected from the group consisting of PVD, CVD and plating. The method according to claim 15 or 16, The chip manufacturing method of the wafer level package, characterized in that mounted in the wire bonding method or flip chip bonding method. The method according to claim 15 or 16, And the mold is formed by any one process selected from the group consisting of molding, spin coating, lamination, and screen printing. The method according to claim 15 or 16, The external connection member is a manufacturing method of the wafer level package, characterized in that the solder ball. The method according to claim 15 or 16, Patterning the metal layer to form a metal wiring; Since the Forming a redistribution layer between the metal wires; and manufacturing a wafer level package. The method of claim 24, The redistribution layer is a manufacturing method of the wafer level package, characterized in that consisting of a single layer or multiple layers. The method of claim 16, Peeling the release layer and the substrate from the metal wiring; Since the Forming a redistribution layer between the metal wires; and manufacturing a wafer level package. Forming a release layer on the substrate; Mounting a chip on the release layer under the presence of a conductive adhesive; Forming a mold to protect the chip on the release layer; Peeling the release layer and the substrate from the mold; And Forming an external connection member electrically connected to the conductive adhesive under the conductive adhesive; Method of manufacturing a wafer level package comprising a. The method of claim 27, Mounting a chip on the release layer under the presence of a conductive adhesive; Since the Forming an underfill on both sides of the chip; The manufacturing method of the wafer level package further comprising. The method of claim 27, Peeling the release layer and the substrate from the mold; Since the Forming a redistribution layer between the conductive adhesives;

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