CN110660725A - 具有可控间隙的扇出封装件 - Google Patents

具有可控间隙的扇出封装件 Download PDF

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Publication number
CN110660725A
CN110660725A CN201910023923.1A CN201910023923A CN110660725A CN 110660725 A CN110660725 A CN 110660725A CN 201910023923 A CN201910023923 A CN 201910023923A CN 110660725 A CN110660725 A CN 110660725A
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China
Prior art keywords
dielectric layer
metal
forming
interposer
interconnect structure
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CN201910023923.1A
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CN110660725B (zh
Inventor
蔡柏豪
翁得期
周孟纬
林孟良
庄博尧
郑心圃
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

方法包括形成中介层，形成中介层包括形成刚性介电层；以及去除部分刚性介电层。该方法还包括将封装组件接合至互连结构，以及将中介层接合至互连结构。中介层中的间隔件具有接触封装组件的顶面的底面，并且间隔件包括选自由金属部件、刚性介电层和它们的组合组成的组中的部件。对互连结构实施管芯锯切。本发明实施例涉及具有可控间隙的扇出封装件。

Description

具有可控间隙的扇出封装件
技术领域
本发明实施例涉及具有可控间隙的扇出封装件。
背景技术
随着半导体技术的进步，半导体芯片/管芯变得越来越小。同时，更多功能需要集成在半导体管芯内。因此，半导体管芯需要将越来越多的I/O焊盘封装至更小的区内，并且I/O焊盘的密度随着时间迅速提升。因此，半导体管芯的封装变得更加困难，这不利地影响了封装的良率。
传统的封装技术可以分为两类。在第一类中，晶圆上的管芯在它们被锯切之前封装。这种封装技术具有一些有利特征，诸如更大的生产量和更低的成本。此外，需要较少的底部填充物或模塑料。然而，这种封装技术也具有缺陷。由于管芯的尺寸变得越来越小，并且相应的封装件仅可以是扇入型封装件，其中，每个管芯的I/O焊盘限制于相应的管芯的表面正上方的区域。由于管芯的面积有限，I/O焊盘的数量由于I/O焊盘的间距的限制而受到限制。如果焊盘的间距减小，则可能发生焊料桥接。此外，焊球必须具有特定的尺寸，这进而限制了可以封装在管芯表面上的焊球的数量。
在另一类封装中，在封装管芯之前从晶圆锯切管芯。该封装技术的有利特征是可能形成扇出封装件，这意味着管芯上的I/O焊盘可以分布至比管芯更大的区域，并且因此可以增加封装在管芯的表面上的I/O焊盘的数量。该封装技术的另一有利特征是封装“已知良好管芯”，以及丢弃缺陷管芯，并且因此不会在缺陷管芯上浪费成本和精力。扇出封装件经受翘曲。这导致扇出封装件难以接合至封装衬底，并且相应的焊料连接可能失效。
发明内容
根据本发明的一些实施例，提供了一种形成封装件的方法，包括：形成中介层，包括：形成刚性介电层；以及去除所述刚性介电层的部分；将封装组件接合至互连结构；将所述中介层接合至所述互连结构，其中，所述中介层中的间隔件具有接触所述封装组件的顶面的底面，并且所述间隔件包括选自由金属部件、所述刚性介电层和它们的组合组成的组中的部件；以及对所述互连结构实施管芯锯切。
根据本发明的另一些实施例，还提供了一种形成封装件的方法，包括：形成中介层，包括：在第一载体上方镀金属间隔件；形成介电层以将所述金属间隔件嵌入在所述介电层内；在所述介电层上方形成衬底；形成穿透所述衬底的通孔；在所述通孔上方形成电连接至所述通孔的多个第一再分布线；去除所述第一载体以露出所述介电层；以及图案化所述介电层以去除所述介电层的第一部分，其中，所述介电层的第二部分保留；在第二载体上方形成互连结构；将封装组件接合至所述互连结构；以及将所述中介层接合至所述互连结构，其中，所述金属间隔件和所述介电层的第二部分将所述封装组件与所述衬底间隔开。
根据本发明的又一些实施例，还提供了一种封装件，包括：互连结构，包括接合焊盘；封装组件，位于所述互连结构上方并且接合至所述互连结构；中介层，位于所述互连结构上方并且接合至所述互连结构，所述中介层包括：金属部件，覆盖所述封装组件；刚性介电层，将所述金属部件密封在所述刚性介电层中；再分布线，位于所述刚性介电层上方；以及导电部件，接合至所述互连结构，其中，所述导电部件电连接至所述互连结构中的接合焊盘；以及密封剂，接触所述刚性介电层的侧壁和所述封装组件的顶面。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图11A示出了根据一些实施例的中介层的形成中的中间阶段的截面图。
图11B、图11C和图11D示出了根据一些实施例的中介层的截面图。
图12至图19A示出了根据一些实施例的包括中介层和扇出封装件的封装件的形成中的中间阶段的截面图。
图19B、图19C、图19D和图19E示出了根据一些实施例的封装件的截面图。
图20至图22示出了根据一些实施例的包括中介层和扇出封装件的封装件的形成中的中间阶段的截面图。
图23A、图23B、图23C和图23D示出了根据一些实施例的金属间隔件的顶视图。
图24和图25示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据各个实施例提供了包括中介层和扇出封装件的封装件及其形成方法。根据一些实施例示出了形成封装件的中间阶段。讨论了一些实施例的一些变化。贯穿各个视图和示例性实施例，相同的参考标号用于指定相同的元件。根据本发明的一些实施例，中介层被构造为包括金属间隔件和/或刚性介电层，并且中介层的主体由金属间隔件和/或刚性介电层构成。然后，图案化刚性介电层。将中介层接合至扇出封装件，其中，金属间隔件和/或刚性介电层用于限定中介层和封装件之间的相隔距离。
图1至图11A示出了根据一些实施例的中介层的形成中的中间阶段的截面图。如图24所示的工艺流程300也示意性地示出了图1至图11A所示的步骤。
图1示出了载体20和形成在载体20上的离型膜22。载体20可以是玻璃载体、陶瓷载体等。载体20可以具有圆形的顶视图形状并且可以具有硅晶圆的尺寸。例如，载体20可以具有8英寸的直径、12英寸的直径等。离型膜22可以由基于聚合物的材料(诸如光热转换(LTHC)材料)形成，离型膜22可以与载体20一起从将在随后步骤中形成的上面的结构去除。可以将离型膜22涂覆到载体20上。
在离型膜22上形成金属晶种层24。根据本发明的一些实施例，金属晶种层24包括钛层和位于钛层上方的铜层。晶种层也可以是单层，其可以是铜层。可以使用例如物理汽相沉积(PVD)形成金属晶种层24。
在金属晶种层24上方形成镀掩模26，并且然后例如通过光刻工艺图案化镀掩模26。根据本发明的一些实施例，镀掩模26由光刻胶形成。在镀掩模26中形成开口28，其中，金属晶种层24具有暴露于开口28的一些部分。
参照图2，实施镀工艺以将金属材料镀在金属晶种层24的暴露部分上以形成金属部件30，在整个说明书中，金属部件30称为金属间隔件30。相应的工艺示出为图24所示的工艺流程中的工艺302。镀的金属材料可以包括铜、铝、钨等。可以使用例如电化学镀、化学镀等实施镀。开口28将形成的金属间隔件30限制为具有期望的形状。然后，去除镀掩模26，在金属晶种层24上留下金属间隔件30。可以通过灰化工艺去除镀掩模26。因此暴露金属晶种层24。金属间隔件30的顶视图形状的一些实例在图23A、图23B、图23C和图23D中示出，并且将在随后的段落中讨论。
接下来，参照图3，形成刚性层32以将金属间隔件30嵌入在其内。相应的步骤示出为图24所示的工艺流程中的步骤304。根据本发明的一些实施例，刚性层32由诸如聚合物的介电材料形成，在一些实施例中，该聚合物可以是味之素构建膜(ABF)等。刚性层32这样的名称是因为其刚性足以抵抗上面的中介层60’的翘曲(例如，图19A)。形成工艺可以包括在金属间隔件30上层压预形成膜(诸如ABF膜)，并且通过加热和加压使膜热定形。然后，实施诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺以使金属间隔件30和刚性层32的顶面齐平。因此，金属间隔件30嵌入内部并且由刚性层32围绕，其中，金属间隔件30的顶面与刚性层32的顶面共面。根据其它实施例，刚性层32的形成包括分配诸如聚合物的可流动材料，固化可流动材料，并且实施平坦化工艺。根据又其它实施例，刚性层32的形成包括沉积诸如氧化硅、硅、氮化物等的无机材料，并且然后实施平坦化。
图4示出了金属焊盘34A的形成。相应的工艺示出为图24所示的工艺流程中的工艺306。根据本发明的一些实施例，通过镀形成金属焊盘34A。形成可以包括形成金属晶种层，形成和图案化镀掩模(诸如光刻胶，未示出)，在镀掩模的开口中镀金属焊盘34A，去除镀掩模，以及蚀刻金属晶种层的先前由镀掩模覆盖的部分。根据其它实施例，跳过金属晶种层的形成，其中，将金属焊盘34A镀在镀掩模中而不使用金属晶种层。金属晶种层(如果形成的话)可以由铜层、包括钛层和位于钛层上方的铜层的复合层等形成。
根据本发明的一些实施例，在形成金属焊盘34A的同时形成金属焊盘34B，并且金属焊盘34B与金属焊盘34A共享相同的形成工艺。相应的工艺也示出为图24所示的工艺流程中的工艺306。根据本发明的其它实施例，没有形成金属焊盘34B。因此，金属焊盘34B示出为虚线以指示其可以形成或可以不形成。金属焊盘34A和34B单独和统称为金属焊盘34。金属焊盘34B可以不用于电连接，并且可选地称为金属板以区分用于电连接的金属焊盘34A。
图5示出了衬底36的形成(或粘合)和金属箔38的层压。相应的工艺示出为图24所示的工艺流程中的工艺308。根据本发明的一些实施例，通过在金属焊盘34上层压诸如预浸料膜的介电膜来形成衬底36。根据可选实施例，通过在金属焊盘34上涂覆诸如聚合物的可流动介电材料，并且然后固化可流动介电材料来形成衬底36。根据又其它实施例，通过沉积(诸如使用化学汽相沉积方法)介电材料或通过粘合膜(未示出)粘合介电板(诸如氧化硅板、氮化硅板等)形成衬底36。因此，粘合膜将金属焊盘34嵌入在衬底36内，并且使其顶面接触衬底36。衬底36中可以包括纤维。根据又其它实施例，通过沉积半导体材料(诸如硅)或通过粘合膜(未示出)粘合半导体板(诸如硅衬底)来形成衬底36。金属箔38可以由铜、铝或其它类似金属材料形成。
图6示出了穿透衬底36和金属箔38的开口40的形成。相应的工艺示出为图24所示的工艺流程中的工艺310。形成方法包括激光钻孔、蚀刻等。因此，金属焊盘34A通过开口40暴露。另一方面，金属板34B由衬底36和金属箔38覆盖，并且不暴露。
然后例如在去污工艺中清洁如图6所示的结构，以去除在先前工艺中产生的副产物和残留物。如图7所示，然后实施镀工艺以在衬底36中形成通孔42。相应的工艺示出为图24所示的工艺流程中的工艺312。根据衬底36由诸如硅的半导体材料形成的一些实施例，隔离层可以形成为环绕通孔42以使通孔42与衬底36电绝缘。也实施图案化工艺以形成金属焊盘44，其可以包括镀金属材料和可能的金属箔38的一些部分。
参照图8，在金属焊盘44和衬底36上方形成介电层46。介电层46可以使用有机材料形成，有机材料可以选自聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等。可选地，介电层46可以包括非有机介电材料，诸如氧化硅、氮化硅、碳化硅、氮氧化硅等。在介电层46中形成开口(由再分布线(RDL)48占据)以暴露金属焊盘44。开口可以通过光刻工艺形成。
接下来，形成RDL 48以电连接至金属焊盘44和通孔42。相应的工艺示出为图24所示的工艺流程中的工艺314。RDL 48包括位于介电层46上方的金属迹线(金属线)以及延伸至介电层46中的开口内的通孔以电连接至金属焊盘44。根据本发明的一些实施例，RDL 48在镀工艺中形成，其中，每个RDL 48均包括晶种层和位于晶种层上方的镀金属材料。晶种层和镀材料可以由相同材料或不同材料形成。例如，晶种层可以由诸如钛、铜的金属形成，或可以包括钛层和位于钛层上方的铜层。镀金属材料可以包括铜或其它金属。
形成额外的介电层50以覆盖RDL 48和介电层46。介电层50可以由选自用于形成介电层46的相同候选材料的材料形成。然后在介电层50中形成开口52以暴露RDL 48的金属焊盘部分。可以通过激光钻孔、蚀刻等形成开口52。在整个说明书中，包括晶种层24、刚性层32、间隔件30和上面的部件的结构的部分组合称为中介层晶圆60。
然后，中介层晶圆60从载体20脱离。相应的工艺示出为图24所示的工艺流程中的工艺316。可以通过对离型膜22投射光(诸如激光束)来实施脱离，并且光穿透透明载体20。因此，离型膜22被分解，并且从载体20释放中介层晶圆60。然后，例如通过蚀刻去除金属晶种层24。图9中示出了产生的中介层晶圆60。
图10示出了刚性层32的图案化以露出金属焊盘34A。相应的工艺示出为图24所示的工艺流程中的工艺318。图案化可以包括蚀刻工艺，蚀刻工艺中包括光刻工艺。根据本发明的一些实施例，刚性层32包括位于金属板34B(如果形成的话)正下面的部分。剩余的刚性层32相对于金属板34B的尺寸可以具有不同的尺寸。例如，图10示出了边缘32A的位置的一些实例。如边缘32A表示的，刚性层32可以具有与金属板34B的相应边缘齐平的边缘。刚性层32也可以具有从金属板34B的边缘凹进的边缘，或可以具有延伸超出金属板34B的边缘的部分。
图11A示出了继续形成的中介层晶圆60。根据一些实施例，形成金属柱62以连接至金属焊盘34A。相应的工艺示出为图24所示的工艺流程中的工艺320。形成工艺包括上下翻转中介层晶圆60，在中介层晶圆60上方形成图案化的镀掩模(诸如光刻胶，未示出)，镀金属柱62，并且去除镀掩模。也可以使用镀掩模将焊料区域64镀在金属柱62上。可以实施回流工艺以回流焊料区域64。在形成中介层晶圆60之后，可以实施分割工艺以锯切穿过中介层晶圆60，以形成多个相同的中介层60’。
图11B示出了根据可选实施例的中介层60’的截面图。如图11B所示的中介层60’与图11A所示的中介层60’类似，除了去除所有刚性层32(图9)，并且在金属间隔件30上形成焊料区域66之外。形成如图11B所示的中介层60’的工艺与图1至图11A所示的工艺类似，除了在刚性层32(图10)的图案化中，去除所有刚性层32之外。可以实施额外的镀工艺以将焊料镀在金属间隔件30上，并且焊料区域66与焊料区域64一起回流。焊料区域64和66可以由无铅焊料形成。根据本发明的一些实施例，金属间隔件30是离散的金属柱，如图23A和图23B所示。
图11C示出了根据可选实施例的中介层60’的截面图。如图11C所示的中介层60’与图11A所示的中介层60’类似，除了没有形成如图11A所示的金属柱62和焊料区域64之外。相反，焊料区域68形成为中介层60’的一部分。可以通过在金属焊盘34A上放置焊球以及随后的回流工艺来形成焊料区域68。可选地，可以通过将焊料区域镀在金属焊盘34A上以及随后的回流工艺来形成焊料区域68。焊料区域68也可以由无铅焊料形成。
图11D示出了根据可选实施例的中介层60’的截面图。如图11D所示的中介层60’与图11A所示的中介层60’类似，除了没有形成金属间隔件30之外。用于形成如图11D所示的中介层60’的工艺与图1至图11A所示的工艺类似，除了跳过用于形成金属间隔件30的步骤(如图1和图2所示的步骤)之外，而实施图3至图10和图11C中示出的步骤。
中介层60’(图11A、图11B、图11C和图11D)的位于刚性层32上方的部分具有厚度T1(在图11A中标记)，并且刚性层32具有厚度T2。根据本发明的一些实施例，厚度T2小于厚度T1的约1/3。比率T2/T1也可以在约1/5和约1/3之间的范围内。厚度T1可以在约50nm和约300nm之间的范围内。金属间隔件30的宽度W5可以在约20μm和约300μm之间的范围内。金属柱62的宽度W6可以在约50μm和约300μm之间的范围内。
图12至图19A示出了根据一些实施例的InFO封装件的形成以及扇出封装件与中介层的集成中的中间阶段的截面图。如图25所示的工艺流程400也示意性地反映了图12至图19A所示的工艺流程。
图12示出了载体120和形成在载体120上的离型膜122。载体120可以是玻璃载体、硅晶圆、有机载体等。离型膜122可以由诸如LTHC的基于聚合物的材料形成。在离型膜122上形成介电层124。根据本发明的一些实施例，介电层124由聚合物形成，该聚合物可以是诸如PBO、聚酰亚胺、BCB等的光敏材料。
在介电层124上方形成RDL 126。相应的工艺示出为图25所示的工艺流程中的工艺402。RDL 126的形成可以包括在介电层124上方形成晶种层(未示出)，在晶种层上方形成诸如光刻胶的图案化的镀掩模(未示出)，并且然后将RDL 126镀在暴露的晶种层上。然后去除图案化的镀掩模和晶种层的由图案化的镀掩模覆盖的部分，留下如图12中的RDL 126。根据本发明的一些实施例，晶种层包括铜层或包括钛层和位于钛层上方的铜层的复合层。可以使用例如PVD形成晶种层。可以使用例如化学镀来实施镀。
进一步参照图12，在RDL 126上形成介电层128。介电层128的底面与RDL 126和介电层124的顶面接触。根据本发明的一些实施例，介电层层128由聚合物形成，该聚合物可以是诸如PBO、聚酰亚胺、BCB等的光敏材料。然后图案化介电层128以在介电层128中形成开口130。RDL 126的一些部分通过介电层128中的开口130暴露。
接下来，参照图13，在RDL 126上方形成介电层132和RDL 134，其中，RDL 134电连接至RDL 126。RDL 134包括位于介电层128上方的金属迹线(金属线)和相应的介电层132。RDL 134也包括延伸至介电层128和相应的介电层132中的开口内的通孔。RDL 134也可以在镀工艺中形成，其中，RDL 134的每个均包括晶种层(未示出)和位于晶种层上方的镀金属材料。晶种层和镀材料可以由相同材料或不同材料形成。RDL 134可以包括金属或金属合金，包括铝、铜、钨等。
可以使用聚合物形成介电层132，该聚合物可以选自与介电层128的候选材料相同的候选材料的组。例如，介电层132可以由PBO、聚酰亚胺、BCB等形成。可选地，介电层132可以包括非有机介电材料，诸如氧化硅、氮化硅、碳化硅、氮氧化硅等。
图13进一步示出了接合焊盘136(包括136A和136B)的形成，其电连接至RDL 134。RDL 134、介电层132和接合焊盘136的形成示出为图25所示的工艺流程中的工艺404。接合焊盘136可以包括接合焊盘136A和可能的接合焊盘136B。接合焊盘136的形成可以采用与用于形成RDL 134的方法和材料类似的方法和材料。应当理解，虽然在一些实施例的示出的实例中，示出了两个RDL层134和相应的介电层，但是可以采用更少或更多的介电层和RDL层，这取决于布线要求。例如，可以存在单个RDL层或三个、四个或更多RDL层。在整个说明书中，图13中的离型膜122上方的部件组合称为互连结构140。
接下来，参照图14，将封装组件142接合至互连结构140。相应的工艺示出为图25所示的工艺流程中的工艺406。根据本发明的一些实施例，封装组件142是片上系统(SoC)管芯。根据可选实施例，封装组件142是中央处理单元(CPU)管芯、图形处理单元(GPU)管芯、微控制单元(MCU)管芯、输入-输出(IO)管芯、基带(BB)管芯或应用处理器(AP)管芯、射频前端(RFFE)管芯、电源管理IC(PMIC)管芯等。封装组件142也可以是其中包括器件管芯的封装件或管芯堆叠件。此外，封装组件142可以包括选自前述类型的不同类型的管芯。
封装组件142包括接合至接合焊盘136B的电连接件144。封装组件142还可以包括半导体衬底148，其可以是硅衬底。在封装组件142中形成集成电路器件146，集成电路器件146可以包括诸如晶体管和/或二极管的有源器件，以及诸如电容器、电阻器等的无源器件。可以通过焊料接合、金属至金属直接接合等来实施接合。在将封装组件142接合至互连结构140之后，将底部填充物150分配到封装组件142和互连结构140之间的间隙中，从而形成扇出封装件152。相应的工艺示出为图25所示的工艺流程中的工艺408。
接下来，如图15所示，将中介层60’与扇出封装件152对准。根据一些实施例，使用如图11A所示的中介层60’。将焊料区域64放置在金属焊盘136A上。然后实施回流工艺以将中介层60’接合至扇出封装件152，其中，焊料区域64将金属柱62连接至金属焊盘136A。图16中示出了产生的结构。相应的工艺示出为图25所示的工艺流程中的工艺410。金属柱62的底面可以低于刚性介电层32和金属间隔件30的底面。
在接合工艺之后，将密封剂154分配到中介层60’和扇出封装件152之间的间隙中。相应的工艺示出为图25所示的工艺流程中的工艺412。因此，形成封装件156。根据本发明的一些实施例，密封剂154包括模塑料，其可以使用传递模塑来施加。根据本发明的其它实施例，密封剂154包括底部填充物。
金属间隔件30和刚性层32的底部与封装组件142的顶面接触。金属间隔件30和刚性层32具有若干功能。在接合工艺中，金属间隔件30和刚性层32保持中介层60’和封装组件142之间的相隔距离，并且防止中介层60’太靠近封装组件142。同样，利用金属间隔件30和刚性层32，防止焊料区域64被压碎以彼此桥接。此外，由于金属间隔件30和刚性层32填充间隙的一些中心部分，在中介层60’和封装组件142之间不太可能形成空隙。通过消除空隙并且利用刚性金属间隔件30和刚性层32来保持相隔距离，减小了中介层60’的翘曲。
在随后的工艺中，封装件156从载体120脱离。相应的工艺示出为图25所示的工艺流程中的工艺414。可以通过对离型膜122投射光(诸如激光束)，并且光透过透明载体120来实施脱离。因此，离型膜122被分解，并且从载体120释放封装件156。因此露出介电层124。图17中示出了产生的封装件156。封装件156可以是复合晶圆。
图18示出了电连接件158的形成。根据本发明的一些实施例，例如，通过激光钻孔或蚀刻在介电层124中形成开口以露出RDL 126中的金属焊盘。然后形成电连接件158。电连接件158可以包括焊料区域、其上具有焊料层的金属柱等。
图19A示出了通过焊料区域160将(顶部)封装组件159接合至封装件156，从而形成封装件166。封装件166也称为叠层封装(PoP)结构。相应的工艺示出为图25所示的工艺流程中的工艺416。根据本发明的一些实施例，封装件159包括封装衬底161和器件管芯162，器件管芯162可以是诸如静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等的存储器管芯。根据本发明的一些实施例，底部填充物164设置在封装件159和下面的封装件156之间的间隙中，并且被固化。根据本发明的其它实施例，在封装件159和下面的封装件156之间没有设置底部填充物，并且间隙保持未被填充。可以实施分割工艺以将封装件156(其可以是复合晶圆(重建晶圆))锯切为多个封装件156’，其中，封装件159接合在封装件156’上。从而形成封装件166，其包括与封装件159接合的封装件156’。
根据本发明的一些实施例，刚性层32具有宽度W2，并且封装组件142具有宽度W3。根据本发明的一些实施例，宽度W2小于宽度W3。根据一些实施例，比率W2/W3可以在约0.5和约0.9之间的范围内。
图19B、图19C、图19D和图19E示出了根据本发明的一些实施例的封装件的截面图。除非另有说明，否则这些实施例中的组件的材料和形成方法与相同的组件基本相同，相同的组件在图1至图19A所示的实施例中由相同的参考标号表示。因此，可以在图1至图19A所示的实施例的讨论中发现关于图19B、图19C、图19D和图19E所示的组件的形成工艺和材料的细节。
图19B示出了根据可选实施例的封装件166的截面图。如图19B所示的封装件与图19A所示的封装件类似，除了使用图11B所示的中介层60’(未形成图11B所示的焊料区域66)之外。用于形成图19B中的封装件的工艺与图12至图19A所示的基本相同。由于去除了金属间隔件30周围的刚性层32，因此密封剂154填充为环绕金属间隔件30并且与金属间隔件30接触。
图19C示出了根据又一可选实施例的封装件166的截面图。如图19C所示的封装件与图19A所示的封装件类似，除了使用图11C所示的中介层60’之外。用于形成图19C中的封装件的工艺与图12至图19A所示的基本相同(除了中介层60’的不同之外)。
图19D示出了根据又一可选实施例的封装件166的截面图。如图19D所示的封装件与图19A所示的封装件类似，除了在封装组件142的背面上形成金属层170，并且焊料区域66形成为接合至金属层170之外。图20至图22示出了图19D中的封装件166的形成中的一些中间阶段的截面图，其在随后讨论的工艺中讨论。
图19E示出了根据又一可选实施例的封装件166的截面图。如图19E所示的封装件与图19A所示的封装件类似，除了使用如图11D所示的中介层60’，其中，没有形成金属间隔件30之外。
图23A、图23B、图23C和图23D示出了根据一些实施例的金属间隔件30的顶视图。图23A示出了根据一些实施例的包括多个离散片的金属间隔件30，其可以具有矩形顶视图形状。根据一些实施例，水平尺寸W1可以在约20μm和约300μm之间的范围内。金属间隔件30可以均匀地布置，例如，具有诸如阵列的可重复图案、蜂窝图案等。图23B所示的金属间隔件30与图23A所示的金属间隔件类似，除了金属间隔件30的顶视图形状为圆形之外。图23C示出了形成为栅格的金属间隔件30，该栅格包括连接在一起的水平带和垂直带以形成栅格。图23D示出了形成为细长并且为离散带的金属间隔件30。形成如图23A、图23B、图23C和图23D所示的金属间隔件30而不是大的固体金属板可以减小镀工艺中的图案负载效应而不影响它们的功能。
在图19A、图19B、图19C和图19D中，金属间隔件30、金属板34B和金属层170(图19D)可以电连接至封装组件142中的半导体衬底148。根据其它实施例，金属间隔件30、金属板34B和金属层170用于散热，并且不用于电连接至半导体衬底148。然而，这些部件的顶端在金属板34B的顶面和侧壁处终止，或如果没有形成金属板34B，则在金属间隔件30的顶面处终止。因此，金属间隔件30、金属板34B和金属层170(图19D)被配置为不允许电流流过。当在金属层170和衬底148之间使用粘合膜(如将在随后的段落中讨论的)时，粘合膜可以是导电的或电绝缘的。因此，当粘合膜电绝缘时，金属板34B和金属层170也可以是电浮置的。
图20至图22示出了如图19D所示的封装件的形成中的中间阶段的截面图。除非另有说明，否则这些实施例中的组件的材料和形成方法与相同的组件基本相同，相同的组件在图12至图19A所示的实施例中由相同的参考标号表示。
参照图20，这些实施例的初始步骤与图12至图14所示的基本相同，除了封装组件142在其背面(示出的顶面)处包括金属层170。图20中示出了产生的封装件152。根据本发明的一些实施例，金属层170与衬底148物理接触，衬底148可以是半导体衬底。根据本发明的一些实施例，金属层170通过粘合膜(未示出)附接至衬底148的背面(示出的顶面)。金属层170可以包括铜层、钛层、包括钛层和位于钛层上方的铜层的复合Ti/Cu层、复合TiN/Cu层、复合Ti/Cu/Ti层、复合Al/Ti/Ni/Ag层等。在封装组件142接合至互连结构140之前，金属层170预先形成为封装组件142的顶面层。例如，在从相应晶圆锯切封装组件142之前，可以在封装组件142上形成金属层170。因此，金属层170的所有边缘可以与半导体衬底148的相应边缘齐平。金属层170也可以是在封装组件142的整个顶面上延伸的毯式层。此外，金属层170可以通过金属箔层压、沉积(诸如使用PVD或CVD)、粘合(诸如通过粘合膜)等形成。金属层170可以具有在约0.3μm和约150μm之间的范围内的厚度。
接下来，参照图21，将图11B所示的中介层60’与封装件152对准。焊料区域64与金属焊盘136A对准并且放置在金属焊盘136A上。然后实施回流，从而回流焊料区域64以将金属焊盘136A连接至金属柱62。此外，回流焊料区域66以将金属间隔件30接合至金属层170。焊料区域66和金属间隔件30可以保持相隔距离，并且也具有向上消散封装组件142产生的热量的功能。此外，通过焊料区域66，防止中介层60’向上和向下翘曲，并且显著减小了产生的封装件中的翘曲。在与图17、图18和图19A所示的工艺步骤类似的随后的工艺步骤中，形成如图19D所示的封装件166。
在以上示出的实施例中，根据本发明的一些实施例讨论了一些工艺和部件。也可以包括其它部件和工艺。例如，可以包括测试结构以帮助三维(3D)封装件或3DIC器件的验证测试。测试结构可以包括例如在再分布层中或衬底上形成的测试焊盘，以允许3D封装件或3DIC的测试、探针和/或探针卡的使用等。验证测试可以对中间结构以及最终结构实施。此外，本文公开的结构和方法可以与包含已知良好管芯的中间验证的测试方法结合使用，以提高良率并且降低成本。
本发明的实施例具有一些有利特征。通过形成刚性层和/或金属间隔件，中介层与中介层下面的封装组件之间的相隔距离限定为具有期望值。因此，减小了产生的封装件的翘曲。
根据本发明的一些实施例，方法包括形成中介层，形成中介层包括形成刚性介电层；以及去除部分刚性介电层；将封装组件接合至互连结构；将中介层接合至互连结构，其中，中介层中的间隔件具有接触封装组件的顶面的底面，并且间隔件包括选自由金属部件、刚性介电层和它们的组合组成的组；以及对互连结构实施管芯锯切。在实施例中，该方法还包括在载体上形成互连结构，当互连结构位于载体上时，封装组件接合至互连结构。在实施例中，该方法还包括形成金属部件，其中刚性介电层形成为使金属部件嵌入在其内；以及实施平坦化工艺以使金属部件的表面与刚性介电层的表面齐平。在实施例中，在去除刚性介电层的部分时，去除整个刚性介电层。在实施例中，该方法还包括在金属部件上形成作为中介层的一部分的焊料区域，其中，在中介层接合至互连结构之后焊料区域接触封装组件。在实施例中，在去除刚性介电层的部分时，去除刚性介电层的第一部分，并且留下未去除的刚性介电层的第二部分。在实施例中，间隔件包括金属部件和焊料区域，封装组件包括器件管芯，器件管芯包括半导体衬底和位于半导体衬底上的金属层，并且焊料区域将金属部件连接至金属层。
根据本发明的一些实施例，方法包括形成中介层，形成中介层包括在第一载体上方镀金属间隔件；形成介电层以将金属间隔件嵌入在其内；在介电层上方形成衬底；形成穿透衬底的通孔；通孔上方形成电连接至通孔的多个第一再分布线；去除第一载体以露出介电层；以及图案化介电层以去除介电层的第一部分，其中，介电层的第二部分保留；在第二载体上方形成互连结构；将封装组件接合至互连结构；以及将中介层接合至互连结构，其中，金属间隔件和介电层的第二部分将封装组件与衬底间隔开。在实施例中，形成中介层还包括在金属间隔件上形成焊料区域。在实施例中，封装组件包括：半导体衬底；以及位于半导体衬底上方的毯式金属层，其中，当中介层接合至互连结构时，焊料区域同时接合至毯式金属层。在实施例中，该方法还包括在介电层上形成多个金属焊盘；以及在中介层上形成多个金属柱，其中，通孔和多个金属柱位于多个金属焊盘的相对表面上；以及形成多个焊料区域，多个焊料区域的每个均位于多个金属柱中的一个上。在实施例中，该方法还包括在介电层上形成多个金属焊盘；以及在中介层上形成多个焊料区域，其中，通孔和多个焊料区域位于多个金属焊盘的相对表面上。在实施例中，形成衬底包括层压膜。在实施例中，形成介电层以将金属间隔件嵌入在其内包括：在金属间隔件上层压介电膜；以及平坦化金属间隔件和介电膜。
根据本发明的一些实施例，封装件包括互连结构，该互连结构包括接合焊盘；位于互连结构上方并且接合至互连结构的封装组件；位于互连结构上方并且接合至互连结构的中介层，中介层包括与封装组件重叠的金属部件；其中密封金属部件的刚性介电层；位于刚性介电层上方的再分布线；以及接合至互连结构的导电部件，其中，导电部件电连接至互连结构中的接合焊盘；以及接触刚性介电层的侧壁和封装组件的顶面的密封剂。在实施例中，封装件还包括位于刚性介电层上方的衬底；位于金属部件和刚性介电层上方并且接触金属部件和刚性介电层的金属板，其中，金属板位于衬底中，并且具有与衬底的底面基本共面的底面。在实施例中，封装组件包括器件管芯，该器件管芯包括半导体衬底，其中，金属部件和刚性介电层与半导体衬底的顶面物理接触。在实施例中，中介层还包括：位于刚性介电层上方并且接触刚性介电层的衬底；以及位于衬底中的通孔，其中通孔将再分布线电连接至导电部件。在实施例中，刚性介电层包括味之素构建膜(ABF)。在实施例中，导电部件包括金属柱，其中，金属柱的底面在封装组件的顶面之下延伸。
根据本发明的一些实施例，提供了一种形成封装件的方法，包括：形成中介层，包括：形成刚性介电层；以及去除所述刚性介电层的部分；将封装组件接合至互连结构；将所述中介层接合至所述互连结构，其中，所述中介层中的间隔件具有接触所述封装组件的顶面的底面，并且所述间隔件包括选自由金属部件、所述刚性介电层和它们的组合组成的组中的部件；以及对所述互连结构实施管芯锯切。
在上述方法中，还包括：在载体上形成所述互连结构，当所述互连结构位于所述载体上时，所述封装组件接合至所述互连结构。
在上述方法中，还包括：形成所述金属部件，其中，所述刚性介电层形成为使所述金属部件嵌入在所述刚性介电层内；以及实施平坦化工艺以使所述金属部件的表面与所述刚性介电层的表面齐平。
在上述方法中，在去除所述刚性介电层的部分时，去除整个所述刚性介电层。
在上述方法中，还包括：在所述金属部件上形成作为所述中介层的一部分的焊料区域，其中，在所述中介层接合至所述互连结构之后，所述焊料区域接触所述封装组件。
在上述方法中，在去除所述刚性介电层的部分时，去除所述刚性介电层的第一部分，并且留下所述刚性介电层的第二部分不被去除。
在上述方法中，所述间隔件包括所述金属部件和焊料区域，所述封装组件包括器件管芯，所述器件管芯包括半导体衬底和位于所述半导体衬底上的金属层，并且所述焊料区域将所述金属部件连接至所述金属层。
根据本发明的另一些实施例，还提供了一种形成封装件的方法，包括：形成中介层，包括：在第一载体上方镀金属间隔件；形成介电层以将所述金属间隔件嵌入在所述介电层内；在所述介电层上方形成衬底；形成穿透所述衬底的通孔；在所述通孔上方形成电连接至所述通孔的多个第一再分布线；去除所述第一载体以露出所述介电层；以及图案化所述介电层以去除所述介电层的第一部分，其中，所述介电层的第二部分保留；在第二载体上方形成互连结构；将封装组件接合至所述互连结构；以及将所述中介层接合至所述互连结构，其中，所述金属间隔件和所述介电层的第二部分将所述封装组件与所述衬底间隔开。
在上述方法中，形成所述中介层还包括在所述金属间隔件上形成焊料区域。
在上述方法中，所述封装组件包括：半导体衬底；以及毯式金属层，位于所述半导体衬底上方，其中，当所述中介层接合至所述互连结构时，所述焊料区域同时接合至所述毯式金属层。
在上述方法中，还包括：在所述介电层上形成多个金属焊盘；以及在所述中介层上形成多个金属柱，其中，所述通孔和所述多个金属柱位于所述多个金属焊盘的相对表面上；以及形成多个焊料区域，所述多个焊料区域的每个均位于所述多个金属柱中的一个上。
在上述方法中，还包括：在所述介电层上形成多个金属焊盘；以及在所述中介层上形成多个焊料区域，其中，所述通孔和所述多个焊料区域位于所述多个金属焊盘的相对表面上。
在上述方法中，形成所述衬底包括层压膜。
在上述方法中，形成所述介电层以将所述金属间隔件嵌入在所述介电层内包括：在所述金属间隔件上层压介电膜；以及平坦化所述金属间隔件和所述介电膜。
根据本发明的又一些实施例，还提供了一种封装件，包括：互连结构，包括接合焊盘；封装组件，位于所述互连结构上方并且接合至所述互连结构；中介层，位于所述互连结构上方并且接合至所述互连结构，所述中介层包括：金属部件，覆盖所述封装组件；刚性介电层，将所述金属部件密封在所述刚性介电层中；再分布线，位于所述刚性介电层上方；以及导电部件，接合至所述互连结构，其中，所述导电部件电连接至所述互连结构中的接合焊盘；以及密封剂，接触所述刚性介电层的侧壁和所述封装组件的顶面。
在上述封装件中，还包括：衬底，位于所述刚性介电层上方；以及金属板，位于所述金属部件和所述刚性介电层上方并且接触所述金属部件和所述刚性介电层，其中，所述金属板位于所述衬底中，并且具有与所述衬底的底面共面的底面。
在上述封装件中，所述封装组件包括器件管芯，所述器件管芯包括半导体衬底，其中，所述金属部件和所述刚性介电层与所述半导体衬底的顶面物理接触。
在上述封装件中，所述中介层还包括：衬底，位于所述刚性介电层上方并且接触所述刚性介电层；以及通孔，位于所述衬底中，其中，所述通孔将所述再分布线电连接至所述导电部件。
在上述封装件中，所述刚性介电层包括味之素构建膜(ABF)。
在上述封装件中，所述导电部件包括金属柱，其中，所述金属柱的底面在所述封装组件的顶面之下延伸。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成封装件的方法，包括：
形成中介层，包括：
形成刚性介电层；以及
去除所述刚性介电层的部分；
将封装组件接合至互连结构；
将所述中介层接合至所述互连结构，其中，所述中介层中的间隔件具有接触所述封装组件的顶面的底面，并且所述间隔件包括选自由金属部件、所述刚性介电层和它们的组合组成的组中的部件；以及
对所述互连结构实施管芯锯切。
2.根据权利要求1所述的方法，还包括：在载体上形成所述互连结构，当所述互连结构位于所述载体上时，所述封装组件接合至所述互连结构。
3.根据权利要求1所述的方法，还包括：
形成所述金属部件，其中，所述刚性介电层形成为使所述金属部件嵌入在所述刚性介电层内；以及
实施平坦化工艺以使所述金属部件的表面与所述刚性介电层的表面齐平。
4.根据权利要求1所述的方法，其中，在去除所述刚性介电层的部分时，去除整个所述刚性介电层。
5.根据权利要求4所述的方法，还包括：在所述金属部件上形成作为所述中介层的一部分的焊料区域，其中，在所述中介层接合至所述互连结构之后，所述焊料区域接触所述封装组件。
6.根据权利要求1所述的方法，其中，在去除所述刚性介电层的部分时，去除所述刚性介电层的第一部分，并且留下所述刚性介电层的第二部分不被去除。
7.根据权利要求1所述的方法，其中，所述间隔件包括所述金属部件和焊料区域，所述封装组件包括器件管芯，所述器件管芯包括半导体衬底和位于所述半导体衬底上的金属层，并且所述焊料区域将所述金属部件连接至所述金属层。
8.一种形成封装件的方法，包括：
形成中介层，包括：
在第一载体上方镀金属间隔件；
形成介电层以将所述金属间隔件嵌入在所述介电层内；
在所述介电层上方形成衬底；
形成穿透所述衬底的通孔；
在所述通孔上方形成电连接至所述通孔的多个第一再分布线；
去除所述第一载体以露出所述介电层；以及
图案化所述介电层以去除所述介电层的第一部分，其中，所述介电层的第二部分保留；
在第二载体上方形成互连结构；
将封装组件接合至所述互连结构；以及
将所述中介层接合至所述互连结构，其中，所述金属间隔件和所述介电层的第二部分将所述封装组件与所述衬底间隔开。
9.根据权利要求8所述的方法，其中，形成所述中介层还包括在所述金属间隔件上形成焊料区域。
10.一种封装件，包括：
互连结构，包括接合焊盘；
封装组件，位于所述互连结构上方并且接合至所述互连结构；
中介层，位于所述互连结构上方并且接合至所述互连结构，所述中介层包括：
金属部件，覆盖所述封装组件；
刚性介电层，将所述金属部件密封在所述刚性介电层中；
再分布线，位于所述刚性介电层上方；以及
导电部件，接合至所述互连结构，其中，所述导电部件电连接至所述互连结构中的接合焊盘；以及
密封剂，接触所述刚性介电层的侧壁和所述封装组件的顶面。
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