WO2024060694A1

WO2024060694A1 - Chip package structure and manufacturing method therefor

Info

Publication number: WO2024060694A1
Application number: PCT/CN2023/099291
Authority: WO
Inventors: 陈彦亨; 林正忠; 杨进
Original assignee: 盛合晶微半导体(江阴)有限公司
Priority date: 2022-09-20
Filing date: 2023-06-09
Publication date: 2024-03-28
Also published as: CN115458501A

Abstract

The present invention provides a chip package structure and a manufacturing method therefor. According to the manufacturing method, an expensive organic substrate in the prior art is replaced with a combination structure of re-distribution layers and a pre-impregnated substrate, the re-distribution layers are used for realizing fine-pitch distribution, and then are bonded to the pre-impregnated substrate so as to perform relatively rough wiring connection. Compared with existing organic substrates, the combination structure has the remarkable advantage of low cost, and can be applicable to packaging specific chip products without high frequency or low delay. Moreover, a plurality of chip stacks formed by a plurality of chips and the re-distribution layers are synchronously bonded to the surface of the pre-impregnated substrate, such that the problem in the prior art of low manufacturing efficiency during one-by-one bonding is avoided, thereby effectively saving the manufacturing cost and improving the production efficiency.

Description

A chip packaging structure and its preparation method

Technical field

The present invention relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure and a preparation method thereof.

Background technique

IC packaging has developed rapidly in recent years, and flip-chip electronic packaging, as the mainstream packaging form, accounts for 60-70% of the IC packaging market. For high-end flip-chip packaging structures, such as CPUs for servers, AI, and HPC, multiple chips need to be integrated on an organic substrate. This chip packaging structure usually includes multiple chips, such as core chip (core die), IO chip (IO die), cache/SRAM chip (cache die), fabric die, etc. As shown in Figure 1, in a typical flip chip package, single or multiple chips 101 are directly bonded to a single organic substrate 100 to form a flip chip package, which usually requires fine pitch wiring, which requires very fine L/S, such as 15/15um or below 10/10um, therefore it is necessary to use a high-density interconnected organic substrate 100 to achieve signal transmission. Organic substrates for high-density interconnection usually include dielectric layers made of ABF and signal, GND, and power layers made of copper. For high-performance products, organic substrates usually have 8+2+8 layer stacks, or 12+2+12 layer stacks or even higher, and are made using advanced materials and complex manufacturing processes, which also leads to this Organic substrates for high-density interconnections are very expensive. At the same time, when the organic substrate is directly bonded to multiple chips, thermal compression bonding (TCB) is usually used to bond each chip to the organic substrate one by one, which results in low manufacturing efficiency.

Especially for some low-end servers/workstations, which have less stringent frequency or delay requirements, there is no need to use such expensive high-density interconnection organic substrates. Therefore, a new packaging structure needs to be proposed to replace this. An expensive organic substrate.

Contents of the invention

In view of the above shortcomings of the prior art, the purpose of the present invention is to provide a chip packaging structure and a preparation method thereof to solve the problems of expensive organic substrates and low manufacturing efficiency in the prior art.

In order to achieve the above object, the present invention provides a method for preparing a chip packaging structure. The preparation method includes the following steps:

S1: Provide a carrier board, on which a rewiring layer and a chip are formed in sequence;

S2: Remove the carrier board, divide the rewiring layer along the gap between adjacent chips, and form a chip stack by dividing the chips and rewiring layers connected up and down;

S3: Simultaneously bond a plurality of the chip stacks to the surface of a prepreg substrate. The prepreg substrate includes more than two layers of conductive plates and a prepreg layer sandwiched between adjacent conductive plates.

Preferably, the conductive board is a PCB board, including a core board and a metal layer located on the surface of the core board.

Preferably, the material of the prepreg layer is impregnated resin.

Preferably, the total number of layers of the conductive plate and prepreg layer in the prepreg substrate is 10 or more.

Preferably, the rewiring layer includes a wiring dielectric layer and a metal wiring layer located within the wiring dielectric layer.

The invention also provides a chip packaging structure, which includes:

Prepreg substrate, the prepreg substrate includes more than two layers of conductive plates and a prepreg layer sandwiched between adjacent conductive plates;

At least one chip stack is located on the prepreg substrate, and the chip stack includes rewiring layers and chips stacked from bottom to top.

Preferably, the material of the prepreg layer is impregnated resin.

As mentioned above, the present invention provides a chip packaging structure and a preparation method thereof. The preparation method replaces the expensive organic substrate in the prior art with a combined structure of a rewiring layer and a prepreg substrate. The rewiring layer is used to achieve fine Pitch routing and then bonding to prepreg substrate for rougher routing connections. This combined structure has significant advantages in low cost compared to existing organic substrates, and can be applied to specific chip product packaging that does not require high frequency or low latency. At the same time, multiple chip stacks formed by multiple chips and rewiring layers are simultaneously bonded to the surface of the prepreg substrate, which avoids the problem of low manufacturing efficiency when bonding one by one in the existing technology, and can effectively save manufacturing costs. and improve production efficiency.

Description of the drawings

Figure 1 shows a schematic structural diagram of an organic substrate in the prior art.

FIG. 2 shows a schematic structural diagram of forming a rewiring layer and a chip on a carrier board in the present invention.

Figure 3 shows a schematic structural diagram of the chip stack.

Figure 4 shows a schematic side view of the finally formed chip packaging structure.

Figure 5 shows a schematic structural diagram of the conductive plate.

Figure 6 shows a schematic top view of the finally formed chip packaging structure.

Component label description

101 Chip

201 Rewiring layer

211 Metal wiring layer

212 Wiring media layer

301 Carrier board

401 Prepreg substrate

410 conductive plate

420 Prepreg layer

411 metal layer

412 core board

413 metal layer

Detailed ways

The following illustrates the embodiments of the present invention through specific examples. Those skilled in the art can understand from this description Other advantages and effects of the present invention can be readily understood from the disclosure. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

When describing the embodiments of the present invention in detail, for convenience of explanation, the cross-sectional views showing the device structure are not partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual production.

For convenience of description, spatial relationship words such as "below", "below", "below", "below", "above", "on", etc. may be used herein to describe an element or element shown in the drawings. The relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientations depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between" means including both endpoint values.

In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, so the illustrations only show the components related to the present invention and are not based on the number, shape and number of components during actual implementation. Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complex.

Aiming at the shortcoming of expensive cost of high-density interconnected organic substrates in the prior art, the present invention uses prepreg substrates instead. The silicon die or chip is first attached to a substrate made by the fan-out RDL process for fine pitch wiring. The assembled substrate with the attached silicon mold/chip is then attached to a low-cost prepreg substrate with a multi-layer structure for rough electrical routing using standard flip-chip assembly processes. This stacked packaging structure formed using packaging methods is mainly targeted at applications that do not require the highest frequency or the lowest delay.

Embodiment 1

As shown in Figures 2-6, this embodiment provides a method for preparing a chip packaging structure, which includes the following steps:

S1: Provide a carrier board 301, on which the rewiring layer 201 and the chip 101 are sequentially formed, as shown in Figure 2;

S2: Remove the carrier board 301 and divide the rewiring layer 201 along the gap between adjacent chips 101. After division, the chips 101 and the rewiring layer 201 connected up and down form a chip stack, as shown in Figure 3 ;

S3: Simultaneously bond multiple chip stacks to the surface of a prepreg substrate 401. The prepreg substrate 401 includes more than two layers of conductive plates 410 and a prepreg layer 420 sandwiched between adjacent conductive plates 410. , as shown in Figure 4 and Figure 6.

Specifically, as shown in FIG. 5 , the conductive board 410 may be a PCB board. The PCB board usually includes a core board 412 and a metal layer 411 located on the surface of the core board 412 , where the material of the metal layer 411 is usually copper. The core board 412 is a hard plate with a specific thickness, which may be fiberglass material, to ensure that the PCB board has a certain rigidity. The PCB board may be a single-sided PCB or a double-sided PCB. The difference is that the metal layer is located on one side or both sides of the core board 412 . As an example, the conductive board 410 in FIG. 4 is a double-sided PCB, and the upper and lower surfaces of the core board 412 have metal layers 411 and 413 respectively.

The prepreg layer 420 is also called a semi-cured sheet or Prepreg, and its material is usually an impregnating resin. Impregnating resin is a type of resin that uses a cross-linked copolymer as a carrier adsorbent resin and is impregnated in a liquid extractant to absorb various liquid ion exchangers. When producing reinforced composite materials, it is used to impregnate various skeleton materials such as wood, fabric, carbon fiber or glass fiber. Resins of materials such as fibers (including epoxy and phenolic resins, etc.). In this embodiment, the prepreg layer 420 can be used as a bonding material and interlayer insulation between the conductive plates 410. During lamination, the resin material of the prepreg layer 420 melts, flows, and solidifies, bonding the layers of circuits together to form a reliable insulating layer. As an example, FIG. 4 shows a specific structure with two layers of conductive plates. In practice, the number of conductive plates can be increased as needed, and adjacent conductive plates can be connected using the prepreg layer 420. For example, the sum of the number of layers of the conductive plates 410 and the prepreg layer 420 in the prepreg substrate 401 can be more than 10 layers.

In step S3, a large-scale reflow soldering process can be used to simultaneously bond multiple chip stacks to the surface of the prepreg substrate 401 in a parallel manner. Compared with the existing thermocompression bonding (TCB) method, each chip stack is Each chip is bonded to the organic substrate one by one, which can effectively save manufacturing costs and improve production efficiency.

Specifically, the carrier 301 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate. In this embodiment, the carrier plate 301 is selected as a glass substrate, which has a low cost and is easy to form a temporary bonding adhesive (also called TB glue, temporary bonding adhesive) on its surface to bond the new substrate. The wiring layer 201 can also reduce the subsequent difficulty of peeling off the carrier board 301. When separation is required, the temporary bonding glue can be heated based on a laser to reduce its viscosity, so that the rewiring layer 201 and the carrier board 301 are separated from each other from the bonding layer 20 .

Specifically, the rewiring layer 201 includes a wiring dielectric layer 212 and a metal wiring layer 211 located in the wiring dielectric layer 212 . The material of the wiring dielectric layer 212 includes one or a combination of two or more from the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the metal wiring The material of layer 211 includes one or a combination of two or more from the group consisting of copper, aluminum, nickel, gold, silver and titanium. The material, number of layers and distribution morphology of the wiring dielectric layer 212 and the metal wiring layer 211 can be set according to the specific conditions of the semiconductor chip, and are not limited here. In this embodiment, 4-5 layers are preferred. The chip 101 may be one of a core chip (core die), an IO chip (IO die), a cache/SRAM chip (cache die), a fabric die (fabric die), or any combination thereof, which will not be discussed here. Many restrictions.

This embodiment replaces the organic substrate 100 in the prior art with a combined structure of the rewiring layer 201 and the prepreg substrate 401. The rewiring layer 201 is used to achieve fine pitch wiring, and is then combined with the prepreg substrate 401. 401 bonding for rougher wiring connections. This combined structure has significant advantages in low cost compared to existing organic substrates, and can be applied to specific chip product packaging that does not require high frequency or low latency. At the same time, the chip stack is synchronously bonded to the surface of the prepreg substrate, which avoids the problem of low manufacturing efficiency when bonding one by one in the prior art, and improves productivity.

Embodiment 2

This embodiment provides a chip packaging structure, as shown in Figures 4 to 6, which can be prepared by the preparation method in the above-mentioned embodiment 1, but is not limited to the above-mentioned preparation method. The chip packaging structure specifically includes:

Prepreg substrate 401, which includes two or more layers of conductive plates 410 and a prepreg layer 420 sandwiched between adjacent conductive plates 410;

At least one chip stack is located on the prepreg substrate 401. The chip stack includes a rewiring layer 201 and a chip 101 stacked from bottom to top.

Specifically, as shown in FIG. 5 , the conductive board 410 may be a PCB board. The PCB board usually includes a core board 412 and a metal layer 411 located on the surface of the core board 412 , where the material of the metal layer 411 is usually copper. The core board 412 is a hard plate with a specific thickness, which may be fiberglass material, to ensure that the PCB board has a certain rigidity. The PCB board can be a single The difference between the two-sided PCB and the double-sided PCB is that the metal layer is located on one side or both sides of the core board 412 . As an example, the conductive board 410 in FIG. 4 is a double-sided PCB, and the upper and lower surfaces of the core board 412 have metal layers 411 and 413 respectively.

The prepreg layer 420 is also called prepreg or prepreg, and its material is usually impregnated resin. Impregnation resin is a type of resin that uses a cross-linked copolymer as a carrier adsorption resin, impregnates it in a liquid extraction agent, and absorbs various liquid ion exchangers. When producing reinforced composite materials, resins (including epoxy and phenolic resins, etc.) used to impregnate various skeleton materials such as wood, fabric, carbon fiber or glass fiber. In this embodiment, the prepreg layer 420 can be used as a bonding material and interlayer insulation between the conductive plates 410 . During lamination, the resin material of the prepreg layer 420 melts, flows, and solidifies, bonding each layer of circuits together and forming a reliable insulation layer. As an example, FIG. 4 shows a specific structure with two layers of conductive plates. In practice, the number of conductive plates can be increased as needed, and the prepreg layer 420 can be used to connect adjacent conductive plates. For example, the total number of layers of the conductive plate 410 and the prepreg layer 420 in the prepreg substrate 401 may be 10 or more layers.

Specifically, the rewiring layer 201 includes a wiring dielectric layer 212 and a metal wiring layer 211 located in the wiring dielectric layer 212 . The material of the wiring dielectric layer 212 includes one or a combination of two or more from the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the metal wiring The material of layer 211 includes one or a combination of two or more from the group consisting of copper, aluminum, nickel, gold, silver and titanium. The material, number of layers and distribution morphology of the wiring dielectric layer 212 and the metal wiring layer 211 can be set according to the specific conditions of the semiconductor chip, and are not limited here. In this embodiment, 4-5 layers are preferred. The chip 101 may be one of a core chip (core die), an IO chip (IO die), a cache/SRAM chip (cache die), a fabric die (fabric die), or any combination thereof, which will not be explained here. Many restrictions.

In summary, the present invention provides a chip packaging structure and a preparation method thereof. The preparation method replaces the expensive organic substrate in the prior art with a combined structure of a rewiring layer and a prepreg substrate. The rewiring layer is used to realize Fine pitch routing is then bonded to a prepreg substrate for rougher routing connections. This combined structure has significant advantages in low cost compared to existing organic substrates, and can be applied to specific chip product packaging that does not require high frequency or low latency. At the same time, multiple chip stacks formed by multiple chips and rewiring layers are simultaneously bonded to the surface of the prepreg substrate, which avoids the problem of low manufacturing efficiency when bonding one by one in the existing technology, and can effectively save manufacturing costs. and improve production efficiency.

The above embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims

A method for preparing a chip packaging structure, characterized in that the preparation method includes the following steps:

S1: providing a carrier board, and sequentially forming a rewiring layer and a chip on the carrier board;

S2: Remove the carrier board, divide the rewiring layer along the gap between adjacent chips, and form a chip stack by dividing the chips and rewiring layers connected up and down;

S3: Simultaneously bond a plurality of the chip stacks to the surface of a prepreg substrate. The prepreg substrate includes more than two layers of conductive plates and a prepreg layer sandwiched between adjacent conductive plates.
The preparation method according to claim 1, characterized in that the conductive plate is a PCB board, including a core plate and a metal layer located on the surface of the core plate.
The preparation method according to claim 1, characterized in that the material of the prepreg layer is impregnated resin.
The preparation method according to claim 1, characterized in that the total number of layers of the conductive plate and the prepreg layer in the prepreg substrate is 10 or more.
The preparation method according to claim 1 is characterized in that the rewiring layer includes a wiring dielectric layer and a metal wiring layer located in the wiring dielectric layer.
A chip packaging structure, characterized in that the chip packaging structure includes:

Prepreg substrate, the prepreg substrate includes more than two layers of conductive plates and a prepreg layer sandwiched between adjacent conductive plates;

At least one chip stack is located on the prepreg substrate, and the chip stack includes rewiring layers and chips stacked from bottom to top.
The chip packaging structure according to claim 6, wherein the conductive plate is a PCB board, including a core board and a metal layer located on the surface of the core board.
The chip packaging structure according to claim 6, wherein the material of the prepreg layer is impregnated resin.
The chip packaging structure according to claim 6, wherein the total number of layers of the conductive plate and the prepreg layer in the prepreg substrate is 10 or more.
The chip packaging structure according to claim 6, wherein the rewiring layer includes a wiring dielectric layer and a metal wiring layer located in the wiring dielectric layer.