WO2024060694A1 - Chip package structure and manufacturing method therefor - Google Patents
Chip package structure and manufacturing method therefor Download PDFInfo
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- WO2024060694A1 WO2024060694A1 PCT/CN2023/099291 CN2023099291W WO2024060694A1 WO 2024060694 A1 WO2024060694 A1 WO 2024060694A1 CN 2023099291 W CN2023099291 W CN 2023099291W WO 2024060694 A1 WO2024060694 A1 WO 2024060694A1
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- chip
- prepreg
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- substrate
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- 238000004806 packaging method and process Methods 0.000 claims abstract description 30
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- 239000004744 fabric Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
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- 229910052759 nickel Inorganic materials 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
Definitions
- the present invention relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure and a preparation method thereof.
- IC packaging has developed rapidly in recent years, and flip-chip electronic packaging, as the mainstream packaging form, accounts for 60-70% of the IC packaging market.
- flip-chip electronic packaging As the mainstream packaging form, accounts for 60-70% of the IC packaging market.
- This chip packaging structure usually includes multiple chips, such as core chip (core die), IO chip (IO die), cache/SRAM chip (cache die), fabric die, etc.
- Organic substrates for high-density interconnection usually include dielectric layers made of ABF and signal, GND, and power layers made of copper.
- organic substrates usually have 8+2+8 layer stacks, or 12+2+12 layer stacks or even higher, and are made using advanced materials and complex manufacturing processes, which also leads to this Organic substrates for high-density interconnections are very expensive.
- thermal compression bonding TAB is usually used to bond each chip to the organic substrate one by one, which results in low manufacturing efficiency.
- the purpose of the present invention is to provide a chip packaging structure and a preparation method thereof to solve the problems of expensive organic substrates and low manufacturing efficiency in the prior art.
- the present invention provides a method for preparing a chip packaging structure.
- the preparation method includes the following steps:
- S1 Provide a carrier board, on which a rewiring layer and a chip are formed in sequence;
- S2 Remove the carrier board, divide the rewiring layer along the gap between adjacent chips, and form a chip stack by dividing the chips and rewiring layers connected up and down;
- the prepreg substrate includes more than two layers of conductive plates and a prepreg layer sandwiched between adjacent conductive plates.
- the conductive board is a PCB board, including a core board and a metal layer located on the surface of the core board.
- the material of the prepreg layer is impregnated resin.
- the total number of layers of the conductive plate and prepreg layer in the prepreg substrate is 10 or more.
- the rewiring layer includes a wiring dielectric layer and a metal wiring layer located within the wiring dielectric layer.
- the invention also provides a chip packaging structure, which includes:
- the prepreg substrate includes more than two layers of conductive plates and a prepreg layer sandwiched between adjacent conductive plates;
- At least one chip stack is located on the prepreg substrate, and the chip stack includes rewiring layers and chips stacked from bottom to top.
- the conductive board is a PCB board, including a core board and a metal layer located on the surface of the core board.
- the material of the prepreg layer is impregnated resin.
- the total number of layers of the conductive plate and prepreg layer in the prepreg substrate is 10 or more.
- the rewiring layer includes a wiring dielectric layer and a metal wiring layer located within the wiring dielectric layer.
- the present invention provides a chip packaging structure and a preparation method thereof.
- the preparation method replaces the expensive organic substrate in the prior art with a combined structure of a rewiring layer and a prepreg substrate.
- the rewiring layer is used to achieve fine Pitch routing and then bonding to prepreg substrate for rougher routing connections.
- This combined structure has significant advantages in low cost compared to existing organic substrates, and can be applied to specific chip product packaging that does not require high frequency or low latency.
- multiple chip stacks formed by multiple chips and rewiring layers are simultaneously bonded to the surface of the prepreg substrate, which avoids the problem of low manufacturing efficiency when bonding one by one in the existing technology, and can effectively save manufacturing costs. and improve production efficiency.
- Figure 1 shows a schematic structural diagram of an organic substrate in the prior art.
- FIG. 2 shows a schematic structural diagram of forming a rewiring layer and a chip on a carrier board in the present invention.
- Figure 3 shows a schematic structural diagram of the chip stack.
- Figure 4 shows a schematic side view of the finally formed chip packaging structure.
- Figure 5 shows a schematic structural diagram of the conductive plate.
- Figure 6 shows a schematic top view of the finally formed chip packaging structure.
- spatial relationship words such as “below”, “below”, “below”, “below”, “above”, “on”, etc. may be used herein to describe an element or element shown in the drawings.
- a layer when referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
- “between” means including both endpoint values.
- a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
- illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, so the illustrations only show the components related to the present invention and are not based on the number, shape and number of components during actual implementation. Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complex.
- the present invention uses prepreg substrates instead.
- the silicon die or chip is first attached to a substrate made by the fan-out RDL process for fine pitch wiring.
- the assembled substrate with the attached silicon mold/chip is then attached to a low-cost prepreg substrate with a multi-layer structure for rough electrical routing using standard flip-chip assembly processes.
- This stacked packaging structure formed using packaging methods is mainly targeted at applications that do not require the highest frequency or the lowest delay.
- this embodiment provides a method for preparing a chip packaging structure, which includes the following steps:
- S1 Provide a carrier board 301, on which the rewiring layer 201 and the chip 101 are sequentially formed, as shown in Figure 2;
- the prepreg substrate 401 includes more than two layers of conductive plates 410 and a prepreg layer 420 sandwiched between adjacent conductive plates 410. , as shown in Figure 4 and Figure 6.
- the conductive board 410 may be a PCB board.
- the PCB board usually includes a core board 412 and a metal layer 411 located on the surface of the core board 412 , where the material of the metal layer 411 is usually copper.
- the core board 412 is a hard plate with a specific thickness, which may be fiberglass material, to ensure that the PCB board has a certain rigidity.
- the PCB board may be a single-sided PCB or a double-sided PCB. The difference is that the metal layer is located on one side or both sides of the core board 412 .
- the conductive board 410 in FIG. 4 is a double-sided PCB, and the upper and lower surfaces of the core board 412 have metal layers 411 and 413 respectively.
- the prepreg layer 420 is also called a semi-cured sheet or Prepreg, and its material is usually an impregnating resin.
- Impregnating resin is a type of resin that uses a cross-linked copolymer as a carrier adsorbent resin and is impregnated in a liquid extractant to absorb various liquid ion exchangers. When producing reinforced composite materials, it is used to impregnate various skeleton materials such as wood, fabric, carbon fiber or glass fiber. Resins of materials such as fibers (including epoxy and phenolic resins, etc.).
- the prepreg layer 420 can be used as a bonding material and interlayer insulation between the conductive plates 410.
- FIG. 4 shows a specific structure with two layers of conductive plates.
- the number of conductive plates can be increased as needed, and adjacent conductive plates can be connected using the prepreg layer 420.
- the sum of the number of layers of the conductive plates 410 and the prepreg layer 420 in the prepreg substrate 401 can be more than 10 layers.
- step S3 a large-scale reflow soldering process can be used to simultaneously bond multiple chip stacks to the surface of the prepreg substrate 401 in a parallel manner.
- each chip stack is Each chip is bonded to the organic substrate one by one, which can effectively save manufacturing costs and improve production efficiency.
- the carrier 301 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate.
- the carrier plate 301 is selected as a glass substrate, which has a low cost and is easy to form a temporary bonding adhesive (also called TB glue, temporary bonding adhesive) on its surface to bond the new substrate.
- the wiring layer 201 can also reduce the subsequent difficulty of peeling off the carrier board 301.
- the temporary bonding glue can be heated based on a laser to reduce its viscosity, so that the rewiring layer 201 and the carrier board 301 are separated from each other from the bonding layer 20 .
- the rewiring layer 201 includes a wiring dielectric layer 212 and a metal wiring layer 211 located in the wiring dielectric layer 212 .
- the material of the wiring dielectric layer 212 includes one or a combination of two or more from the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the metal wiring
- the material of layer 211 includes one or a combination of two or more from the group consisting of copper, aluminum, nickel, gold, silver and titanium.
- the material, number of layers and distribution morphology of the wiring dielectric layer 212 and the metal wiring layer 211 can be set according to the specific conditions of the semiconductor chip, and are not limited here. In this embodiment, 4-5 layers are preferred.
- the chip 101 may be one of a core chip (core die), an IO chip (IO die), a cache/SRAM chip (cache die), a fabric die (fabric die), or any combination thereof, which will not be discussed here. Many restrictions.
- This embodiment replaces the organic substrate 100 in the prior art with a combined structure of the rewiring layer 201 and the prepreg substrate 401.
- the rewiring layer 201 is used to achieve fine pitch wiring, and is then combined with the prepreg substrate 401. 401 bonding for rougher wiring connections.
- This combined structure has significant advantages in low cost compared to existing organic substrates, and can be applied to specific chip product packaging that does not require high frequency or low latency.
- the chip stack is synchronously bonded to the surface of the prepreg substrate, which avoids the problem of low manufacturing efficiency when bonding one by one in the prior art, and improves productivity.
- This embodiment provides a chip packaging structure, as shown in Figures 4 to 6, which can be prepared by the preparation method in the above-mentioned embodiment 1, but is not limited to the above-mentioned preparation method.
- the chip packaging structure specifically includes:
- Prepreg substrate 401 which includes two or more layers of conductive plates 410 and a prepreg layer 420 sandwiched between adjacent conductive plates 410;
- At least one chip stack is located on the prepreg substrate 401.
- the chip stack includes a rewiring layer 201 and a chip 101 stacked from bottom to top.
- the conductive board 410 may be a PCB board.
- the PCB board usually includes a core board 412 and a metal layer 411 located on the surface of the core board 412 , where the material of the metal layer 411 is usually copper.
- the core board 412 is a hard plate with a specific thickness, which may be fiberglass material, to ensure that the PCB board has a certain rigidity.
- the PCB board can be a single The difference between the two-sided PCB and the double-sided PCB is that the metal layer is located on one side or both sides of the core board 412 .
- the conductive board 410 in FIG. 4 is a double-sided PCB, and the upper and lower surfaces of the core board 412 have metal layers 411 and 413 respectively.
- the prepreg layer 420 is also called prepreg or prepreg, and its material is usually impregnated resin.
- Impregnation resin is a type of resin that uses a cross-linked copolymer as a carrier adsorption resin, impregnates it in a liquid extraction agent, and absorbs various liquid ion exchangers.
- resins including epoxy and phenolic resins, etc.
- the prepreg layer 420 can be used as a bonding material and interlayer insulation between the conductive plates 410 .
- FIG. 4 shows a specific structure with two layers of conductive plates.
- the number of conductive plates can be increased as needed, and the prepreg layer 420 can be used to connect adjacent conductive plates.
- the total number of layers of the conductive plate 410 and the prepreg layer 420 in the prepreg substrate 401 may be 10 or more layers.
- the rewiring layer 201 includes a wiring dielectric layer 212 and a metal wiring layer 211 located in the wiring dielectric layer 212 .
- the material of the wiring dielectric layer 212 includes one or a combination of two or more from the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the metal wiring
- the material of layer 211 includes one or a combination of two or more from the group consisting of copper, aluminum, nickel, gold, silver and titanium.
- the material, number of layers and distribution morphology of the wiring dielectric layer 212 and the metal wiring layer 211 can be set according to the specific conditions of the semiconductor chip, and are not limited here. In this embodiment, 4-5 layers are preferred.
- the chip 101 may be one of a core chip (core die), an IO chip (IO die), a cache/SRAM chip (cache die), a fabric die (fabric die), or any combination thereof, which will not be explained here. Many restrictions.
- the present invention provides a chip packaging structure and a preparation method thereof.
- the preparation method replaces the expensive organic substrate in the prior art with a combined structure of a rewiring layer and a prepreg substrate.
- the rewiring layer is used to realize Fine pitch routing is then bonded to a prepreg substrate for rougher routing connections.
- This combined structure has significant advantages in low cost compared to existing organic substrates, and can be applied to specific chip product packaging that does not require high frequency or low latency.
- multiple chip stacks formed by multiple chips and rewiring layers are simultaneously bonded to the surface of the prepreg substrate, which avoids the problem of low manufacturing efficiency when bonding one by one in the existing technology, and can effectively save manufacturing costs. and improve production efficiency.
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Computer Hardware Design (AREA)
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Abstract
The present invention provides a chip package structure and a manufacturing method therefor. According to the manufacturing method, an expensive organic substrate in the prior art is replaced with a combination structure of re-distribution layers and a pre-impregnated substrate, the re-distribution layers are used for realizing fine-pitch distribution, and then are bonded to the pre-impregnated substrate so as to perform relatively rough wiring connection. Compared with existing organic substrates, the combination structure has the remarkable advantage of low cost, and can be applicable to packaging specific chip products without high frequency or low delay. Moreover, a plurality of chip stacks formed by a plurality of chips and the re-distribution layers are synchronously bonded to the surface of the pre-impregnated substrate, such that the problem in the prior art of low manufacturing efficiency during one-by-one bonding is avoided, thereby effectively saving the manufacturing cost and improving the production efficiency.
Description
本发明涉及半导体封装技术领域,特别是涉及一种芯片封装结构及其制备方法。The present invention relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure and a preparation method thereof.
IC封装近年来发展迅速,倒装芯片电子封装作为主流封装形式占据了IC封装市场的60-70%。对于高端的倒装芯片封装结构,例如用于服务器、AI和HPC的CPU,需要将多芯片集成在一个有机基板上。这种芯片封装结构通常包括多个芯片,例如核心芯片(core die)、IO芯片(IO die)、高速缓存/SRAM芯片(cache die)、结构芯片(fabric die)等。如图1所示,在典型的倒装芯片封装中,单个或多个芯片101直接键合至单个有机基板100上以形成倒装芯片封装,其通常需要精细间距布线,这就要求非常精细的L/S,如15/15um或10/10um以下,因此需要使用高密度互连的有机基板100以实现信号传输。高密度互连的有机基板通常包括由ABF制成的电介质层以及由铜制成的信号层、GND层、电源层。对于高性能产品,有机基板通常具有8+2+8层堆叠,或者具有12+2+12层堆叠甚至更高,且使用先进的材料和复杂的制造工艺制作而成,这也导致了这种高密度互连的有机基板造价非常昂贵。同时该有机基板与多个芯片直接键合时,通常采用热压键合(TCB)的方式将每个芯片逐一键合至有机基板,制造效率较低。IC packaging has developed rapidly in recent years, and flip-chip electronic packaging, as the mainstream packaging form, accounts for 60-70% of the IC packaging market. For high-end flip-chip packaging structures, such as CPUs for servers, AI, and HPC, multiple chips need to be integrated on an organic substrate. This chip packaging structure usually includes multiple chips, such as core chip (core die), IO chip (IO die), cache/SRAM chip (cache die), fabric die, etc. As shown in Figure 1, in a typical flip chip package, single or multiple chips 101 are directly bonded to a single organic substrate 100 to form a flip chip package, which usually requires fine pitch wiring, which requires very fine L/S, such as 15/15um or below 10/10um, therefore it is necessary to use a high-density interconnected organic substrate 100 to achieve signal transmission. Organic substrates for high-density interconnection usually include dielectric layers made of ABF and signal, GND, and power layers made of copper. For high-performance products, organic substrates usually have 8+2+8 layer stacks, or 12+2+12 layer stacks or even higher, and are made using advanced materials and complex manufacturing processes, which also leads to this Organic substrates for high-density interconnections are very expensive. At the same time, when the organic substrate is directly bonded to multiple chips, thermal compression bonding (TCB) is usually used to bond each chip to the organic substrate one by one, which results in low manufacturing efficiency.
尤其是针对某些低端服务器/工作站,其对于频率或延迟要求没有那么严格,不必要用到这种造价昂贵的高密度互连的有机基板,因此需要提出一种新的封装结构来替代这种造价昂贵的有机基板。Especially for some low-end servers/workstations, which have less stringent frequency or delay requirements, there is no need to use such expensive high-density interconnection organic substrates. Therefore, a new packaging structure needs to be proposed to replace this. An expensive organic substrate.
发明内容Contents of the invention
鉴于以上所述现有技术的缺点,本发明的目的在于提供一种芯片封装结构及其制备方法,用于解决现有技术中有机基板造价昂贵、制造效率低的问题。In view of the above shortcomings of the prior art, the purpose of the present invention is to provide a chip packaging structure and a preparation method thereof to solve the problems of expensive organic substrates and low manufacturing efficiency in the prior art.
为实现上述目的,本发明提供一种芯片封装结构的制备方法,所述制备方法包括如下步骤:In order to achieve the above object, the present invention provides a method for preparing a chip packaging structure. The preparation method includes the following steps:
S1:提供载板,在所述载板上依次形成重新布线层及芯片;S1: Provide a carrier board, on which a rewiring layer and a chip are formed in sequence;
S2:去除所述载板,沿相邻芯片之间的间隙对所述重新布线层进行分割,分割后上下相连的芯片及重新布线层形成芯片堆叠体;S2: Remove the carrier board, divide the rewiring layer along the gap between adjacent chips, and form a chip stack by dividing the chips and rewiring layers connected up and down;
S3:将多个所述芯片堆叠体同步键合至预浸基板表面,所述预浸基板包括2层以上的导电板及夹设于相邻导电板之间的预浸层。S3: Simultaneously bond a plurality of the chip stacks to the surface of a prepreg substrate. The prepreg substrate includes more than two layers of conductive plates and a prepreg layer sandwiched between adjacent conductive plates.
优选地,所述导电板为PCB板,包括芯板及位于所述芯板表面的金属层。Preferably, the conductive board is a PCB board, including a core board and a metal layer located on the surface of the core board.
优选地,所述预浸层的材料为浸渍树脂。Preferably, the material of the prepreg layer is impregnated resin.
优选地,所述预浸基板中所述导电板及预浸层的层数之和为10层以上。Preferably, the total number of layers of the conductive plate and prepreg layer in the prepreg substrate is 10 or more.
优选地,所述重新布线层包括布线介质层及位于所述布线介质层内的金属布线层。Preferably, the rewiring layer includes a wiring dielectric layer and a metal wiring layer located within the wiring dielectric layer.
本发明还提供一种芯片封装结构,所述芯片封装结构包括:
The invention also provides a chip packaging structure, which includes:
预浸基板,所述预浸基板包括2层以上的导电板及夹设于相邻导电板之间的预浸层;Prepreg substrate, the prepreg substrate includes more than two layers of conductive plates and a prepreg layer sandwiched between adjacent conductive plates;
至少一个芯片堆叠体,位于所述预浸基板上,所述芯片堆叠体包括自下而上叠置的重新布线层及芯片。At least one chip stack is located on the prepreg substrate, and the chip stack includes rewiring layers and chips stacked from bottom to top.
优选地,所述导电板为PCB板,包括芯板及位于所述芯板表面的金属层。Preferably, the conductive board is a PCB board, including a core board and a metal layer located on the surface of the core board.
优选地,所述预浸层的材料为浸渍树脂。Preferably, the material of the prepreg layer is impregnated resin.
优选地,所述预浸基板中所述导电板及预浸层的层数之和为10层以上。Preferably, the total number of layers of the conductive plate and prepreg layer in the prepreg substrate is 10 or more.
优选地,所述重新布线层包括布线介质层及位于所述布线介质层内的金属布线层。Preferably, the rewiring layer includes a wiring dielectric layer and a metal wiring layer located within the wiring dielectric layer.
如上所述,本发明提供一种芯片封装结构及其制备方法,该制备方法将现有技术中造价昂贵的有机基板替换为重新布线层与预浸基板的组合结构,重新布线层用于实现精细间距布线,之后再与预浸基板键合,以进行较为粗糙的布线连接。该种组合结构相比现有的有机基板具有低成本的显著优势,并能够适用于不需要高频率或低延迟的特定芯片产品封装。同时,将多个芯片与重新布线层形成的多个芯片堆叠体同步键合至预浸基板表面,避免了现有技术中逐个进行键合时制造效率较低的问题,能够有效地节省制造成本并提高生产效率。As mentioned above, the present invention provides a chip packaging structure and a preparation method thereof. The preparation method replaces the expensive organic substrate in the prior art with a combined structure of a rewiring layer and a prepreg substrate. The rewiring layer is used to achieve fine Pitch routing and then bonding to prepreg substrate for rougher routing connections. This combined structure has significant advantages in low cost compared to existing organic substrates, and can be applied to specific chip product packaging that does not require high frequency or low latency. At the same time, multiple chip stacks formed by multiple chips and rewiring layers are simultaneously bonded to the surface of the prepreg substrate, which avoids the problem of low manufacturing efficiency when bonding one by one in the existing technology, and can effectively save manufacturing costs. and improve production efficiency.
图1显示现有技术中的有机基板的结构示意图。Figure 1 shows a schematic structural diagram of an organic substrate in the prior art.
图2显示为本发明中于载板上形成重新布线层及芯片的结构示意图。FIG. 2 shows a schematic structural diagram of forming a rewiring layer and a chip on a carrier board in the present invention.
图3显示为芯片堆叠体的结构示意图。Figure 3 shows a schematic structural diagram of the chip stack.
图4显示为最终形成的芯片封装结构的侧视示意图。Figure 4 shows a schematic side view of the finally formed chip packaging structure.
图5显示为导电板的结构示意图。Figure 5 shows a schematic structural diagram of the conductive plate.
图6显示为最终形成的芯片封装结构的俯视示意图。Figure 6 shows a schematic top view of the finally formed chip packaging structure.
元件标号说明Component label description
101 芯片101 Chip
201 重新布线层201 Rewiring layer
211 金属布线层211 Metal wiring layer
212 布线介质层212 Wiring media layer
301 载板301 Carrier board
401 预浸基板401 Prepreg substrate
410 导电板410 conductive plate
420 预浸层420 Prepreg layer
411 金属层411 metal layer
412 芯板412 core board
413 金属层413 metal layer
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书
所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。The following illustrates the embodiments of the present invention through specific examples. Those skilled in the art can understand from this description Other advantages and effects of the present invention can be readily understood from the disclosure. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
如在详述本发明实施例时,为便于说明,表示器件结构的剖面图会不依一般比例作局部放大,而且所述示意图只是示例,其在此不应限制本发明保护的范围。此外,在实际制作中应包含长度、宽度及深度的三维空间尺寸。When describing the embodiments of the present invention in detail, for convenience of explanation, the cross-sectional views showing the device structure are not partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual production.
为了方便描述,此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等的空间关系词语来描述附图中所示的一个元件或特征与其他元件或特征的关系。将理解到,这些空间关系词语意图包含使用中或操作中的器件的、除了附图中描绘的方向之外的其他方向。此外,当一层被称为在两层“之间”时,它可以是所述两层之间仅有的层,或者也可以存在一个或多个介于其间的层。本文使用的“介于……之间”表示包括两端点值。For convenience of description, spatial relationship words such as "below", "below", "below", "below", "above", "on", etc. may be used herein to describe an element or element shown in the drawings. The relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientations depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between" means including both endpoint values.
在本申请的上下文中,所描述的第一特征在第二特征“之上”的结构可以包括第一和第二特征形成为直接接触的实施例,也可以包括另外的特征形成在第一和第二特征之间的实施例,这样第一和第二特征可能不是直接接触。In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
需要说明的是,本实施例中所提供的图示仅以示意方式说明本发明的基本构想,遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制,其实际实施时各组件的型态、数量及比例可为一种随意的改变,其组件布局型态也可能更为复杂。It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, so the illustrations only show the components related to the present invention and are not based on the number, shape and number of components during actual implementation. Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complex.
针对现有技术中高密度互连的有机基板成本昂贵的缺点,本发明使用预浸基板进行代替。先将硅管芯或芯片连接到由扇出RDL工艺制成的基板上,用于精细间距布线。然后,使用标准倒装芯片组装工艺,将带有附加硅模具/芯片的组装基板连接到具有多层结构的低成本预浸基板上,以进行粗略的电气布线。这种使用封装方法形成的堆叠封装结构,主要针对不需要最高频率或最低延迟的应用。Aiming at the shortcoming of expensive cost of high-density interconnected organic substrates in the prior art, the present invention uses prepreg substrates instead. The silicon die or chip is first attached to a substrate made by the fan-out RDL process for fine pitch wiring. The assembled substrate with the attached silicon mold/chip is then attached to a low-cost prepreg substrate with a multi-layer structure for rough electrical routing using standard flip-chip assembly processes. This stacked packaging structure formed using packaging methods is mainly targeted at applications that do not require the highest frequency or the lowest delay.
实施例一Embodiment 1
如图2-图6所示,本实施例提供一种芯片封装结构的制备方法,包括如下步骤:As shown in Figures 2-6, this embodiment provides a method for preparing a chip packaging structure, which includes the following steps:
S1:提供载板301,在所述载板301上依次形成重新布线层201及芯片101,如图2所示;S1: Provide a carrier board 301, on which the rewiring layer 201 and the chip 101 are sequentially formed, as shown in Figure 2;
S2:去除所述载板301,沿相邻芯片101之间的间隙对所述重新布线层201进行分割,分割后上下相连的芯片101及重新布线层201形成芯片堆叠体,如图3所示;S2: Remove the carrier board 301 and divide the rewiring layer 201 along the gap between adjacent chips 101. After division, the chips 101 and the rewiring layer 201 connected up and down form a chip stack, as shown in Figure 3 ;
S3:将多个所述芯片堆叠体同步键合至预浸基板401表面,所述预浸基板401包括2层以上的导电板410及夹设于相邻导电板410之间的预浸层420,如图4、图6所示。S3: Simultaneously bond multiple chip stacks to the surface of a prepreg substrate 401. The prepreg substrate 401 includes more than two layers of conductive plates 410 and a prepreg layer 420 sandwiched between adjacent conductive plates 410. , as shown in Figure 4 and Figure 6.
具体地,如图5所示,所述导电板410可以是PCB板,PCB板通常包括芯板412及位于芯板412表面的金属层411,其中所述金属层411的材料通常为铜。芯板412是一种硬质的、有特定厚度的板材,可以是玻璃纤维材料,以保证PCB板具有一定的刚性。所述PCB板可以是单面PCB或双面PCB,其区别在于所述金属层位于所述芯板412的一侧或是两侧。作为示例,图4中的导电板410为双面PCB,芯板412的上下表面分别具有金属层411、413。Specifically, as shown in FIG. 5 , the conductive board 410 may be a PCB board. The PCB board usually includes a core board 412 and a metal layer 411 located on the surface of the core board 412 , where the material of the metal layer 411 is usually copper. The core board 412 is a hard plate with a specific thickness, which may be fiberglass material, to ensure that the PCB board has a certain rigidity. The PCB board may be a single-sided PCB or a double-sided PCB. The difference is that the metal layer is located on one side or both sides of the core board 412 . As an example, the conductive board 410 in FIG. 4 is a double-sided PCB, and the upper and lower surfaces of the core board 412 have metal layers 411 and 413 respectively.
所述预浸层420又称为半固化片或Prepreg,其材料通常为浸渍树脂。浸渍树脂是将交联共聚物当作载体吸附树脂,放入液体萃取剂中浸渍,吸收了各种液体离子交换剂的一类树脂。在生产增强复合材料时,用以浸入各种骨架材料如木材、织物、碳纤维或玻璃纤
维等材料的树脂(包括环氧和酚醛树脂等)。本实施例中,所述预浸层420可用作导电板410之间的黏结材料和层间绝缘。在层压时,所述预浸层420的树脂材料融化、流动、凝固,将各层电路黏合在一起,并形成可靠的绝缘层。作为示例,图4中示出了具有2层导电板的具体结构,实际中可根据需要对导电板的数量进行增加,相邻导电板之间使用所述预浸层420进行连接即可。例如,所述预浸基板401中所述导电板410及预浸层420的层数之和可以是10层以上。The prepreg layer 420 is also called a semi-cured sheet or Prepreg, and its material is usually an impregnating resin. Impregnating resin is a type of resin that uses a cross-linked copolymer as a carrier adsorbent resin and is impregnated in a liquid extractant to absorb various liquid ion exchangers. When producing reinforced composite materials, it is used to impregnate various skeleton materials such as wood, fabric, carbon fiber or glass fiber. Resins of materials such as fibers (including epoxy and phenolic resins, etc.). In this embodiment, the prepreg layer 420 can be used as a bonding material and interlayer insulation between the conductive plates 410. During lamination, the resin material of the prepreg layer 420 melts, flows, and solidifies, bonding the layers of circuits together to form a reliable insulating layer. As an example, FIG. 4 shows a specific structure with two layers of conductive plates. In practice, the number of conductive plates can be increased as needed, and adjacent conductive plates can be connected using the prepreg layer 420. For example, the sum of the number of layers of the conductive plates 410 and the prepreg layer 420 in the prepreg substrate 401 can be more than 10 layers.
步骤S3中可以采用大规模回流焊的工艺将多个所述芯片堆叠体以并行的方式同步键合至预浸基板401表面,相比现有的采用热压键合(TCB)的方式将每个芯片逐一键合至有机基板,能够有效地节省制造成本并提高生产效率。In step S3, a large-scale reflow soldering process can be used to simultaneously bond multiple chip stacks to the surface of the prepreg substrate 401 in a parallel manner. Compared with the existing thermocompression bonding (TCB) method, each chip stack is Each chip is bonded to the organic substrate one by one, which can effectively save manufacturing costs and improve production efficiency.
具体地,所述载板301包括玻璃基底、金属基底、半导体基底、聚合物基底及陶瓷基底中的一种。在本实施例中,所述载板301选用为玻璃基底,所述玻璃基底成本较低,且容易在其表面形成临时键合胶(也称TB胶,temporary bonding adhesive)以粘合所述重新布线层201,同时能降低后续的剥离所述载板301的难度。在需要分离时,可以基于激光对所述临时键合胶进行加热使其粘性降低,以使所述重新布线层201及载板301自所述键合层20处相互分离。Specifically, the carrier 301 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate. In this embodiment, the carrier plate 301 is selected as a glass substrate, which has a low cost and is easy to form a temporary bonding adhesive (also called TB glue, temporary bonding adhesive) on its surface to bond the new substrate. The wiring layer 201 can also reduce the subsequent difficulty of peeling off the carrier board 301. When separation is required, the temporary bonding glue can be heated based on a laser to reduce its viscosity, so that the rewiring layer 201 and the carrier board 301 are separated from each other from the bonding layer 20 .
具体地,所述重新布线层201包括布线介质层212及位于所述布线介质层212内的金属布线层211。所述布线介质层212的材料包括由环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃及含氟玻璃组成的群组中的一种或两种以上组合;所述金属布线层211的材料包括由铜、铝、镍、金、银及钛组成的群组中的一种或两种以上组合。所述布线介质层212及金属布线层211的材料、层数及分布形貌,可根据半导体芯片的具体情况进行设置,在此不作限制,本实施例中优选为4-5层。所述芯片101可以是核心芯片(core die)、IO芯片(IO die)、高速缓存/SRAM芯片(cache die)、结构芯片(fabric die)中的一种或任意种的组合,此处不作过多限制。Specifically, the rewiring layer 201 includes a wiring dielectric layer 212 and a metal wiring layer 211 located in the wiring dielectric layer 212 . The material of the wiring dielectric layer 212 includes one or a combination of two or more from the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the metal wiring The material of layer 211 includes one or a combination of two or more from the group consisting of copper, aluminum, nickel, gold, silver and titanium. The material, number of layers and distribution morphology of the wiring dielectric layer 212 and the metal wiring layer 211 can be set according to the specific conditions of the semiconductor chip, and are not limited here. In this embodiment, 4-5 layers are preferred. The chip 101 may be one of a core chip (core die), an IO chip (IO die), a cache/SRAM chip (cache die), a fabric die (fabric die), or any combination thereof, which will not be discussed here. Many restrictions.
本实施例将现有技术中的有机基板100替换为所述重新布线层201与预浸基板401的组合结构,所述重新布线层201用于实现精细间距布线,之后再与所述预浸基板401键合,以进行较为粗糙的布线连接。该种组合结构相比现有的有机基板具有低成本的显著优势,并能够适用于不需要高频率或低延迟的特定芯片产品封装。同时,将所述芯片堆叠体同步键合至预浸基板表面,避免了现有技术中逐个进行键合时制造效率较低的问题,提高了产能。This embodiment replaces the organic substrate 100 in the prior art with a combined structure of the rewiring layer 201 and the prepreg substrate 401. The rewiring layer 201 is used to achieve fine pitch wiring, and is then combined with the prepreg substrate 401. 401 bonding for rougher wiring connections. This combined structure has significant advantages in low cost compared to existing organic substrates, and can be applied to specific chip product packaging that does not require high frequency or low latency. At the same time, the chip stack is synchronously bonded to the surface of the prepreg substrate, which avoids the problem of low manufacturing efficiency when bonding one by one in the prior art, and improves productivity.
实施例二Embodiment 2
本实施例提供一种芯片封装结构,如图4-图6所示,该芯片封装结构可以采用上述实施例一中的制备方法制得,但不限于上述制备方法。所述芯片封装结构具体包括:This embodiment provides a chip packaging structure, as shown in Figures 4 to 6, which can be prepared by the preparation method in the above-mentioned embodiment 1, but is not limited to the above-mentioned preparation method. The chip packaging structure specifically includes:
预浸基板401,所述预浸基板401包括2层以上的导电板410及夹设于相邻导电板410之间的预浸层420;Prepreg substrate 401, which includes two or more layers of conductive plates 410 and a prepreg layer 420 sandwiched between adjacent conductive plates 410;
至少一个芯片堆叠体,位于所述预浸基板401上,所述芯片堆叠体包括自下而上叠置的重新布线层201及芯片101。At least one chip stack is located on the prepreg substrate 401. The chip stack includes a rewiring layer 201 and a chip 101 stacked from bottom to top.
具体地,如图5所示,所述导电板410可以是PCB板,PCB板通常包括芯板412及位于芯板412表面的金属层411,其中所述金属层411的材料通常为铜。芯板412是一种硬质的、有特定厚度的板材,可以是玻璃纤维材料,以保证PCB板具有一定的刚性。所述PCB板可以是单
面PCB或双面PCB,其区别在于所述金属层位于所述芯板412的一侧或是两侧。作为示例,图4中的导电板410为双面PCB,芯板412的上下表面分别具有金属层411、413。Specifically, as shown in FIG. 5 , the conductive board 410 may be a PCB board. The PCB board usually includes a core board 412 and a metal layer 411 located on the surface of the core board 412 , where the material of the metal layer 411 is usually copper. The core board 412 is a hard plate with a specific thickness, which may be fiberglass material, to ensure that the PCB board has a certain rigidity. The PCB board can be a single The difference between the two-sided PCB and the double-sided PCB is that the metal layer is located on one side or both sides of the core board 412 . As an example, the conductive board 410 in FIG. 4 is a double-sided PCB, and the upper and lower surfaces of the core board 412 have metal layers 411 and 413 respectively.
所述预浸层420又称为半固化片或Prepreg,其材料通常为浸渍树脂。浸渍树脂是将交联共聚物当作载体吸附树脂,放入液体萃取剂中浸渍,吸收了各种液体离子交换剂的一类树脂。在生产增强复合材料时,用以浸入各种骨架材料如木材、织物、碳纤维或玻璃纤维等材料的树脂(包括环氧和酚醛树脂等)。本实施例中,所述预浸层420可用作导电板410之间的黏结材料和层间绝缘。在层压时,所述预浸层420的树脂材料融化、流动、凝固,将各层电路黏合在一起,并形成可靠的绝缘层。作为示例,图4中示出了具有2层导电板的具体结构,实际中可根据需要对导电板的数量进行增加,相邻导电板之间使用所述预浸层420进行连接即可。例如,所述预浸基板401中所述导电板410及预浸层420的层数之和可以是10层以上。The prepreg layer 420 is also called prepreg or prepreg, and its material is usually impregnated resin. Impregnation resin is a type of resin that uses a cross-linked copolymer as a carrier adsorption resin, impregnates it in a liquid extraction agent, and absorbs various liquid ion exchangers. When producing reinforced composite materials, resins (including epoxy and phenolic resins, etc.) used to impregnate various skeleton materials such as wood, fabric, carbon fiber or glass fiber. In this embodiment, the prepreg layer 420 can be used as a bonding material and interlayer insulation between the conductive plates 410 . During lamination, the resin material of the prepreg layer 420 melts, flows, and solidifies, bonding each layer of circuits together and forming a reliable insulation layer. As an example, FIG. 4 shows a specific structure with two layers of conductive plates. In practice, the number of conductive plates can be increased as needed, and the prepreg layer 420 can be used to connect adjacent conductive plates. For example, the total number of layers of the conductive plate 410 and the prepreg layer 420 in the prepreg substrate 401 may be 10 or more layers.
具体地,所述重新布线层201包括布线介质层212及位于所述布线介质层212内的金属布线层211。所述布线介质层212的材料包括由环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃及含氟玻璃组成的群组中的一种或两种以上组合;所述金属布线层211的材料包括由铜、铝、镍、金、银及钛组成的群组中的一种或两种以上组合。所述布线介质层212及金属布线层211的材料、层数及分布形貌,可根据半导体芯片的具体情况进行设置,在此不作限制,本实施例中优选为4-5层。所述芯片101可以是核心芯片(core die)、IO芯片(IO die)、高速缓存/SRAM芯片(cache die)、结构芯片(fabric die)中的一种或任意种的组合,此处不作过多限制。Specifically, the rewiring layer 201 includes a wiring dielectric layer 212 and a metal wiring layer 211 located in the wiring dielectric layer 212 . The material of the wiring dielectric layer 212 includes one or a combination of two or more from the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the metal wiring The material of layer 211 includes one or a combination of two or more from the group consisting of copper, aluminum, nickel, gold, silver and titanium. The material, number of layers and distribution morphology of the wiring dielectric layer 212 and the metal wiring layer 211 can be set according to the specific conditions of the semiconductor chip, and are not limited here. In this embodiment, 4-5 layers are preferred. The chip 101 may be one of a core chip (core die), an IO chip (IO die), a cache/SRAM chip (cache die), a fabric die (fabric die), or any combination thereof, which will not be explained here. Many restrictions.
综上所述,本发明提供一种芯片封装结构及其制备方法,该制备方法将现有技术中造价昂贵的有机基板替换为重新布线层与预浸基板的组合结构,重新布线层用于实现精细间距布线,之后再与预浸基板键合,以进行较为粗糙的布线连接。该种组合结构相比现有的有机基板具有低成本的显著优势,并能够适用于不需要高频率或低延迟的特定芯片产品封装。同时,将多个芯片与重新布线层形成的多个芯片堆叠体同步键合至预浸基板表面,避免了现有技术中逐个进行键合时制造效率较低的问题,能够有效地节省制造成本并提高生产效率。In summary, the present invention provides a chip packaging structure and a preparation method thereof. The preparation method replaces the expensive organic substrate in the prior art with a combined structure of a rewiring layer and a prepreg substrate. The rewiring layer is used to realize Fine pitch routing is then bonded to a prepreg substrate for rougher routing connections. This combined structure has significant advantages in low cost compared to existing organic substrates, and can be applied to specific chip product packaging that does not require high frequency or low latency. At the same time, multiple chip stacks formed by multiple chips and rewiring layers are simultaneously bonded to the surface of the prepreg substrate, which avoids the problem of low manufacturing efficiency when bonding one by one in the existing technology, and can effectively save manufacturing costs. and improve production efficiency.
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。
The above embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.
Claims (10)
- 一种芯片封装结构的制备方法,其特征在于,所述制备方法包括如下步骤:A method for preparing a chip packaging structure, characterized in that the preparation method includes the following steps:S1:提供载板,在所述载板上依次形成重新布线层及芯片;S1: providing a carrier board, and sequentially forming a rewiring layer and a chip on the carrier board;S2:去除所述载板,沿相邻芯片之间的间隙对所述重新布线层进行分割,分割后上下相连的芯片及重新布线层形成芯片堆叠体;S2: Remove the carrier board, divide the rewiring layer along the gap between adjacent chips, and form a chip stack by dividing the chips and rewiring layers connected up and down;S3:将多个所述芯片堆叠体同步键合至预浸基板表面,所述预浸基板包括2层以上的导电板及夹设于相邻导电板之间的预浸层。S3: Simultaneously bond a plurality of the chip stacks to the surface of a prepreg substrate. The prepreg substrate includes more than two layers of conductive plates and a prepreg layer sandwiched between adjacent conductive plates.
- 根据权利要求1所述的制备方法,其特征在于,所述导电板为PCB板,包括芯板及位于所述芯板表面的金属层。The preparation method according to claim 1, characterized in that the conductive plate is a PCB board, including a core plate and a metal layer located on the surface of the core plate.
- 根据权利要求1所述的制备方法,其特征在于,所述预浸层的材料为浸渍树脂。The preparation method according to claim 1, characterized in that the material of the prepreg layer is impregnated resin.
- 根据权利要求1所述的制备方法,其特征在于,所述预浸基板中所述导电板及预浸层的层数之和为10层以上。The preparation method according to claim 1, characterized in that the total number of layers of the conductive plate and the prepreg layer in the prepreg substrate is 10 or more.
- 根据权利要求1所述的制备方法,其特征在于,所述重新布线层包括布线介质层及位于所述布线介质层内的金属布线层。The preparation method according to claim 1 is characterized in that the rewiring layer includes a wiring dielectric layer and a metal wiring layer located in the wiring dielectric layer.
- 一种芯片封装结构,其特征在于,所述芯片封装结构包括:A chip packaging structure, characterized in that the chip packaging structure includes:预浸基板,所述预浸基板包括2层以上的导电板及夹设于相邻导电板之间的预浸层;Prepreg substrate, the prepreg substrate includes more than two layers of conductive plates and a prepreg layer sandwiched between adjacent conductive plates;至少一个芯片堆叠体,位于所述预浸基板上,所述芯片堆叠体包括自下而上叠置的重新布线层及芯片。At least one chip stack is located on the prepreg substrate, and the chip stack includes rewiring layers and chips stacked from bottom to top.
- 根据权利要求6所述的芯片封装结构,其特征在于,所述导电板为PCB板,包括芯板及位于所述芯板表面的金属层。The chip packaging structure according to claim 6, wherein the conductive plate is a PCB board, including a core board and a metal layer located on the surface of the core board.
- 根据权利要求6所述的芯片封装结构,其特征在于,所述预浸层的材料为浸渍树脂。The chip packaging structure according to claim 6, wherein the material of the prepreg layer is impregnated resin.
- 根据权利要求6所述的芯片封装结构,其特征在于,所述预浸基板中所述导电板及预浸层的层数之和为10层以上。The chip packaging structure according to claim 6, wherein the total number of layers of the conductive plate and the prepreg layer in the prepreg substrate is 10 or more.
- 根据权利要求6所述的芯片封装结构,其特征在于,所述重新布线层包括布线介质层及位于所述布线介质层内的金属布线层。 The chip packaging structure according to claim 6, wherein the rewiring layer includes a wiring dielectric layer and a metal wiring layer located in the wiring dielectric layer.
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104602449A (en) * | 2013-10-30 | 2015-05-06 | 英飞凌科技股份有限公司 | System and Method for a Millimeter Wave Circuit Board |
CN107785339A (en) * | 2017-10-13 | 2018-03-09 | 中芯长电半导体(江阴)有限公司 | 3D chip-packaging structures and preparation method thereof |
CN110867385A (en) * | 2019-11-07 | 2020-03-06 | 中芯长电半导体(江阴)有限公司 | Packaging structure and preparation method thereof |
US20210020600A1 (en) * | 2019-07-18 | 2021-01-21 | Samsung Electronics Co., Ltd. | Method of manufacturing fan-out wafer level package |
CN112310050A (en) * | 2019-07-29 | 2021-02-02 | 英特尔公司 | Multi-die ultra fine pitch tile architecture and method of manufacture |
US20210366863A1 (en) * | 2020-05-20 | 2021-11-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor Package and Method |
CN115458501A (en) * | 2022-09-20 | 2022-12-09 | 盛合晶微半导体(江阴)有限公司 | Chip packaging structure and preparation method thereof |
-
2022
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-
2023
- 2023-06-09 WO PCT/CN2023/099291 patent/WO2024060694A1/en unknown
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104602449A (en) * | 2013-10-30 | 2015-05-06 | 英飞凌科技股份有限公司 | System and Method for a Millimeter Wave Circuit Board |
CN107785339A (en) * | 2017-10-13 | 2018-03-09 | 中芯长电半导体(江阴)有限公司 | 3D chip-packaging structures and preparation method thereof |
US20210020600A1 (en) * | 2019-07-18 | 2021-01-21 | Samsung Electronics Co., Ltd. | Method of manufacturing fan-out wafer level package |
CN112310050A (en) * | 2019-07-29 | 2021-02-02 | 英特尔公司 | Multi-die ultra fine pitch tile architecture and method of manufacture |
CN110867385A (en) * | 2019-11-07 | 2020-03-06 | 中芯长电半导体(江阴)有限公司 | Packaging structure and preparation method thereof |
US20210366863A1 (en) * | 2020-05-20 | 2021-11-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor Package and Method |
CN115458501A (en) * | 2022-09-20 | 2022-12-09 | 盛合晶微半导体(江阴)有限公司 | Chip packaging structure and preparation method thereof |
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