CN206758428U - Fan-out-type wafer level packaging structure - Google Patents
Fan-out-type wafer level packaging structure Download PDFInfo
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- CN206758428U CN206758428U CN201720531294.XU CN201720531294U CN206758428U CN 206758428 U CN206758428 U CN 206758428U CN 201720531294 U CN201720531294 U CN 201720531294U CN 206758428 U CN206758428 U CN 206758428U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The utility model provides a kind of fan-out-type wafer level packaging structure, and the fan-out-type wafer level packaging structure comprises at least：Re-wiring layer；First flip-chip, it is bonded to the upper surface of the re-wiring layer；Metal paste conductive pole, electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；Second flip-chip, it is bonded to the upper surface of the metal paste conductive pole；Plastic packaging layer, positioned at the upper surface of the re-wiring layer；Soldered ball projection, positioned at the lower surface of the re-wiring layer.In fan-out-type wafer level packaging structure of the present utility model, metallic conduction post of the prior art is substituted using metal paste conductive pole, metal paste conductive pole can be prepared using metal paste typography, and preparing metallic conduction post compared to electroplating technology of the prior art has the advantages that cost is low, preparation technology is simple.
Description
Technical field
Technical field of semiconductor encapsulation is the utility model is related to, more particularly to a kind of fan-out-type wafer level packaging structure.
Background technology
It is more inexpensive, more reliable, faster and more highdensity circuit be integrated antenna package pursue target.In future,
Integrated antenna package will improve the integration density of various electronic components by constantly reducing minimum feature size.At present, first
The method for packing entered includes：Wafer chip level chip-scale package (Wafer Level Chip Scale Packaging,
WLCSP), fan-out-type wafer-level packaging (Fan-Out Wafer Level Package, FOWLP), flip-chip (Flip
Chip), stacked package (Package on Package, POP) etc..
Fan-out-type wafer-level packaging is a kind of embedded chip method for packing of wafer level processing, be current a kind of input/
One of preferable Advanced Packaging method of more, the integrated flexibility of output port (I/O).Fan-out-type wafer-level packaging is compared to routine
Wafer-level packaging have its it is unique the advantages of：1. I/O spacing is flexible, independent of chip size；2. only use effective nude film
(die), product yield improves；3. there is flexible 3D package paths, you can to form the figure of General Cell at top；4. have
There are preferable electrical property and hot property；5. frequency applications；6. easily realize high-density wiring in re-wiring layer (RDL).
At present, fan-out-type wafer-level packaging method is generally：Carrier is provided, adhesive layer is formed in carrier surface；In bonding
Photoetching on layer, electroplate out re-wiring layer (Redistribution Layers, RDL)；Using chip bonding/flip-chip work
Flip-chip is arranged on re-wiring layer by skill, and metallic conduction post is formed on re-wiring layer using electroplating technology；Adopt
With Shooting Technique by flip-chip and metallic conduction post plastic packaging in capsulation material layer；Photoetching, electroplate out metal layer under ball；Enter
Row plants ball backflow, forms soldered ball bump array；Remove carrier.However, exist such as in existing fan-out-type wafer level packaging structure
Lower problem：1. flip-chip is arranged in individual layer in fan-out-type wafer level packaging structure, pass through routing mode phase between flip-chip
Connect, the spacing between the flip-chip being connected is farther out so that it is longer that the response time is linked up between flip-chip；2. metal is led
Electric post is formed using electroplating technology, then again together with flip-chip by capsulation material layer plastic packaging；Plating forms metallic conduction post
The shortcomings of costly, complex process is difficult be present.
Utility model content
In view of the above the shortcomings that prior art, the purpose of this utility model is to provide a kind of fan-out-type wafer scale envelope
Assembling structure, for solving fan-out-type wafer level packaging structure of the prior art because flip-chip is existing in individual layer arrangement
The problem of communication response time is longer between flip-chip, and it is existing due to forming metallic conduction post using electroplating technology
Costly, the problem of complex process is difficult.
In order to achieve the above objects and other related objects, the utility model provides a kind of fan-out-type wafer level packaging structure,
The fan-out-type wafer level packaging structure comprises at least：
Re-wiring layer；
First flip-chip, the upper surface of the re-wiring layer is bonded to, and is electrically connected with the re-wiring layer；
Metal paste conductive pole, electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；
Second flip-chip, the upper surface of the metal paste conductive pole is bonded to, and positioned at first flip-chip
Top, second flip-chip electrically connect via the metal paste conductive pole with the re-wiring layer；
Plastic packaging layer, positioned at the upper surface of the re-wiring layer, and fill up first flip-chip, the metal paste is led
Gap between electric post, second flip-chip and the re-wiring layer, and by first flip-chip, the metal
Cream conductive pole and second flip-chip enveloping plastic packaging；
Soldered ball projection, electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer.
Preferably, the re-wiring layer comprises at least：
First dielectric layer；
Metallic stacked structure, in first dielectric layer, the metallic stacked structure includes Spaced arrangement
Metal line layer and metal plug, the metal plug is between the adjacent metal line layer, by the adjacent metal wire
Layer electrical connection；
Lower metal layer, electrically connected positioned at the upper surface of first dielectric layer, and with the metal line layer.
Preferably, first flip-chip comprises at least：
Bare chip；
Articulamentum, positioned at the upper surface of the bare chip；
Projection is interconnected, on the articulamentum, and the interconnection projection is realized and the naked core by the articulamentum
The electric connection of piece；
Wherein, first flip-chip by the interconnection bump bond in the upper surface of the lower metal layer, from
And realize the electric connection with the re-wiring layer.
Preferably, the articulamentum comprises at least：
Multiple pads, positioned at the upper surface of the bare chip；
Second dielectric layer, it is covered in the upper surface of the bare chip and the pad；
Insulating barrier, positioned at the upper surface of second dielectric layer；
Through hole, through the insulating barrier and second dielectric layer, to expose the upper surface of the pad.
Preferably, the interconnection projection is formed at upper surface and the covering part insulating barrier of the pad, and the interconnection
Projection realizes the electric connection with the bare chip by the pad.
Preferably, the interconnection projection is by metal column and is formed at the gold that the metal cap of the metal column upper surface forms
Belong to combining structure, or the interconnection projection is metal welding pellet.
Preferably, the material of the metal column includes Cu or Ni, the material of the metal cap and the metal welding pellet
Material includes tin, copper, nickel, silver-colored gun-metal or kamash alloy respectively.
Preferably, first dielectric layer and second dielectric layer use low k dielectric.
Preferably, the material of the plastic packaging layer includes polyimides, silica gel or epoxy resin.
In order to achieve the above objects and other related objects, the preparation method of the fan-out-type wafer level packaging structure is at least wrapped
Include following steps：
One carrier is provided, adhesive layer is formed in the upper surface of the carrier；
Re-wiring layer is formed in the upper surface of the adhesive layer；
The first flip-chip, the flip-chip and the re-wiring layer are bonded in the upper surface of the re-wiring layer
Realize and be electrically connected with；
The first plastic packaging layer is formed in the upper surface of the re-wiring layer, the first plastic packaging layer fills up first upside-down mounting
Gap between chip and the re-wiring layer, and first flip-chip is encapsulated into plastic packaging；
In forming opening in the first plastic packaging layer, the opening runs through the first plastic packaging layer to expose described in part
Re-wiring layer；
Metal paste conductive pole is formed in the opening using metal paste typography, the metal paste conductive pole with it is described
Re-wiring layer electrically connects；
The second flip-chip is bonded in the upper surface of the first plastic packaging layer；Second flip-chip is located at described first
The top of flip-chip, and electrically connected via the metal paste conductive pole with the re-wiring layer；
The second plastic packaging layer is formed in the upper surface of the first plastic packaging layer, the second plastic packaging layer fills up second upside-down mounting
Gap between chip and the first plastic packaging layer, and second flip-chip is encapsulated into plastic packaging；
Remove the carrier and the adhesive layer；
Soldered ball projection is formed in the lower surface of the re-wiring layer.
Preferably, re-wiring layer is formed in the upper surface of the passivation layer to comprise the following steps：
First layer metal line layer is formed in the upper surface of the passivation layer；
The upper surface of metal line layer described in covering first layer is formed in the upper surface of the passivation layer and the first of side wall is situated between
Electric layer；
It is adjacent in other metal line layers formed in first dielectric layer and the first layer metal line layer is electrically connected with
Electrically connected between the metal line layer via metal plug；
Lower metal layer, the lower metal layer and the metal wiring layer are formed in the upper surface of first dielectric layer
Electrical connection.
Preferably, first flip-chip comprises at least：Bare chip；Articulamentum, positioned at the upper surface of the bare chip；
Interconnect projection, on the articulamentum, and the interconnection projection realized by the articulamentum it is electrical with the bare chip
Connection；Wherein, first flip-chip by the interconnection bump bond in the upper surface of the lower metal layer, so as to real
Now with the electric connection of the re-wiring layer；Being bonded first flip-chip in the upper surface of the re-wiring layer includes
Following steps：
Scaling powder glue-line is formed in the upper surface of the upper surface of the interconnection projection or the lower metal layer；
By the position where lower metal layer described in the top alignment of the interconnection projection, reflow soldering is then carried out, from
And make first flip-chip by the interconnection bump bond in the upper surface of the lower metal layer.
Preferably, first plastic packaging is formed in the upper surface of the re-wiring layer using molded underfill technique
Layer；The second plastic packaging layer is formed in the upper surface of the first plastic packaging layer using molded underfill technique.
Preferably, using laser boring technique in forming the opening in the first plastic packaging layer.
As described above, fan-out-type wafer level packaging structure of the present utility model, has the advantages that：The utility model
Fan-out-type wafer level packaging structure in, substitute metallic conduction post of the prior art using metal paste conductive pole, metal paste is led
Electric post can be prepared using metal paste typography, and metallic conduction post is prepared compared to electroplating technology of the prior art
Have the advantages that cost is low, preparation technology is simple；Meanwhile in fan-out-type wafer level packaging structure of the present utility model, first falls
Cartridge chip and the perpendicular storehouse of the second flip-chip are distributed so that between first flip-chip and second flip-chip
Spacing reach most short, so as to shorten the communication response time of first flip-chip and second flip-chip.
Brief description of the drawings
Fig. 1 is shown as the structural representation of the fan-out-type wafer level packaging structure provided in the utility model embodiment one.
Fig. 2 is shown as the first upside-down mounting core in the fan-out-type wafer level packaging structure that is provided in the utility model embodiment one
The structural representation of piece.
Fig. 3 is shown as the stream of the preparation method of the fan-out-type wafer level packaging structure provided in the utility model embodiment two
Journey schematic diagram.
Fig. 4~Figure 13 is shown as each step institute of fan-out-type wafer-level packaging method provided in the utility model embodiment two
The structural representation of presentation.
Component label instructions
1 re-wiring layer
11 first dielectric layers
12 metallic stacked structures
13 times metal layers
2 first flip-chips
21 bare chips
22 articulamentums
221 pads
222 second dielectric layers
223 insulating barriers
23 interconnection projections
231 metal columns
232 metal caps
3 metal paste conductive poles
4 second flip-chips
5 plastic packaging layers
51 first plastic packaging layers
511 openings
52 second plastic packaging layers
6 soldered ball projections
7 carriers
8 adhesive layers
Embodiment
Illustrate embodiment of the present utility model below by way of specific instantiation, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the present utility model easily.The utility model can also be by addition
Different embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering
With, without departing from it is of the present utility model spirit under carry out various modifications or alterations.
Fig. 1 is referred to Figure 13.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though when the component relevant with the utility model is only shown in diagram rather than being implemented according to reality
Component count, shape and size are drawn, and it is actual when implementing form, quantity and the ratio of each component can be a kind of changing arbitrarily
Become, and its assembly layout kenel may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the utility model provides a kind of fan-out-type wafer level packaging structure, the fan-out-type wafer-level packaging
Structure comprises at least：Re-wiring layer 1；First flip-chip 2, first flip-chip 2 are bonded to the re-wiring layer 1
Upper surface, and electrically connected with the re-wiring layer 1；Metal paste conductive pole 3, the metal paste conductive pole 3 is positioned at described heavy
The upper surface of new route layer 1, and electrically connected with the re-wiring layer 1；Second flip-chip 4, the key of the second flip-chip 4
Together in the upper surface of the metal paste conductive pole 3, and positioned at the top of first flip-chip 2, second flip-chip 2
Electrically connected via the metal paste conductive pole 3 with the re-wiring layer 1；Plastic packaging layer 5, the plastic packaging layer 5 positioned at it is described again
The upper surface of wiring layer 1, and fill up first flip-chip 2, the metal paste conductive pole 3, second flip-chip 4 and
Gap between the re-wiring layer 1, and first flip-chip 2, the metal paste conductive pole 3 and described second are fallen
Cartridge chip 4 encapsulates plastic packaging；Soldered ball projection 6, the soldered ball projection 6 are located at the lower surface of the re-wiring layer 1, and with it is described heavy
New route layer 1 electrically connects.In fan-out-type wafer level packaging structure of the present utility model, substituted using the metal paste conductive pole 3
Metallic conduction post of the prior art, the metal paste conductive pole 3 can be prepared using metal paste typography, compared
Preparing metallic conduction post in electroplating technology of the prior art has the advantages that cost is low, preparation technology is simple；Meanwhile this practicality
In new fan-out-type wafer level packaging structure, 2 and second flip-chip of the first flip-chip, the 4 perpendicular storehouse distribution,
So that the spacing between first flip-chip 2 and second flip-chip 4 reaches most short, so as to shorten described first
The communication response time of flip-chip 2 and second flip-chip 4.
In the fan-out-type wafer level packaging structure of present embodiment, the plastic packaging layer 5 fill up first flip-chip 2,
Gap between the metal paste conductive pole 3, second flip-chip 4 and the re-wiring layer 1, and described first is fallen
Cartridge chip 2, the metal paste conductive pole 3 and second flip-chip 4 enveloping plastic packaging, on the one hand can protect described first to fall
Interconnection portion between cartridge chip 2 and second flip-chip 4 and the re-wiring layer 1, it is on the other hand described first
Seamless bonding is provided between flip-chip 2 and second flip-chip 4 and the re-wiring layer 1 and good is connect
Structure is closed, there is good packaging effect, avoid the risk of interface debonding, improve the reliability of encapsulating structure, it is more applicable
Encapsulate in highly integrated device, be with a wide range of applications in field of semiconductor package.In addition, forming the plastic packaging layer 5
When, underfill is carried out using capsulation material, capsulation material can be rapidly flowing into first flip-chip 2, institute with smooth
The gap between metal paste conductive pole 3, second flip-chip 4 and the re-wiring layer 1 is stated, reduces technology difficulty,
It can be used in smaller connection gap.
As an example, the metal paste conductive pole 3 is positioned at can as shown in fig. 1, respectively positioned at the first upside-down mounting core
The both sides of piece 2, and the upper surface of the metal paste conductive pole 3 is greater than or equal to the upper surface of first flip-chip 2.It is described
Second flip-chip 4 is located at the surface of first flip-chip 2, and via with positioned at the both sides of the first flip-chip 2
The metal paste conductive pole 3 electrically connected with the re-wiring layer 1.
As an example, the metal paste conductive pole 3 can be to form opening in the present plastic packaging layer 5, then using gold
The structure that category cream typography is printed filling metal paste and formed in the opening.Form the gold of the metal paste conductive pole 3
It can be any one conductive metal paste of the prior art to belong to cream.For example, in the present embodiment, the metal paste conductive pole 3
Material can be metal powder granulates or the mixed structure of metal glue material and organic matter, the metal powder granulates or the metal
Glue material can be distributed evenly in the organic matter.The organic matter can be but be not limited only to conducting resinl etc..
As an example, the re-wiring layer 1 comprises at least：First dielectric layer 11；Metallic stacked structure 12, the metal
Laminated construction 12 is located in first dielectric layer 11, and the metallic stacked structure 12 includes the metal line layer of Spaced arrangement
And metal plug, the metal plug electrically connect the adjacent metal line layer between the adjacent metal line layer；
Lower metal layer 13, the lower metal layer 13 are located at the upper surface of first dielectric layer 11, and electric with the metal line layer
Connection.
As an example, the metal line layer can include single metal layer, two layers or more metal layers can also be included.Make
For example, the metal line layer and the metal plug can be using copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds
Combined material above.
As an example, the material of the lower metal layer 13 can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or
Two or more combined materials.
As an example, referring to Fig. 2, first flip-chip 2 comprises at least：Bare chip 21；Articulamentum 22, the company
Connect the upper surface that layer 22 is located at the bare chip 21；Projection 23 is interconnected, the interconnection projection 23 is located on the articulamentum 22, and
The interconnection projection 23 realizes the electric connection with the bare chip 21 by the articulamentum 22；Wherein, first upside-down mounting
Chip 2 is bonded to the upper surface of the lower metal layer 13 by the interconnection projection 23, so as to realize and the rewiring
The electric connection of layer 1.
As an example, the articulamentum 22 comprises at least：Multiple pads 221, the pad 221 are located at the bare chip 21
Upper surface；Second dielectric layer 222, second dielectric layer 222 are covered in the upper surface of the bare chip 21 and the pad
221；Insulating barrier 223, the insulating barrier 223 are located at the upper surface of second dielectric layer 222；Through hole, the through hole run through institute
Insulating barrier 223 and second dielectric layer 222 are stated, to expose the upper surface of the pad 221.
As an example, the interconnection projection 23 is formed at upper surface and the covering part insulating barrier 223 of the pad 221,
And the interconnection projection 23 realizes the electric connection with the bare chip 21 by the pad 221.
As an example, insulating barrier 223 can use the materials such as silica or PET.
Although it is to be understood that only include two described 221, two interconnections of pads in structural representation shown in Fig. 2
Projection 23, but Fig. 2 is only the simple schematic diagram drawn for the first flip-chip of specific explanations 2, in fact, present embodiment
In first flip-chip 2 can include multiple pads 221, it is multiple it is described interconnection projection 23, not with shown in Fig. 2
Structural representation for limitation.
In one example, as shown in Fig. 2 the interconnection projection 23 is by metal column 231 and is formed at the upper table of metal column 231
The metallic combination structure that the metal cap 232 in face forms.
As an example, metal column 231 can use Cu or Ni metal materials.Wherein, metal column 231 preferably uses Cu posts.
As an example, metal cap 232 can use a kind of material in tin, copper, nickel, silver-colored gun-metal or kamash alloy
Material, include but is not limited to this.
In another example, the interconnection projection 23 can also be metal welding pellet (solder ball).
As an example, metal welding pellet can use a kind of material in tin, copper, nickel, silver-colored gun-metal or kamash alloy
Material, include but is not limited to this.
As an example, first dielectric layer 11 and second dielectric layer 222 can use low k dielectric.Make
For example, the first dielectric layer 11 and the second dielectric layer 222 can use epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorus
A kind of material in silica glass and fluorine-containing glass.
As an example, the material of the plastic packaging layer 5 can be polyimides, silica gel or epoxy resin.
Embodiment two
Referring to Fig. 3, the utility model also provides a kind of preparation method of fan-out-type wafer level packaging structure, it is described to be fanned out to
The preparation method of type wafer level packaging structure is suitable to prepare the fan-out-type wafer level packaging structure as described in embodiment one, described
The preparation method of fan-out-type wafer level packaging structure comprises at least following steps：
S1：One carrier is provided, adhesive layer is formed in the upper surface of the carrier；
S2：Re-wiring layer is formed in the upper surface of the adhesive layer；
S3：The first flip-chip, the flip-chip and the cloth again are bonded in the upper surface of the re-wiring layer
Line layer, which is realized, to be electrically connected with；
S4：The first plastic packaging layer is formed in the upper surface of the re-wiring layer, the first plastic packaging layer fills up described first
Gap between flip-chip and the re-wiring layer, and first flip-chip is encapsulated into plastic packaging；
S5：In forming opening in the first plastic packaging layer, the opening runs through the first plastic packaging layer to expose part
The re-wiring layer；
S6：Metal paste conductive pole is formed in the opening using metal paste typography, the metal paste conductive pole with
The re-wiring layer electrical connection；
S7：The second flip-chip is bonded in the upper surface of the first plastic packaging layer；Second flip-chip is positioned at described
The top of first flip-chip, and electrically connected via the metal paste conductive pole with the re-wiring layer；
S8：The second plastic packaging layer is formed in the upper surface of the first plastic packaging layer, the second plastic packaging layer fills up described second
Gap between flip-chip and the first plastic packaging layer, and second flip-chip is encapsulated into plastic packaging；
S9：Remove the carrier and the adhesive layer；
S10：Soldered ball projection is formed in the lower surface of the re-wiring layer.
In step sl, S1 steps and Fig. 4 in Fig. 3 are referred to, there is provided a carrier 7, in the upper surface shape of the carrier 7
Into adhesive layer 8.
As an example, the material of the carrier 7 can be in silicon, glass, silica, ceramics, polymer and metal
A kind of material or two or more composites, its shape can be wafer shape, it is square or it is other it is any needed for shape.
As an example, the adhesive layer 8 in subsequent technique as the re-wiring layer 1 being subsequently formed and positioned at institute
The separating layer between the other structures on re-wiring layer 1 and the carrier 7 is stated, it is preferably from the bonding with smooth finish surface
Material is made, and it must have certain adhesion with re-wiring layer 1, to ensure the re-wiring layer 1 in subsequent technique
In will not produce situations such as mobile, in addition, it also has stronger adhesion with the carrier 7, in general, itself and the load
The adhesion of body 7 needs to be more than the adhesion with the re-wiring layer 1.As an example, the material of the adhesive layer 8 is selected from double
Face is respectively provided with the adhesive tape of viscosity or the adhesive glue by spin coating proceeding making etc..Adhesive tape preferably uses UV adhesive tapes, and it is in UV illumination
It is easy to pull off after penetrating.In other embodiments, physical vaporous deposition or chemical gaseous phase also can be selected in the adhesive layer 8
The other materials layer that sedimentation is formed, such as epoxy resin (Epoxy), silicon rubber (silicone rubber), polyimides
(PI), polybenzoxazoles (PBO), benzocyclobutene (BCB) etc..In carrier 7 described in later separation, can use wet etching,
The methods of cmp, removes the adhesive layer 8.
In step s 2, S2 steps and Fig. 5 in Fig. 3 are referred to, in the upper surface of the adhesive layer 8 formation again cloth
Line layer 1.
Comprise the following steps as an example, forming re-wiring layer 1 in the upper surface of the adhesive layer 8：
S21：First layer metal line layer is formed in the upper surface of the adhesive layer 8；
S22：The of the upper surface of metal line layer described in covering first layer and side wall is formed in the upper surface of the adhesive layer 8
One dielectric layer 11；
S23：In other metal wires formed in first dielectric layer 11 and the first layer metal line layer is electrically connected with
Layer, electrically connected between the adjacent metal line layer via metal plug；Each layer metal line layer and the metal plug are common
Form metallic stacked structure 12；
S24：Form lower metal layer 13 in the upper surface of first dielectric layer 11, the lower metal layer 13 with it is described
Metal wiring layer electrically connects.
As an example, the metal line layer can include single metal layer, two layers or more metal layers can also be included.Make
For example, the metal line layer and the metal plug can be using copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds
Combined material above.
As an example, the material of first dielectric layer 11 can be low k dielectric.As an example, described first is situated between
Electric layer 11 can use a kind of material in epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass,
And the techniques such as spin coating, CVD, plasma enhanced CVD can be used to form first dielectric layer 11.
As an example, the material of the lower metal layer 13 can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or
Two or more combined materials.
In step s3, S3 steps and Fig. 6 in Fig. 3 are referred to, first is bonded in the upper surface of the re-wiring layer 1
Flip-chip 2, the flip-chip 2 are realized with the re-wiring layer 1 and are electrically connected with.
As an example, please continue to refer to Fig. 2 in embodiment one, first flip-chip 2 comprises at least：Bare chip
21；Articulamentum 22, the articulamentum 22 are located at the upper surface of the bare chip 21；Interconnect projection 23, the interconnection projection 23
In on the articulamentum 22, and the interconnection projection 23 is realized by the articulamentum 22 and connected with the electrical of the bare chip 21
Connect；Wherein, first flip-chip 2 is bonded to the upper surface of the lower metal layer 13 by the interconnection projection 23, from
And realize the electric connection with the re-wiring layer 1；The first upside-down mounting core is bonded in the upper surface of the re-wiring layer 1
Piece 2 comprises the following steps：
Scaling powder glue-line is formed in the upper surface of the upper surface of the interconnection projection 23 or the lower metal layer 13；
By top (i.e. described surface of the interconnection projection 23 away from the articulamentum 22) alignment institute of the interconnection projection 23
The position where lower metal layer 13 is stated, reflow soldering is then carried out, so that first flip-chip 2 passes through the interconnection
Projection 23 is bonded to the upper surface of the lower metal layer 13.The structure of formation is as shown in Figure 6.
It is to be understood that the scaling powder glue-line can remove the interconnection projection 23 and the table of lower metal layer 13
Oxide layer on face, improve the wetting effect of solder flux and the reliability of engagement.The scaling powder glue-line can use dipping or
The modes such as spraying are formed, should be as thin as possible and uniform.
As an example, the articulamentum 22 comprises at least：Multiple pads 221, the pad 221 are located at the bare chip 21
Upper surface；Second dielectric layer 222, second dielectric layer 222 are covered in the upper surface of the bare chip 21 and the pad
221；Insulating barrier 223, the insulating barrier 223 are located at the upper surface of second dielectric layer 222；Through hole, the through hole run through institute
Insulating barrier 223 and second dielectric layer 222 are stated, to expose the upper surface of the pad 221.
In one example, as shown in Fig. 2 in embodiment one, the interconnection projection 23 is by metal column 231 and is formed at gold
Belong to the metallic combination structure that the metal cap 232 of the upper surface of post 231 forms.
As an example, metal column 231 can use Cu or Ni metal materials.Wherein, metal column 231 preferably uses Cu posts.
As an example, metal cap 232 can use a kind of material in tin, copper, nickel, silver-colored gun-metal or kamash alloy
Material, include but is not limited to this.
In another example, the interconnection projection 23 can also be metal welding pellet (solder ball).
As an example, metal welding pellet can use a kind of material in tin, copper, nickel, silver-colored gun-metal or kamash alloy
Material, include but is not limited to this.
, in the present embodiment, can be with it should be noted that first flip-chip 2 can include a variety of circuit structures
First flip-chip 2 of multiple same types is bonded, multiple different types of first flip-chips can also be bonded
2, it can be selected as needed.
In step s 4, S4 steps and Fig. 7 in Fig. 3 are referred to, first is formed in the upper surface of the re-wiring layer 1
Plastic packaging layer 51, the gap that the first plastic packaging layer 51 is filled up between first flip-chip 2 and the re-wiring layer 1, and
First flip-chip 2 is encapsulated into plastic packaging.
As an example, first modeling is formed in the upper surface of the re-wiring layer 1 using molded underfill technique
Sealing 51.The first plastic packaging layer 51, plastic packaging are formed in the upper surface of the re-wiring layer 1 using molded underfill technique
The gap that material can be promptly filled up with smooth between first flip-chip 2 and the re-wiring layer 1, can be effective
Avoid interface debonding occurring；And molded underfill will not be limited as capillary underfill technique of the prior art
System, greatly reduces technology difficulty, can be used for smaller joint gap, be more suitable for stacked architecture.
In step s 5, S5 steps and Fig. 8 in Fig. 3 are referred to, opening 511 is formed in the first plastic packaging layer 51,
The opening 511 runs through the first plastic packaging layer 51 to expose the part re-wiring layer 1.
As an example, laser boring technique can be used in the opening 511 of formation in the first plastic packaging layer 51.
As an example, the opening 511 is used to be subsequently formed the metal paste conductive pole 3, the opening 511 is positioned at can be with
As shown in Figure 8, respectively positioned at the both sides of first flip-chip 2.
In step s 6, S6 steps and Fig. 9 in Fig. 3 are referred to, using metal paste typography in the opening 511
Metal paste conductive pole 3 is formed, the metal paste conductive pole 3 electrically connects with the re-wiring layer 1.
It is dispersed in as an example, the metal paste can be metal powder granulates or metal glue-line in organic matter, this
When the metal paste be grume, the metal is repeatedly stenciled on the surface of the first capsulation material layer 51 by typography
Cream so that the metal paste fills up the opening 511.
It should be noted that the metal paste can be quickly solidified as admittedly under certain process conditions or under field conditions (factors)
State.
The utility model prepares the metal paste conductive pole 3 using metal paste typography, compared to of the prior art
Electroplating technology, which prepares metallic conduction post, has the advantages that cost is low, preparation technology is simple.
In the step s 7, S7 steps and Figure 10 in Fig. 3 are referred to, in the upper surface of the first plastic packaging layer 51 bonding the
Two flip-chips 4；Second flip-chip 4 is located at the top of first flip-chip 2, and conductive via the metal paste
Post 3 electrically connects with the re-wiring layer 1.
As shown in Figure 10, second flip-chip 4 is distributed with the 2 perpendicular storehouse of the first flip-chip so that institute
State the spacing between the first flip-chip 2 and second flip-chip 4 and reach most short, so as to shorten the first upside-down mounting core
The communication response time of piece 2 and second flip-chip 4.
In step s 8, S8 steps and Figure 11 in Fig. 3 are referred to, the is formed in the upper surface of the first plastic packaging layer 51
Two plastic packaging layers 52, the gap that the second plastic packaging layer 52 is filled up between second flip-chip 4 and the first plastic packaging layer 51,
And second flip-chip 4 is encapsulated into plastic packaging.
As an example, second modeling is formed in the upper surface of the first plastic packaging layer 51 using molded underfill technique
Sealing 52.The second plastic packaging layer 52 is formed in the upper surface of the first plastic packaging layer 51 using molded underfill technique, moulded
The gap that closure material can be promptly filled up with smooth between second flip-chip 4 and the first plastic packaging layer 51, can be with
Effectively avoid interface debonding occurring；And molded underfill will not as capillary underfill technique of the prior art by
To limitation, technology difficulty is greatly reduced, can be used for smaller joint gap, be more suitable for stacked architecture.
It should be noted that both the first plastic packaging layers 51 and the second plastic packaging layer 52 in the present embodiment are superimposed
Come as the plastic packaging layer 5 described in embodiment one.Because the material of the first plastic packaging layer 51 and the second plastic packaging layer 52 is complete
Exactly the same, after the second plastic packaging layer 52 is formed, the first plastic packaging layer 51 is overall with the second plastic packaging layer 52 to be
One layer of plastic packaging layer, i.e., the plastic packaging layer 5 described in embodiment one.
In step s 9, S9 steps and Figure 12 in Fig. 3 are referred to, removes the carrier 7 and the adhesive layer 8.
As an example, grinding technics, reduction process etc. can be used to be removed the carrier 7 and the adhesive layer 8.It is excellent
Selection of land, in the present embodiment, use and tear the mode of the adhesive layer 8 to remove the carrier 7.
In step slo, S10 steps and Figure 13 in Fig. 3 are referred to, is formed in the lower surface of the re-wiring layer 1
Soldered ball projection 6.
The technique of the soldered ball projection 6 is formed known to those skilled in the art, is not repeated herein.
In summary, the utility model provides a kind of fan-out-type wafer level packaging structure, the fan-out-type wafer-level packaging
Structure comprises at least：Re-wiring layer；First flip-chip, is bonded to the upper surface of the re-wiring layer, and with it is described heavy
New route layer electrically connects；Metal paste conductive pole, it is electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer
Connect；Second flip-chip, the upper surface of the metal paste conductive pole is bonded to, and is located at the top of first flip-chip,
Second flip-chip electrically connects via the metal paste conductive pole with the re-wiring layer；Plastic packaging layer, positioned at described heavy
The upper surface of new route layer, and fill up first flip-chip, the metal paste conductive pole, second flip-chip and institute
State the gap between re-wiring layer, and by first flip-chip, the metal paste conductive pole and the second upside-down mounting core
Piece encapsulates plastic packaging；Soldered ball projection, electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer.This reality
With in new fan-out-type wafer level packaging structure, metallic conduction post of the prior art, gold are substituted using metal paste conductive pole
Category cream conductive pole can be prepared using metal paste typography, and metal is prepared compared to electroplating technology of the prior art
Conductive pole has the advantages that cost is low, preparation technology is simple；Meanwhile in fan-out-type wafer level packaging structure of the present utility model,
First flip-chip and the perpendicular storehouse of the second flip-chip are distributed so that first flip-chip and the second upside-down mounting core
Spacing between piece reaches most short, when being responded so as to shorten the communication of first flip-chip and second flip-chip
Between.
Above-mentioned embodiment only illustrative principle of the present utility model and its effect are new not for this practicality is limited
Type.Any person skilled in the art can all enter without prejudice under spirit and scope of the present utility model to above-mentioned embodiment
Row modifications and changes.Therefore, such as those of ordinary skill in the art without departing from disclosed in the utility model
Spirit and all equivalent modifications completed under technological thought or change, should be covered by claim of the present utility model.
Claims (9)
1. a kind of fan-out-type wafer level packaging structure, it is characterised in that the fan-out-type wafer level packaging structure comprises at least：
Re-wiring layer；
First flip-chip, the upper surface of the re-wiring layer is bonded to, and is electrically connected with the re-wiring layer；
Metal paste conductive pole, electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；
Second flip-chip, the upper surface of the metal paste conductive pole is bonded to, and is located at the top of first flip-chip,
Second flip-chip electrically connects via the metal paste conductive pole with the re-wiring layer；
Plastic packaging layer, positioned at the upper surface of the re-wiring layer, and it is conductive to fill up first flip-chip, the metal paste
Gap between post, second flip-chip and the re-wiring layer, and by first flip-chip, the metal paste
Conductive pole and second flip-chip enveloping plastic packaging；
Soldered ball projection, electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer.
2. fan-out-type wafer level packaging structure according to claim 1, it is characterised in that：The re-wiring layer at least wraps
Include：
First dielectric layer；
Metallic stacked structure, in first dielectric layer, the metallic stacked structure includes the metal of Spaced arrangement
Line layer and metal plug, the metal plug is between the adjacent metal line layer, by adjacent metal line layer electricity
Connection；
Lower metal layer, electrically connected positioned at the upper surface of first dielectric layer, and with the metal line layer.
3. fan-out-type wafer level packaging structure according to claim 2, it is characterised in that：First flip-chip is at least
Including：
Bare chip；
Articulamentum, positioned at the upper surface of the bare chip；
Projection is interconnected, on the articulamentum, and the interconnection projection is realized and the bare chip by the articulamentum
It is electrically connected with；
Wherein, first flip-chip by the interconnection bump bond in the upper surface of the lower metal layer, so as to real
Now with the electric connection of the re-wiring layer.
4. fan-out-type wafer level packaging structure according to claim 3, it is characterised in that：The articulamentum comprises at least：
Multiple pads, positioned at the upper surface of the bare chip；
Second dielectric layer, it is covered in the upper surface of the bare chip and the pad；
Insulating barrier, positioned at the upper surface of second dielectric layer；
Through hole, through the insulating barrier and second dielectric layer, to expose the upper surface of the pad.
5. fan-out-type wafer level packaging structure according to claim 4, it is characterised in that：The interconnection projection is formed at institute
The upper surface of pad and covering part insulating barrier are stated, and the interconnection projection realizes the electricity with the bare chip by the pad
Property connection.
6. fan-out-type wafer level packaging structure according to claim 5, it is characterised in that：The interconnection projection is by metal
Post and be formed at the metal column upper surface metal cap composition metallic combination structure, or it is described interconnection projection be metal welding
Pellet.
7. fan-out-type wafer level packaging structure according to claim 6, it is characterised in that：The material of the metal column includes
The material of Cu or Ni, the material of the metal cap and the metal welding pellet includes tin, copper, nickel, silver-colored gun-metal or tin respectively
Based alloy.
8. the fan-out-type wafer level packaging structure according to any one of claim 4~7, it is characterised in that：Described first is situated between
Electric layer and second dielectric layer use low k dielectric.
9. the fan-out-type wafer level packaging structure according to any one of claim 1~7, it is characterised in that：The plastic packaging layer
Material include polyimides, silica gel or epoxy resin.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201720531294.XU CN206758428U (en) | 2017-05-15 | 2017-05-15 | Fan-out-type wafer level packaging structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106981467A (en) * | 2017-05-15 | 2017-07-25 | 中芯长电半导体（江阴）有限公司 | Fan-out-type wafer level packaging structure and preparation method thereof |
| CN112582284A (en) * | 2019-09-30 | 2021-03-30 | 中芯长电半导体（江阴）有限公司 | Wafer-level chip packaging structure and packaging method |
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2017
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106981467A (en) * | 2017-05-15 | 2017-07-25 | 中芯长电半导体（江阴）有限公司 | Fan-out-type wafer level packaging structure and preparation method thereof |
| CN112582284A (en) * | 2019-09-30 | 2021-03-30 | 中芯长电半导体（江阴）有限公司 | Wafer-level chip packaging structure and packaging method |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |