CN106684055A - Fan-out type wafer level encapsulation structure and preparation method thereof - Google Patents
Fan-out type wafer level encapsulation structure and preparation method thereof Download PDFInfo
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- CN106684055A CN106684055A CN201710173498.5A CN201710173498A CN106684055A CN 106684055 A CN106684055 A CN 106684055A CN 201710173498 A CN201710173498 A CN 201710173498A CN 106684055 A CN106684055 A CN 106684055A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 25
- 238000005538 encapsulation Methods 0.000 title abstract description 15
- 239000004033 plastic Substances 0.000 claims abstract description 56
- 229920003023 plastic Polymers 0.000 claims abstract description 56
- 239000010410 layer Substances 0.000 claims description 339
- 229910052751 metal Inorganic materials 0.000 claims description 165
- 239000002184 metal Substances 0.000 claims description 165
- 238000004806 packaging method and process Methods 0.000 claims description 121
- 239000000463 material Substances 0.000 claims description 55
- 238000000034 method Methods 0.000 claims description 52
- 238000002161 passivation Methods 0.000 claims description 34
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 30
- 239000012790 adhesive layer Substances 0.000 claims description 24
- 239000010949 copper Substances 0.000 claims description 21
- 229910052802 copper Inorganic materials 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052759 nickel Inorganic materials 0.000 claims description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 13
- 238000004021 metal welding Methods 0.000 claims description 12
- 239000008188 pellet Substances 0.000 claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 11
- 239000010931 gold Substances 0.000 claims description 11
- 229910052737 gold Inorganic materials 0.000 claims description 11
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- 239000000741 silica gel Substances 0.000 claims description 7
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/11019—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for protecting parts during the process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
- H01L2224/1191—Forming a passivation layer after forming the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
The invention provides a fan-out type wafer level encapsulation structure and a preparation method thereof. The encapsulation structure comprises at least a rewiring layer; at least one flip chip with a bump protection structure embedded in the upper surface of the rewiring layer and at least two first bumps formed on the upper surface of the rewiring layer; a plastic encapsulation layer of the flip chip formed on the upper surface of the rewiring layer and filled with the bump protection structure, a joint gap between the rewiring layers and the flip chip with the bump protection structure and part of the first bumps; and a second bump formed on the lower surface of the rewiring layer. The plastic encapsulation layer provides a seamless bonding and an excellent connection structure for the flip chips and the rewiring layers, the risk of boundary separations is avoided, and the reliability of the plastic encapsulation structure is increased; meanwhile the flip chips with the bump protection structures are adopted so that bumps are effectively protected and fixedly interconnected, and the interconnected bumps are prevented from losing efficacy.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, more particularly to a kind of fan-out-type wafer level packaging structure and its system
Preparation Method.
Background technology
It is more inexpensive, more reliable, faster and more highdensity circuit be integrated antenna package pursue target.In future,
Integrated antenna package will improve the integration density of various electronic devices and components by constantly reducing minimum feature size.At present, first
The method for packing for entering includes：Wafer chip level chip-scale package (Wafer Level Chip Scale Packaging,
WLCSP), fan-out-type wafer-level packaging (Fan-Out Wafer Level Package, FOWLP), flip-chip (Flip
Chip), stacked package (Package on Package, POP) etc..
Fan-out-type wafer-level packaging is a kind of embedded chip method for packing of wafer level processing, be a kind of at present input/
Output port (I/O) is more, one of the preferable Advanced Packaging method of integrated motility.Fan-out-type wafer-level packaging is compared to routine
Wafer-level packaging have the advantages that its is unique：1. I/O spacing flexibly, does not rely on chip size；2. effective nude film is only used
(die), product yield is improved；3. there is flexible 3D package paths, you can to form the figure of General Cell at top；4. have
There are preferable electrical property and hot property；5. frequency applications；6. easily in re-wiring layer (RDL) high-density wiring is realized.
At present, fan-out-type wafer-level packaging method is generally：Carrier is provided, in carrier surface adhesive layer is formed；First is situated between
Electric layer on adhesive layer photoetching, electroplate out re-wiring layer (Redistribution Layers, RDL)；Using chip bonding/
Controlled collapsible chip connec-tion is arranged on semiconductor chip on re-wiring layer；Carry out overall drying；Carry out capillary tube underfill
(CUF)；Overall drying is carried out again；Using Shooting Technique by semiconductor chip plastic packaging in capsulation material layer；Plastic packaging grinds, opens
Through hole；Filling through hole；Photoetching, electroplate out metal layer under ball；Carry out planting ball backflow, form welded ball array；Remove carrier.Its
In, the connection gap between flip-chip and re-wiring layer is needed using a large amount of capillary tube underfills for loading filler particles
Material carries out capillary tube underfill, and underfill is extremely important to the reliability of flip chip devices, and it can avoid upside-down mounting
Chip device breaks down because of the coefficient of thermal expansion mismatch (CTE) between chip and organic substrate.
However, with the development of semicon industry, above-mentioned fan-out-type wafer-level packaging method and the fan-out-type crystalline substance for obtaining
Circle class encapsulation structure cannot increasingly meet package requirements.On the one hand, technique is cumbersome, relatively costly, cannot gradually meet collection
Into the package requirements of circuit.On the other hand, with the integration density more and more higher of semiconductor device, flip-chip and rewiring
Connection gap between layer also becomes less and less, and capillary tube underfill cannot be smooth and to be rapidly flowing into these narrow
Gap, causes technology difficulty to improve；Also, the capillary tube Underfill layer 6 ' and injection molded layers in fan-out-type wafer level packaging structure
6 have contact interface, part A as shown in Figure 1, and the part is easy to occur interface debonding when effect is stressed, from
And have a strong impact on the reliability of encapsulating structure.
Therefore, how to solve the above problems, there is provided a kind of technique is simpler, it is low into more this, better reliability and more adapt to
Fan-out-type wafer level packaging structure of highly integrated device encapsulation and preparation method thereof is necessary.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of fan-out-type wafer-level packaging knot
Structure and preparation method thereof, for solving prior art in fan-out-type wafer-level packaging method technique it is loaded down with trivial details, difficulty and cost compared with
Height, and encapsulating structure Presence of an interface risk of delamination, affect the problem of reliability.
For achieving the above object and other related purposes, the present invention provides a kind of fan-out-type wafer level packaging structure, wherein,
The fan-out-type wafer level packaging structure at least includes：
Re-wiring layer；
It is bonded at least one of re-wiring layer upper surface flip-chip and the formation with projection protection structure
In at least two first projections of the re-wiring layer upper surface, the flip-chip with projection protection structure and described
First projection is realized being electrically connected with the re-wiring layer, and the top of first projection is protected higher than described with projection
The top of the flip-chip of protection structure；
It is formed at the full flip-chip with projection protection structure of filling and the institute of the re-wiring layer upper surface
State the connection gap between re-wiring layer and wrap up the flip-chip with projection protection structure and first projection
A part plastic packaging layer；And
It is formed at the second projection of the re-wiring layer lower surface.
Preferably, the re-wiring layer at least includes：
Multiple first pads；
It is covered in the first dielectric layer of the first pad upper surface and side wall；
The metal wiring layer that electric connection can be realized with first pad being formed in first dielectric layer, its
In, the metal wiring layer is single metal layer or more metal layers；
Be formed at the first dielectric layer upper surface can with the metal wiring layer realize be electrically connected with it is multiple under
Metal layer, finally gives the re-wiring layer；
Wherein, the flip-chip with projection protection structure is bonded to the upper surface of the lower metal layer, and logical
Cross the electric connection of the lower metal layer realization and the re-wiring layer.
Preferably, the flip-chip with projection protection structure at least includes：
Bare chip；
It is formed at the articulamentum of the bare chip upper surface；And
The interconnection projection being formed on the articulamentum, and the interconnection projection is naked with described by articulamentum realization
The electric connection of chip；
It is formed at the articulamentum upper surface and surrounds the passivation layer that part interconnects projection, so as to forms projection protection knot
Structure；
Wherein, the flip-chip with projection protection structure by it is described interconnection bump bond in the lower metallization
The upper surface of layer, so as to realize the electric connection with the re-wiring layer.
Preferably, the articulamentum at least includes：
It is formed at multiple second pads of the bare chip upper surface；
It is covered in second dielectric layer at the chip upper surface and each the second pad two ends；And
It is formed at the insulating barrier of the second dielectric layer upper surface.
Preferably, the interconnection projection is formed at the upper surface and covering part insulating barrier of each the second pad, and described
Interconnection projection realizes the electric connection with the bare chip by second pad.
Preferably, first projection, second projection and the interconnection projection are respectively by metal column and are formed at
The metallic combination structure of the metal cap composition of the metal column upper surface, or first projection, second projection and institute
State interconnection projection and be respectively metal welding pellet.
Preferably, the metal column adopts Cu or Ni metal materials, the metal cap and the metal welding pellet to adopt respectively
With a kind of material in stannum, copper, nickel, silver-colored gun-metal or kamash alloy.
Preferably, first dielectric layer and second dielectric layer adopt low k dielectric.
Preferably, the plastic packaging layer is using a kind of curing materials in polyimides, silica gel and epoxy resin.
For achieving the above object and other related purposes, the present invention provides a kind of preparation of fan-out-type wafer level packaging structure
Method, wherein, the preparation method of the fan-out-type wafer level packaging structure at least comprises the steps：
One carrier is provided, on the carrier adhesive layer is formed；
Re-wiring layer is formed in the upper surface of the adhesive layer；
The flip-chip with projection protection structure is prepared, is had in the upper surface bonding at least one of the re-wiring layer
There is the flip-chip of projection protection structure and form at least two first projections, the flip-chip with projection protection structure
Realize being electrically connected with the re-wiring layer with first projection, and the top of first projection has higher than described
The top of the flip-chip of projection protection structure；
The full flip-chip with projection protection structure of filling and institute are formed in the upper surface of the re-wiring layer
State the connection gap between re-wiring layer and wrap up the flip-chip with projection protection structure and first projection
A part plastic packaging layer；
Remove the carrier and the adhesive layer；
The second projection is formed in the lower surface of the re-wiring layer.
Preferably, the upper surface in the adhesive layer forms re-wiring layer, and concrete grammar is：
Multiple first pads are formed in the upper surface of the adhesive layer；
The first dielectric layer for covering the first pad upper surface and side wall is formed in the upper surface of the adhesive layer；
Being formed in first dielectric layer can realize the metal wiring layer of electric connection with first pad, its
In, the metal wiring layer is single metal layer or more metal layers；
In first dielectric layer upper surface formed can with the metal wiring layer realize be electrically connected with it is multiple under
Metal layer, finally gives the re-wiring layer；
Wherein, the flip-chip with projection protection structure is bonded to the upper surface of the lower metal layer, and logical
Cross the electric connection of the lower metal layer realization and the re-wiring layer.
Preferably, the flip-chip with projection protection structure is prepared, concrete grammar is：
A wafer is provided, the wafer at least includes several bare chips；
The articulamentum for covering all bare chip upper surfaces is formed in the upper surface of the wafer；
Interconnection projection is formed on the articulamentum, and the interconnection projection is realized and the naked core by the articulamentum
The electric connection of piece；
Formed in the upper surface of the articulamentum and surround the passivation layer that part interconnects projection；
Wafer after to forming the passivation layer carries out cutting burst, has projection protection structure to form several
Flip-chip.
Formed in the upper surface of the articulamentum and surround the passivation layer that part interconnects projection, concrete grammar is：
The passivation material of the parcel interconnection projection is formed in the upper surface of the articulamentum；
Chip thickness according to actual needs is ground to the lower surface of the wafer；
The upper surface of the passivation material is ground, until the top of the exposure interconnection projection, so as to be formed
Surround the passivation layer that part interconnects projection.
Preferably, the flip-chip with projection protection structure at least includes：Bare chip；It is formed at the bare chip
The articulamentum of upper surface；And the interconnection projection being formed on the articulamentum, and the interconnection projection passes through the articulamentum
Realize the electric connection with the bare chip；Wherein, the flip-chip with projection protection structure is convex by the interconnection
Block is bonded to the upper surface of the lower metal layer, so as to realize the electric connection with the re-wiring layer；Wherein, in described
There is the flip-chip of projection protection structure, concrete grammar is described in the upper surface bonding of re-wiring layer：
Scaling powder glue-line is formed in the upper surface of interconnection projection or the upper surface of the lower metal layer；
The position that lower metal layer described in the top alignment of the interconnection projection is located, then carries out reflow soldering, from
And make the flip-chip with projection protection structure by the interconnection bump bond in the upper table of the lower metal layer
Face.
Preferably, the metal wiring layer is using a kind of material or two or more groups in copper, aluminum, nickel, gold, silver, titanium
Condensation material.
Preferably, when the upper surface in the re-wiring layer forms the plastic packaging layer, the plastic packaging layer is by molding bottom
Portion's completion method is integrally formed, so that the connection between the flip-chip with projection protection structure and the re-wiring layer
Gap is filled full, while being wrapped the flip-chip with projection protection structure and a part for first projection
Firmly；Wherein, another part of first projection is exposed to outside the plastic packaging layer.
Preferably, the carrier is using a kind of material or two in silicon, glass, silicon oxide, ceramics, polymer and metal
Plant the composite of the above.
As described above, fan-out-type wafer level packaging structure of the present invention and preparation method thereof, has the advantages that：This
Plastic packaging layer in the encapsulating structure of invention is filled full connection gap between flip-chip and re-wiring layer and wraps up upside-down mounting core
Piece, is that seamless bonding and good connected structure are provided between flip-chip and re-wiring layer, it is to avoid interface point
The risk of layer, improves the reliability of encapsulating structure, is more suitable for highly integrated device encapsulation.Meanwhile, the present invention is adopted to be had
The flip-chip of projection protection structure, can effective protection and fixed interconnection projection, strengthen the intensity of interconnection projection, prevent stress
The problems such as interconnecting projection crack is caused when larger and causes interconnection projection failure.Also, the present invention carries out bottom using capsulation material
Portion fills, and capsulation material can be reduced with smooth and be rapidly flowing into the connection gap between flip-chip and re-wiring layer
Technology difficulty so that the connection gap between flip-chip and re-wiring layer can be less.Also, the method for the present invention is more easy to
Prepare, be conducive to simplification of flowsheet, reduces cost to improve packaging efficiency, improve integrated level and yield rate.
Description of the drawings
Fig. 1 is shown as capillary tube Underfill layer and note in the fan-out-type wafer level packaging structure of prior art of the present invention
There is the schematic diagram of contact interface between modeling layer.
Fig. 2 is shown as the fan-out-type wafer level packaging structure schematic diagram of first embodiment of the invention.
Fig. 3 is shown as in the fan-out-type wafer level packaging structure of first embodiment of the invention with projection protection structure
The structural representation of flip-chip.
Fig. 4 is shown as the flow process of the preparation method of the fan-out-type wafer level packaging structure of second embodiment of the invention and illustrates
Figure.
Fig. 5~Figure 11 is shown as what each step of fan-out-type wafer-level packaging method of second embodiment of the invention was presented
Structural representation.
Figure 12~Figure 22 is shown as in the fan-out-type wafer-level packaging method of second embodiment of the invention being made in step S3
The structural representation that each step of concrete grammar of the flip-chip of projection protection structure of getting everything ready is presented.
Component label instructions
1 carrier
2 adhesive layers
3 re-wiring layers
31 first pads
32 first dielectric layers
33 metal wiring layers
34 times metal layers
4 flip-chips with projection protection structure
10 wafers
100 bare chips
200 articulamentums
201 second pads
202 second dielectric layers
203 insulating barriers
300 metal seed layers
400 lithographic mask layers
500 interconnection projections
501 metal columns
502 metal caps
600 passivation materials
601 passivation layers
5 first projections
6 plastic packaging layers
6 ' capillary tube Underfill layers
7 second projections
S1~S6 steps
Specific embodiment
Embodiments of the present invention are illustrated below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands easily other advantages and effect of the present invention.The present invention can also pass through concrete realities different in addition
The mode of applying is carried out or applies, the every details in this specification can also based on different viewpoints with application, without departing from
Various modifications and changes are carried out under the spirit of the present invention.
Fig. 2 is referred to, the first embodiment of the present invention is related to a kind of fan-out-type wafer level packaging structure.Need explanation
Be, the diagram provided in present embodiment only illustrate in a schematic way the present invention basic conception, then in schema only show with
Relevant component rather than draw according to component count during actual enforcement, shape and size in the present invention, it is each during its actual enforcement
The kenel of component, quantity and ratio can be a kind of random change, and its assembly layout kenel be likely to it is increasingly complex.
As shown in Fig. 2 the fan-out-type wafer level packaging structure of present embodiment, it at least includes：
Re-wiring layer 3；
It is bonded at least one of the upper surface of the re-wiring layer 3 flip-chip 4 and shape with projection protection structure
At least two first projections 5 of the upper surface of re-wiring layer 3 described in Cheng Yu, the flip-chip 4 with projection protection structure
Realize being electrically connected with the re-wiring layer 3 with first projection 5, and the top of first projection 5 is higher than described
The top of the flip-chip 4 with projection protection structure；
It is formed at the full He of flip-chip 4 with projection protection structure of filling of the upper surface of the re-wiring layer 3
The connection gap and parcel flip-chip 4 and described first with projection protection structure between the re-wiring layer 3
The plastic packaging layer 6 of a part for projection 5；And
It is formed at the second projection 7 of the lower surface of the re-wiring layer 3.
In the fan-out-type wafer level packaging structure of present embodiment, plastic packaging layer 6 fills falling completely with projection protection structure
The flip-chip of connection gap and parcel with projection protection structure between cartridge chip 4 and re-wiring layer 3, on the one hand can
Interconnection portion between flip-chip 4 of the protection with projection protection structure and re-wiring layer 3, is on the other hand with projection
Seamless bonding and good connected structure are provided between the flip-chip and re-wiring layer of protection structure, with good
Packaging effect, it is to avoid the risk of interface debonding, improve the reliability of encapsulating structure, be more suitable for highly integrated device envelope
Dress, is with a wide range of applications in field of semiconductor package.Additionally, when plastic packaging layer 6 is formed, using capsulation material bottom is carried out
Portion fills, capsulation material can with it is smooth and be rapidly flowing into the flip-chip 4 with projection protection structure and re-wiring layer 3 it
Between connection gap, reduce technology difficulty, can be used in less connection gap.
In the present embodiment, please continue to refer to Fig. 2, re-wiring layer 3 at least includes：
Multiple first pads 31；
It is covered in the first dielectric layer 32 of the upper surface of the first pad 31 and side wall；
The metal line that electric connection can be realized with first pad 31 being formed in first dielectric layer 32
Layer 33, wherein, the metal wiring layer 33 is single metal layer or more metal layers；
Be formed at the upper surface of the first dielectric layer 32 can realize many of electric connection with the metal wiring layer 33
Individual lower metal layer 34, finally gives the re-wiring layer 3；
Wherein, the flip-chip 4 with projection protection structure is bonded to the upper surface of the lower metal layer 34, and
The electric connection with the re-wiring layer 3 is realized by the lower metal layer 34.
In the present embodiment, metal wiring layer 33 can be single metal layer or more metal layers.As an example, metal
Wiring layer 33 can adopt a kind of material or two or more combined materials in copper, aluminum, nickel, gold, silver, titanium.
In addition, in the present embodiment, the second projection 7 is formed at the lower surface of first pad 31, and by described
First pad 31 realizes the electric connection with re-wiring layer 3.
In the present embodiment, as shown in figure 3, the flip-chip 4 with projection protection structure at least includes：
Bare chip 100；
It is formed at the articulamentum 200 of the upper surface of the bare chip 100；And
The interconnection projection 500 being formed on the articulamentum 200, and the interconnection projection 500 passes through the articulamentum 200
Realize the electric connection with the bare chip 100；
It is formed at the upper surface of articulamentum 200 and surrounds the passivation layer 601 that part interconnects projection 500, protects so as to form projection
Protection structure；
Wherein, the flip-chip 4 with projection protection structure is bonded to the lower gold by the interconnection projection 500
The upper surface of categoryization layer 34, so as to realize the electric connection with the re-wiring layer 3.Plastic packaging layer 6 is filled and completely protected with projection
Connection gap between the flip-chip 4 and re-wiring layer 3 of protection structure such that it is able to which effective protection has projection protection structure
Flip-chip 4 in not passivated layer 601 surround protection interconnection projection 500 top.
Wherein, the articulamentum at least includes：
It is formed at multiple second pads 201 of the upper surface of the bare chip 100；
It is covered in the upper surface of the bare chip 100 and second dielectric layer 202 at each two ends of the second pad 201；And
It is formed at the insulating barrier 203 of the upper surface of the second dielectric layer 202.
Wherein, the interconnection projection 500 is formed at the upper surface and covering part insulating barrier 203 of each the second pad 201,
And the interconnection projection 500 realizes the electric connection with the bare chip 100 by second pad 201.
As an example, insulating barrier 203 can adopt the material such as silicon dioxide or PET.
In addition, it is necessary to what is explained is, although only include two the second pads 201, two in the structural representation shown in Fig. 3
Interconnection projection 500, but Fig. 3 is only in order to specific explanations have the simple signal that the flip-chip 4 of projection protection structure drawn
Figure, in fact, the flip-chip with projection protection structure in present embodiment can be comprising multiple second pads 201, many
Individual interconnection projection 500, not with the structural representation shown in Fig. 3 to limit.
In addition, in a preferred version of present embodiment, the interconnection projection 500 is by metal column 501 and is formed
In the metallic combination structure that the metal cap 502 of the upper surface of the metal column 501 is constituted.
Specifically, interconnecting projection 500 at least includes：
It is formed at the metal column 501 of each upper surface of pad 201 and covering part insulating barrier 203；And
It is formed at the metal cap 502 of the upper surface of metal column 501.
Wherein, passivation layer 601 is suitable to form corresponding perforate by surrounding part interconnection projection 500, interconnects projection 500
A part is exposed to outside perforate, and another part is located in perforate, and the portion of the passivating layer 601 around perforate and interconnection projection
500 are brought into close contact, and form the structure presented such as Fig. 1.Due to tight with the portion of the passivating layer 601 of interconnection projection 500 joint place
Surround interconnection projection 500, thus passivation layer 601 can effective protection and fixed interconnection projection 500, strengthen interconnection projection 500
Intensity, prevents from the problems such as interconnecting 500 crack of projection being caused when stress is larger and causing interconnection projection failure.It is preferred as one
Scheme, passivation layer 601 surrounds metal column 501, i.e.,：Portion of the passivating layer 601 around perforate is surrounded interconnection projection 500 and is wrapped
The metal column 501 for containing, and be fitted tightly on the outer wall of metal column 501, so, metal cap 502 is on the one hand completely exposed,
Do not interfere with metal cap 502 to be bonded with external substrate, the comprehensive surrounding metal column 601 of another aspect passivation layer 601, can be interconnection
Projection 500 provides more preferable support force, so as to improve the intensity of interconnection projection 500, makes interconnection projection 500 more firm, anti-failure
Effect is also more preferable.Certainly, in other implementations, passivation layer 601 can also only surround part metals post 501.
And first projection 5 and second projection 7 can also be adopted and interconnection projection 500 identical metallic combination knot
Structure.In first projection 5 it is by metal column 501 and is formed at the gold that the metal cap 502 of the upper surface of the metal column 501 is constituted
During category combinative structure, the plastic packaging layer 6 wraps up the metal post part of first projection 5, and the metal cap part of the first projection 5 is sudden and violent
It is exposed to outside plastic packaging layer 6.
As an example, metal column 501 can adopt Cu or Ni metal materials.Wherein, metal column 501 preferably adopts Cu posts.
As an example, metal cap 502 can adopt a kind of material in stannum, copper, nickel, silver-colored gun-metal or kamash alloy
Material, including but not limited to this.
And in another scheme of present embodiment, the interconnection projection 500 can also be metal welding pellet (solder
ball).And first projection 5 and second projection 7 can also be metal welding pellet.It is metal in first projection 5
During solder ball, the plastic packaging layer 6 wraps up a part for first projection 5, and the top of the first projection 5 is exposed to outside plastic packaging layer 6,
The tip height of the first projection 5 being exposed to outside plastic packaging layer 6 can be adjusted as needed.
As an example, metal welding pellet can adopt a kind of material in stannum, copper, nickel, silver-colored gun-metal or kamash alloy
Material, including but not limited to this.
It is only the scheme of metal welding pellet relative to first projection 5, first projection 5 combines metal for metal column
The scheme of cap is more beneficial for saving package area.
In the present embodiment, the first dielectric layer 32 and the second dielectric layer 202 adopt low k dielectric.As an example,
First dielectric layer 32 and the second dielectric layer 202 can using epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and
A kind of material in fluorine-containing glass.
As an example, plastic packaging layer 6 is using a kind of curing materials in polyimides, silica gel and epoxy resin.
The plastic packaging layer 6 not only acts as the effect of the flip-chip 4 with projection protection structure described in plastic packaging, and it combines institute
State the first projection 5, it is possible to achieve stack type package.
Additionally, the fan-out-type wafer level packaging structure of present embodiment not only has stack type package ability, it may have many
Sample packaging body binding ability.Packaging body can be bonded directly to the top of the first projection 5 being exposed to outside plastic packaging layer 6, it is also possible to
The second projection is bonded directly to, packaging efficiency is improved, encapsulation process is also simpler, so as to reduces cost.Wherein, encapsulate
Body can Selective type and bonding position as needed, so as to meet various application demand.
Therefore, the encapsulating structure fan-out-type wafer scale of present embodiment is completely protected by the filling of plastic packaging layer with projection
The flip-chip of connection gap and parcel with projection protection structure between the flip-chip and re-wiring layer of protection structure, be
Seamless bonding and good connected structure are provided between flip-chip with projection protection structure and re-wiring layer,
The risk of interface debonding is avoided, the reliability of encapsulating structure is improve, with good packaging effect, is more suitable for highly integrated
Degree device encapsulation, is with a wide range of applications in field of semiconductor package.Also, underfill is carried out using capsulation material,
Capsulation material can be with connection that is smooth and being rapidly flowing between the flip-chip with projection protection structure and re-wiring layer
Gap, reduces technology difficulty so that the connection gap between the flip-chip with projection protection structure and re-wiring layer
Can be less.Additionally, the flip-chip with projection protection structure in present embodiment, by setting up on the surface of chip 100
The passivation layer 601 of interconnection projection 500 is surrounded, so as to form projection protection structure, being capable of effective protection and fixed interconnection projection
500, strengthen the intensity of interconnection projection 500, prevent from the problems such as interconnecting 500 crack of projection being caused when stress is larger and causing interconnection convex
Block 500 fails.
Fig. 4-Figure 10 is referred to, second embodiment of the invention is related to a kind of preparation side of fan-out-type wafer level packaging structure
Method, for preparing the fan-out-type wafer level packaging structure involved by first embodiment of the invention.
As shown in figure 4, the preparation method of the fan-out-type wafer level packaging structure of present embodiment at least comprises the steps：
Step S1 a, there is provided carrier 100, forms adhesive layer, as shown in Figure 5 on the carrier.
In the present embodiment, carrier 1 provides rigid for follow-up adhesive layer 2, re-wiring layer 3, plastic packaging layer 6 etc. of making
Structure or matrix.As an example, carrier 100 can adopt the one kind in silicon, glass, silicon oxide, ceramics, polymer and metal
Material or two or more composites, its shape can be wafer shape, square or other any required forms.
In the present embodiment, adhesive layer 2 in subsequent technique as the stratum disjunctum between re-wiring layer 3 and carrier 1,
It is preferably made from the jointing material with smooth finish surface, and it must have certain adhesion with re-wiring layer 3, to protect
Situations such as demonstrate,proving the re-wiring layer 3 and will not produce mobile in subsequent technique, in addition, its also have with the carrier 1 it is stronger
Adhesion, in general, its adhesion with the carrier 1 is needed more than the adhesion with the re-wiring layer 3.As
Example, the material of the adhesive layer 2 is selected from the two-sided adhesive tape for being respectively provided with viscosity or the adhesive glue by spin coating proceeding making etc..Institute
Adhesive tape is stated preferably using UV adhesive tapes, it is easy to pull off after UV light irradiations.In other embodiments, the adhesive layer 2
Also the other materials layer that physical vaporous deposition or chemical vapour deposition technique refer to, such as epoxy resin (Epoxy), silicon rubber be can select
Glue (silicone rubber), polyimides (PI), polybenzoxazoles (PBO), benzocyclobutene (BCB) etc..In later separation
During the carrier 1, the adhesive layer 2 can be removed using methods such as wet etching, cmps.
Step S2, forms re-wiring layer 3, as shown in Figure 6 in the upper surface of the adhesive layer 2.
Step S3, prepares the flip-chip with projection protection structure, is bonded in the upper surface of the re-wiring layer
Few one flip-chip with projection protection structure simultaneously forms at least two first projections, described with projection protection structure
Flip-chip and first projection are realized being electrically connected with the re-wiring layer, and the top of first projection is higher than
The top of the flip-chip with projection protection structure, as shown in Figure 7 and Figure 8.
In the present embodiment, the concrete grammar of step S2 is：
Step S201, in the upper surface of the adhesive layer 2 multiple first pads 31 are formed.
Step S202, forms in the upper surface of the adhesive layer 2 and covers the of the upper surface of the first pad 31 and side wall
One dielectric layer 32.
Step S203, being formed in first dielectric layer 32 can realize the gold of electric connection with first pad 31
Category wiring layer 33, wherein, the metal wiring layer 33 is single metal layer or more metal layers.
Step S204, forms and can realize electrically with the metal wiring layer 33 in the upper surface of first dielectric layer 32
The multiple lower metal layer 34 of connection, finally gives the re-wiring layer 3, as shown in Figure 6；Wherein, it is described to protect with projection
The flip-chip 4 of protection structure is bonded to the upper surface of the lower metal layer 34, and by the lower metal layer 34 realize with
The electric connection of the re-wiring layer 3, as shown in Figure 7.
As an example, the first pad 31 can adopt a kind of material or two or more in copper, aluminum, nickel, gold, silver, titanium
Combined material.
In the present embodiment, metal wiring layer 201 can be single metal layer or more metal layers, and more metal layers can
Obtained by the way of the first dielectric layer and metal level using alternately preparing.As an example, metal wiring layer 201 can using copper, aluminum,
A kind of material or two or more combined materials in nickel, gold, silver, titanium, and can select physical vaporous deposition (PVD), chemistry
At least one method in vapour deposition process (CVD), sputtering method, plating and chemical plating is formed.
In the present embodiment, the first dielectric layer 32 adopts low k dielectric.As an example, the first dielectric layer 32 can be with
Using a kind of material in epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass, it is possible to adopt
The techniques such as spin coating, CVD, plasma enhanced CVD form the first dielectric layer.
As an example, lower metal layer (Under Bump Metallization, UBM) 34 can be by one layer of conductive layer
Constitute, or be made up of plurality of conductive layers, conductive layer can adopt a kind of material or two in copper, aluminum, nickel, gold, silver, titanium
Plant the combined material of the above, it is possible to prepare using PVD, CVD, plating, chemical deposit or other metal deposition process.
As shown in figure 3, the flip-chip 4 with projection protection structure at least includes：Bare chip 100；It is formed at institute
State the articulamentum 200 of the upper surface of bare chip 100；And the interconnection projection 500 being formed on the articulamentum 200, and it is described mutual
Connection projection 500 realizes the electric connection with the bare chip 100 by the articulamentum 200；Wherein, it is described with projection protection
The flip-chip 4 of structure is bonded to the upper surface of the lower metal layer 34 by the interconnection projection 500, so as to realize and institute
State the electric connection of re-wiring layer 3.Wherein, the upper surface bonding in the re-wiring layer in step S3 is described with convex
The flip-chip of block protection structure, concrete grammar is：
Scaling powder glue-line is formed in the upper surface of interconnection projection 500 or the upper surface of the lower metal layer 34；
The position that lower metal layer 34 described in the top alignment of the interconnection projection 500 is located, then carries out Reflow Soldering
Connect, so that the flip-chip 4 with projection protection structure is bonded to the lower metallization by the interconnection projection 500
The upper surface of layer 34.
It is to be understood that scaling powder glue-line can remove interconnection projection 500 and the oxidation on the lower surface of metal layer 34
Layer, improves the wetting effect of solder flux and the reliability of engagement.Scaling powder glue-line can be formed using modes such as dipping or sprayings,
Should be as thin as possible and uniform.
In addition, the flip-chip 4 with projection protection structure can include various circuit structures, and in the present embodiment, can
To be bonded the flip-chip 4 with projection protection structure of multiple same types, it is also possible to be bonded and multiple different types of have
The flip-chip 4 of projection protection structure, can be selected as needed.When multiple flip-chips 4 with projection protection structure
It is highly inconsistent when, the top of the top of first projection 5 higher than all flip-chips 4 with projection protection structure.
The preparation method of the fan-out-type wafer level packaging structure of present embodiment makes on the carrier 1 first re-wiring layer
3, then the flip-chip 4 with projection protection structure is connected with re-wiring layer 3 again, it is to avoid during traditional plastic packaging because
Contraction in capsulation material heat curing process causes the problem that chip shifts with re-wiring layer, greatly improved good
Rate.
Step S4, in the upper surface of the re-wiring layer 3 the full upside-down mounting with projection protection structure of filling is formed
The connection gap and parcel flip-chip 4 with projection protection structure and institute between chip 4 and the re-wiring layer 3
The plastic packaging layer 6 of a part for the first projection 5 is stated, as shown in Figure 9.
Wherein, when the upper surface in the re-wiring layer 3 forms the plastic packaging layer 6, the plastic packaging layer 6 is by molding bottom
Portion's completion method is integrally formed, so that the company between the flip-chip 4 with projection protection structure and the re-wiring layer 3
Seam gap is filled full, while making the part quilt of the flip-chip 4 with projection protection structure and first projection 5
Wrap, and another part (tip portion) of first projection 5 is exposed to outside the plastic packaging layer 6.Plastic packaging layer 6 is on the one hand
The interconnection projection 500 between the flip-chip 4 with projection protection structure and re-wiring layer 3 can be protected, is on the other hand
Seamless bonding and good engagement knot are provided between flip-chip 4 with projection protection structure and re-wiring layer 3
Structure, with good packaging effect, it is to avoid the risk of interface debonding, improves the reliability of encapsulating structure, is more suitable for height
Integrated level device is encapsulated, and is with a wide range of applications in field of semiconductor package.Additionally, when plastic packaging layer 6 is formed, using modeling
Closure material carries out molded underfill, and capsulation material can be with smooth and be rapidly flowing into the flip-chip with projection protection structure
Connection gap between 4 and re-wiring layer 3, will not be restricted as the capillary tube underfill of prior art,
Technology difficulty is reduced, can be used in less connection gap, be more suitable for stacked architecture.
As an example, plastic packaging layer 6 can adopt a kind of curing materials in polyimides, silica gel and epoxy resin, and
The formation of plastic packaging layer 6 can adopt spin coating proceeding, Shooting Technique, compressing and forming process, typography, transfer modling technique, liquid
Body sealant cures moulding process and vacuum lamination process etc..Plastic packaging layer 6 can also be effectively ensured with projection protection structure
Flip-chip 4 receive outside contamination.
As an example, by the thickness for controlling the moulding process of plastic packaging layer 6 to control plastic packaging layer 6, without the need for subsequently carrying out again
Thinning its thickness of grinding technics, greatlys save process costs.
In the present embodiment, the top of first projection 5 is exposed to outside plastic packaging layer, can as needed Direct Bonding it is each
Kind of packaging body, it is to avoid the thinning and laser beam drilling process of plastic packaging layer, not only saves material, reduces pollution, it also avoid
Thinning process causes the damage of circuit structure.
Step S5, removes the carrier 1 and the adhesive layer 2, exposes the lower surface of re-wiring layer 3, that is, expose first
The lower surface of pad 31, as shown in Figure 10.
As an example, carrier 1 can be removed using grinding technics, reduction process etc..
Step S6, in the lower surface of the re-wiring layer 3 the second projection 7 is formed, and the second projection 7 is formed at described first
The lower surface of pad 31, and the electric connection with re-wiring layer 3 is realized by first pad 31, as shown in figure 11.
In addition, in a preferred version of present embodiment, the interconnection projection 500 is by metal column 501 and is formed
In the metallic combination structure that the metal cap 502 of the upper surface of the metal column 501 is constituted.And first projection 5 and described second
Projection 7 can also be adopted and the interconnection identical metallic combination structure of projection 500.First projection 5 be by metal column 501 and
When being formed at the metallic combination structure of the composition of metal cap 502 of the upper surface of the metal column 501, the plastic packaging layer 6 wraps up described
The metal post part of the first projection 5, the metal cap part of the first projection 5 is exposed to outside plastic packaging layer 6.
As an example, metal column 501 can adopt Cu or Ni metal materials.Wherein, metal column 501 preferably adopts Cu posts.
The metal column 501 can be formed by techniques such as conventional thick photoresistance photoetching, development, metal deposits, can also pass through micro-embossing, gold
The techniques such as category deposition form the metal column 501.
As an example, metal cap 502 can adopt a kind of material in stannum, copper, nickel, silver-colored gun-metal or kamash alloy
Material, including but not limited to this.
And in another scheme of present embodiment, the interconnection projection 500 can also be metal welding pellet (solder
ball).And first projection 5 and second projection 7 can also be metal welding pellet.It is metal in first projection 5
During solder ball, the plastic packaging layer 6 wraps up a part for first projection 5, and the top of the first projection 5 is exposed to outside plastic packaging layer 6,
The tip height of the first projection 5 being exposed to outside plastic packaging layer 6 can be adjusted as needed.
As an example, metal welding pellet can adopt a kind of material in stannum, copper, nickel, silver-colored gun-metal or kamash alloy
Material, including but not limited to this.
It is only the scheme of metal welding pellet relative to first projection 5, first projection 5 combines metal for metal column
The scheme of cap is more beneficial for saving package area.
In addition, in the present embodiment, respectively the flip-chip 4 with projection protection structure can be included and realize any function
Integrated circuit structure, and their thickness do not limited by the method for packing of present embodiment, can be same thickness,
It can be different-thickness.
Additionally, in the present embodiment, as shown in Figure 12~Figure 22, falling with projection protection structure is prepared in step S3
Cartridge chip, concrete grammar is：
Step A, one wafer 10 of offer, wafer 10 at least includes several bare chips 100.
Step B, form the articulamentum 200 that covers all upper surfaces of bare chip 100, such as Figure 12 in the upper surface of wafer 10
It is shown.
The concrete grammar of step B is：
Step B1, multiple second pads 201 are formed in the upper surface of wafer 10, as shown in figure 12.
Step B2, formed and cover all upper surfaces of bare chip 100 and each second pad in the upper surface of wafer 10
Second dielectric layer 202 at 201 two ends, as shown in figure 12.
Step B3, insulating barrier 203 is formed in the upper surface of the second dielectric layer 202, so as to obtain articulamentum 200, such as Figure 12
It is shown.
In the present embodiment, the second dielectric layer 202 adopts low k dielectric.As an example, the second dielectric layer 202 can
With using a kind of material in epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass.
As an example, insulating barrier 203 can adopt the material such as silicon dioxide or PET.
Step C, on articulamentum 200 formed interconnection projection 500, and interconnect projection 500 by articulamentum 200 realize with it is naked
The electric connection of chip 100, as shown in Figure 13-Figure 18.
In step C, upper surface and covering part insulating barrier that projection 500 is formed at each the second pad 201 are interconnected
203, and projection 500 is interconnected by the realization of the second pad 201 and the electric connection of bare chip 100.Wherein, the concrete side of step C
Method is：
Step C1, in the pad 201 of insulating barrier 203 and second upper surface formed metal seed layer 300, as shown in figure 13.
Step C2, on metal seed layer 300 formed with opening lithographic mask layer 400, opening exposure the second pad
201 and the metal seed layer 300 of the top of partial insulative layer 203, as shown in figure 14.
Metal column 501 is formed on step C3, the metal seed layer 300 in opening, as shown in figure 15.
Step C4, in metal column 501 upper surface formed metal cap 502, as shown in Figure 16 and Figure 17, first in metal column
501 upper surface forms metal cap material so as to metal cap 502 is formed after backflow.
Step C5, removal lithographic mask layer 400 and metal seed layer below 300, to be formed by metal column 501 and gold
The projection of the category composition of cap 502, as shown in figure 18.
As an example, when metal column 501 is formed, metal seed layer 300 of the electric plating method in opening can be adopted
Upper formation metal column 501.
As an example, metal column 501 can adopt Cu or Ni metal materials.Wherein, metal column 501 preferably adopts Cu posts.
As an example, metal cap 502 can adopt a kind of material in stannum, copper, nickel, silver-colored gun-metal or kamash alloy
Material, including but not limited to this.
Step D, formed and surround the passivation layer 601 that part interconnects projection 500 in the upper surface of articulamentum 200, such as Figure 19-figure
Shown in 21.
In the present embodiment, the concrete grammar of step D is：
Step D1, in articulamentum 200 upper surface formed parcel interconnection projection 500 passivation material 600, such as Figure 19 institutes
Show.
Step D2, the thickness of bare chip 100 according to actual needs are ground to the lower surface of wafer 10, such as Figure 20 institutes
Show.
Step D3, the upper surface to passivation material 600 are ground, until expose portion interconnection projection 500, so as to shape
The passivation layer 601 of projection 500 is interconnected into encirclement part, as shown in figure 21.
Step E, to formed passivation layer 601 after wafer 10 carry out cutting burst, to form several there is projection to protect
The flip-chip of protection structure, as shown in figure 22.In the present embodiment, cutting adopts laser cutting parameter, flame cutting technique
Or plasma cutting process, preferably cut and adopt laser cutting parameter.
Therefore, the system to the flip-chip with projection protection structure is realized by above-mentioned steps A~step E
It is standby.Wherein, passivation layer 601 forms corresponding perforate when part interconnection projection 500 is surrounded, and the part for interconnecting projection 500 is sudden and violent
It is exposed at outside perforate, another part is located in perforate, and the portion of the passivating layer 601 around perforate is tight with interconnection projection 500
Laminating, forms the structure presented such as Fig. 1.Due to closely surrounding interconnection with the portion of the passivating layer 601 of interconnection projection 500 joint place
Projection 500, thus passivation layer 601 can effective protection and fixed interconnection projection 500, strengthen the intensity of interconnection projection 500, prevent
The problems such as interconnecting 500 crack of projection is caused when stress is larger and causes projection to fail.As a preferred scheme, the passivation
Layer 601 surrounds the metal column 501, i.e.,：Portion of the passivating layer 601 around perforate surrounds what interconnection projection 500 was included
Metal column 501, and be fitted tightly on the outer wall of metal column 501, so, metal cap 502 is on the one hand completely exposed, will not
Metal cap 502 is affected to be bonded with external substrate, the comprehensive surrounding metal column 601 of another aspect passivation layer 601 can be interconnection projection
500 provide more preferable support force, so as to improve the intensity of interconnection projection 500, make interconnection projection 500 more firm, anti-failure effect
Also it is more preferable.Certainly, in other implementations, the passivation layer 601 can also only surround part metals post 501.
The preparation method of the flip-chip with projection protection structure of present embodiment, can simultaneously prepare several
The flip-chip with projection protection structure involved by invention first embodiment, process is simple, low cost；Simultaneously as
Projection is protected using passivation layer 601, in the back-end process for preparing flip-chip, stickup is eliminated and is removed the step such as protecting film
Suddenly, technique is simpler, and further saves cost.
By above-mentioned steps S1~step S6, making has obtained the fan-out-type wafer involved by first embodiment of the invention
Class encapsulation structure.Wherein, the plastic packaging layer 6 not only acts as the effect of the flip-chip 4 with projection protection structure described in plastic packaging,
It combines first projection 5, it is possible to achieve stack type package.Additionally, the fan-out-type wafer level packaging structure of present embodiment
Not only there is stack type package ability, it may have various packaging body binding ability.Packaging body can be bonded directly to and be exposed to modeling
The top of the first projection 5 outside sealing 6, it is also possible to be bonded directly to the second projection, packaging efficiency is improved, encapsulation process
Also it is simpler, so as to reduces cost.Wherein, packaging body can Selective type and bonding position as needed, it is various so as to meet
Application demand.
Therefore, the preparation method of the fan-out-type wafer level packaging structure of present embodiment is more easy to prepare, relative to existing
There is the preparation method in technology, enormously simplify technological process, reduce totle drilling cost, improve packaging efficiency, improve integrated
Degree and yield rate.
Above the step of various methods divide, be intended merely to description it is clear, can merge into when realizing a step or
Some steps are split, multiple steps are decomposed into, as long as comprising identical logical relation, all in the protection domain of this patent
It is interior；To either adding inessential modification in algorithm in flow process or introducing inessential design, but its algorithm is not changed
With the core design of flow process all in the protection domain of the patent.
It is seen that, present embodiment is the method embodiment corresponding with first embodiment, first embodiment
In the relevant technical details mentioned in the present embodiment still effectively, in order to reduce repetition, repeat no more here.
In sum, the full company between flip-chip and re-wiring layer of plastic packaging layer filling in encapsulating structure of the invention
Seam gap simultaneously wraps up flip-chip, is that seamless bonding and good engagement are provided between flip-chip and re-wiring layer
Structure, it is to avoid the risk of interface debonding, improves the reliability of encapsulating structure, is more suitable for highly integrated device encapsulation.Together
When, the present invention using the flip-chip with projection protection structure, can effective protection and fixed interconnection projection, strengthen interconnection convex
The intensity of block, prevents from the problems such as interconnecting projection crack being caused when stress is larger and causing interconnection projection failure.Also, the present invention is adopted
Carry out underfill with capsulation material, capsulation material can be with smooth and be rapidly flowing between flip-chip and re-wiring layer
Connection gap, reduces technology difficulty so that the connection gap between flip-chip and re-wiring layer can be less.Also,
The method of the present invention is more easy to prepare, and is conducive to simplification of flowsheet, and reduces cost improves packaging efficiency, improve integrated level and into
Product rate.So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The principle and its effect of the above-mentioned embodiment only illustrative present invention, it is of the invention not for limiting.It is any
Those skilled in the art all can be modified or changed under the spirit and the scope without prejudice to the present invention to above-mentioned embodiment
Become.Therefore, such as those of ordinary skill in the art without departing from disclosed spirit and technological thought
Lower all completed equivalent modifications or change, should be covered by the claim of the present invention.
Claims (17)
1. a kind of fan-out-type wafer level packaging structure, it is characterised in that the fan-out-type wafer level packaging structure at least includes：
Re-wiring layer；
It is bonded at least one of the re-wiring layer upper surface there is the flip-chip of projection protection structure and institute is formed at
State at least two first projections of re-wiring layer upper surface, the flip-chip with projection protection structure and described first
Projection is realized being electrically connected with the re-wiring layer, and the top of first projection is tied higher than described with projection protection
The top of the flip-chip of structure；
It is formed at the filling flip-chip with projection protection structure of the re-wiring layer upper surface and described heavy
One of connection gap and the parcel flip-chip with projection protection structure and first projection between new route layer
Partial plastic packaging layer；And
It is formed at the second projection of the re-wiring layer lower surface.
2. fan-out-type wafer level packaging structure according to claim 1, it is characterised in that the re-wiring layer is at least wrapped
Include：
Multiple first pads；
It is covered in the first dielectric layer of the first pad upper surface and side wall；
The metal wiring layer that electric connection can be realized with first pad being formed in first dielectric layer, wherein,
The metal wiring layer is single metal layer or more metal layers；
It is formed at the multiple lower metal that electric connection can be realized with the metal wiring layer of the first dielectric layer upper surface
Change layer, finally give the re-wiring layer；
Wherein, the flip-chip with projection protection structure is bonded to the upper surface of the lower metal layer, and by institute
State the electric connection of lower metal layer realization and the re-wiring layer.
3. fan-out-type wafer level packaging structure according to claim 2, it is characterised in that described with projection protection structure
Flip-chip at least include：
Bare chip；
It is formed at the articulamentum of the bare chip upper surface；And
The interconnection projection being formed on the articulamentum, and the interconnection projection is by articulamentum realization and the bare chip
Electric connection；
It is formed at the articulamentum upper surface and surrounds the passivation layer that part interconnects projection, so as to forms projection protection structure；
Wherein, the flip-chip with projection protection structure passes through the interconnection bump bond in the lower metal layer
Upper surface, so as to realize the electric connection with the re-wiring layer.
4. fan-out-type wafer level packaging structure according to claim 3, it is characterised in that the articulamentum at least includes：
It is formed at multiple second pads of the bare chip upper surface；
It is covered in second dielectric layer at the chip upper surface and each the second pad two ends；And
It is formed at the insulating barrier of the second dielectric layer upper surface.
5. fan-out-type wafer level packaging structure according to claim 4, it is characterised in that the interconnection projection is formed at often
The upper surface and covering part insulating barrier of individual second pad, and the interconnection projection is naked with described by second pad realization
The electric connection of chip.
6. fan-out-type wafer level packaging structure according to claim 5, it is characterised in that first projection, described
Two projections and the interconnection projection are respectively by metal column and are formed at the metal that the metal cap of the metal column upper surface is constituted
Combinative structure, or first projection, second projection and the interconnection projection be respectively metal welding pellet.
7. fan-out-type wafer level packaging structure according to claim 6, it is characterised in that the metal column adopts Cu or Ni
Metal material, the metal cap and the metal welding pellet are respectively adopted in stannum, copper, nickel, silver-colored gun-metal or kamash alloy
A kind of material.
8. the fan-out-type wafer level packaging structure according to any one of claim 4~7, it is characterised in that described first is situated between
Electric layer and second dielectric layer adopt low k dielectric.
9. the fan-out-type wafer level packaging structure according to any one of claim 1~7, it is characterised in that the plastic packaging layer
A kind of curing materials in using polyimides, silica gel and epoxy resin.
10. a kind of preparation method of fan-out-type wafer level packaging structure, it is characterised in that the fan-out-type wafer level packaging structure
Preparation method at least comprise the steps：
One carrier is provided, on the carrier adhesive layer is formed；
Re-wiring layer is formed in the upper surface of the adhesive layer；
The flip-chip with projection protection structure is prepared, is had in the upper surface bonding at least one of the re-wiring layer convex
The flip-chip of block protection structure simultaneously forms at least two first projections, the flip-chip with projection protection structure and institute
State the first projection to realize being electrically connected with the re-wiring layer, and the top of first projection is higher than described with projection
The top of the flip-chip of protection structure；
The filling flip-chip with projection protection structure and described heavy is formed in the upper surface of the re-wiring layer
One of connection gap and the parcel flip-chip with projection protection structure and first projection between new route layer
Partial plastic packaging layer；
Remove the carrier and the adhesive layer；
The second projection is formed in the lower surface of the re-wiring layer.
The preparation method of 11. fan-out-type wafer level packaging structures according to claim 10, it is characterised in that in described viscous
The upper surface for closing layer forms re-wiring layer, and concrete grammar is：
Multiple first pads are formed in the upper surface of the adhesive layer；
The first dielectric layer for covering the first pad upper surface and side wall is formed in the upper surface of the adhesive layer；
Being formed in first dielectric layer can realize the metal wiring layer of electric connection with first pad, wherein, institute
Metal wiring layer is stated for single metal layer or more metal layers；
Being formed in the upper surface of first dielectric layer can realize the multiple lower metal of electric connection with the metal wiring layer
Change layer, finally give the re-wiring layer；
Wherein, the flip-chip with projection protection structure is bonded to the upper surface of the lower metal layer, and by institute
State the electric connection of lower metal layer realization and the re-wiring layer.
The preparation method of the 12. fan-out-type wafer level packaging structures according to claim 10 or 11, it is characterised in that prepare
Flip-chip with projection protection structure, concrete grammar is：
A wafer is provided, the wafer at least includes several bare chips；
The articulamentum for covering all bare chip upper surfaces is formed in the upper surface of the wafer；
Interconnection projection is formed on the articulamentum, and the interconnection projection is realized and the bare chip by the articulamentum
It is electrically connected with；
Formed in the upper surface of the articulamentum and surround the passivation layer that part interconnects projection；
Wafer after to forming the passivation layer carries out cutting burst, to form several upside-down mountings with projection protection structure
Chip.
The preparation method of 13. fan-out-type wafer level packaging structures according to claim 12, it is characterised in that in the company
The upper surface for connecing layer forms the passivation layer for surrounding part interconnection projection, and concrete grammar is：
The passivation material of the parcel interconnection projection is formed in the upper surface of the articulamentum；
Chip thickness according to actual needs is ground to the lower surface of the wafer；
The upper surface of the passivation material is ground, until the top of the exposure interconnection projection, so as to form encirclement
Part interconnects the passivation layer of projection.
The preparation method of 14. fan-out-type wafer level packaging structures according to claim 11, it is characterised in that described to have
The flip-chip of projection protection structure at least includes：Bare chip；It is formed at the articulamentum of the bare chip upper surface；And formed
Interconnection projection on the articulamentum, and the interconnection projection realizes electrically connecting with the bare chip by the articulamentum
Connect；Wherein, the flip-chip with projection protection structure passes through the interconnection bump bond in the lower metal layer
Upper surface, so as to realize the electric connection with the re-wiring layer；Wherein, the upper surface in the re-wiring layer is bonded institute
The flip-chip with projection protection structure is stated, concrete grammar is：
Scaling powder glue-line is formed in the upper surface of interconnection projection or the upper surface of the lower metal layer；
The position that lower metal layer described in the top alignment of the interconnection projection is located, then carries out reflow soldering, so that
The flip-chip with projection protection structure is by the interconnection bump bond in the upper surface of the lower metal layer.
The preparation method of 15. fan-out-type wafer level packaging structures according to claim 11, it is characterised in that the metal
Wiring layer is using a kind of material or two or more combined materials in copper, aluminum, nickel, gold, silver, titanium.
The preparation method of 16. fan-out-type wafer level packaging structures according to claim 10, it is characterised in that described heavy
When the upper surface of new route layer forms the plastic packaging layer, the plastic packaging layer is integrally formed by molded underfill method, so that institute
The connection gap stated between the flip-chip with projection protection structure and the re-wiring layer is filled full, while making described
A part for flip-chip with projection protection structure and first projection is wrapped；Wherein, first projection
Another part is exposed to outside the plastic packaging layer.
The preparation method of 17. fan-out-type wafer level packaging structures according to claim 10, it is characterised in that the carrier
A kind of material or two or more composites in using silicon, glass, silicon oxide, ceramics, polymer and metal.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107195607A (en) * | 2017-07-03 | 2017-09-22 | 京东方科技集团股份有限公司 | A kind of chip packaging method and chip-packaging structure |
| CN107393910A (en) * | 2017-07-05 | 2017-11-24 | 中芯长电半导体（江阴）有限公司 | Fan-out-type system-in-package structure and preparation method thereof |
| CN112985471A (en) * | 2021-04-30 | 2021-06-18 | 深圳市汇顶科技股份有限公司 | Capacitive sensor and manufacturing method thereof |
| WO2022052072A1 (en) * | 2020-09-11 | 2022-03-17 | 华为技术有限公司 | Fan-out type packaging structure and production method therefor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102496605A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Wafer level packaging structure |
| US20150214145A1 (en) * | 2012-01-12 | 2015-07-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect Structure and Method of Fabricating Same |
| CN105225965A (en) * | 2015-11-03 | 2016-01-06 | 中芯长电半导体（江阴）有限公司 | A kind of fan-out package structure and preparation method thereof |
| CN206564245U (en) * | 2017-03-22 | 2017-10-17 | 中芯长电半导体（江阴）有限公司 | A kind of fan-out-type wafer level packaging structure |
-
2017
- 2017-03-22 CN CN201710173498.5A patent/CN106684055A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102496605A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Wafer level packaging structure |
| US20150214145A1 (en) * | 2012-01-12 | 2015-07-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect Structure and Method of Fabricating Same |
| CN105225965A (en) * | 2015-11-03 | 2016-01-06 | 中芯长电半导体（江阴）有限公司 | A kind of fan-out package structure and preparation method thereof |
| CN206564245U (en) * | 2017-03-22 | 2017-10-17 | 中芯长电半导体（江阴）有限公司 | A kind of fan-out-type wafer level packaging structure |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107195607A (en) * | 2017-07-03 | 2017-09-22 | 京东方科技集团股份有限公司 | A kind of chip packaging method and chip-packaging structure |
| CN107195607B (en) * | 2017-07-03 | 2020-01-24 | 京东方科技集团股份有限公司 | Chip packaging method and chip packaging structure |
| CN107393910A (en) * | 2017-07-05 | 2017-11-24 | 中芯长电半导体（江阴）有限公司 | Fan-out-type system-in-package structure and preparation method thereof |
| WO2022052072A1 (en) * | 2020-09-11 | 2022-03-17 | 华为技术有限公司 | Fan-out type packaging structure and production method therefor |
| CN112985471A (en) * | 2021-04-30 | 2021-06-18 | 深圳市汇顶科技股份有限公司 | Capacitive sensor and manufacturing method thereof |
| CN112985471B (en) * | 2021-04-30 | 2021-11-02 | 深圳市汇顶科技股份有限公司 | Capacitive sensor and manufacturing method thereof |
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