CN106449611A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN106449611A
CN106449611A CN201610648773.XA CN201610648773A CN106449611A CN 106449611 A CN106449611 A CN 106449611A CN 201610648773 A CN201610648773 A CN 201610648773A CN 106449611 A CN106449611 A CN 106449611A
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China
Prior art keywords
block
semiconductor
redistribution
layer
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610648773.XA
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Chinese (zh)
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CN106449611B (en
Inventor
麦可·凯利
大卫·海纳
罗纳·休莫勒
罗杰·圣艾曼德
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Imark Technology Co
Original Assignee
Imark Technology Co
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Publication date
Priority claimed from US14/823,689 external-priority patent/US9543242B1/en
Application filed by Imark Technology Co filed Critical Imark Technology Co
Priority to CN202211201187.2A priority Critical patent/CN115632042A/en
Publication of CN106449611A publication Critical patent/CN106449611A/en
Application granted granted Critical
Publication of CN106449611B publication Critical patent/CN106449611B/en
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  • Electromagnetism (AREA)
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Provided is a semiconductor device. AS an unrestricted example, the invention provides a semiconductor package structure, and a method for manufacturing the same, including a thin re-distribution structure with slight gaps.

Description

Semiconductor device
Technical field
The invention relates to a kind of semiconductor device.
The interaction reference of related application/be incorporated by reference
This application case is relevant on January 29th, 2013 application and entitled " semiconductor device and manufacture semiconductor device Method " U.S. patent application case sequence number 13/753,120；On April 16th, 2013 application and entitled " semiconductor device with And the method that manufactures it " U.S. patent application case sequence number 13/863,457；On November 19th, 2013 application and entitled " have The well of straight-through silicon perforation-less deep semiconductor device " U.S. patent application case sequence number 14/083,779；March 18 in 2014 Day application and the U.S. patent application case sequence number 14/218,265 of entitled " semiconductor device and the method manufacturing it "；2014 The application of on June 24, in and the U.S. patent application case sequence number 14/313 of entitled " semiconductor device and the method manufacturing it ", 724；On July 28th, 2014 application and entitled " there is the semiconductor device of thin redistribution layer " U.S. patent application case sequence Number 14/444,450；On October 27th, 2014 application and the United States Patent (USP) of entitled " there is the semiconductor device of the thickness of reduction " Application case sequence number 14/524,443；On November 4th, 2014 application and entitled " mediator, its manufacture method, using its half The U.S. patent application case sequence number 14/532,532 of conductor encapsulation and the method for manufacturing this semiconductor packages "；2014 November 18 application and the U.S. patent application case sequence number 14/546 of entitled " there is the semiconductor device of the warpage of reduction ", 484；And the U.S. patent application case of on March 27th, 2015 application and entitled " semiconductor device and the method manufacturing it " Sequence number 14/671,095；Hereby here is integrally incorporated by reference the content of each of those U.S. patent application case with it.
Background technology
Current semiconductor packages and the method being used for being formed semiconductor packages are not enough, and it e.g. produces excess Cost, relatively low reliability or excessive package dimension.Through existing and traditional mode and as in subject application With reference to the comparison of the present invention being illustrated in the remainder of schema, the further limit of this kind of existing and traditional mode Will to become for having the technical ability person of technique be obvious for system and shortcoming.
Content of the invention
The various features of this content of the invention are to provide a kind of semiconductor device structure and one kind to be used for manufacturing semiconductor The method of device.As nonrestrictive example, the various features of this content of the invention are to provide various semiconductor packages And the method for manufacturing it, it is redistribution (redistribution) structure of the fine pitch thin including.
One aspect of the present invention be a kind of semiconductor device, its be including：One redistribution structure, it includes：One first Redistribution layer, it includes：One first dielectric layer, it includes one first dielectric material；And one first conduction circuit；And One second redistribution layer, it includes：One second dielectric layer, it includes a second dielectric material being different from this first dielectric material Material；And one second conduction circuit, it is electrically coupled to the circuit of this first conduction；One first semiconductor grain, it is attachment To this first redistribution layer；One second semiconductor grain, it is attached to this first redistribution layer；And the interconnection of conduction Structure, it is attached to this second redistribution layer.
Another aspect of the present invention be a kind of semiconductor device, its be including：One redistribution structure, it includes：On one The redistribution layer of side, it includes：One first dielectric layer, it includes one first dielectric material；And one first conduction circuit； And the redistribution layer below, it includes：One second dielectric layer, it includes one second dielectric material；And one second lead The circuit of electricity, it is the circuit being electrically coupled to this first conduction；One first semiconductor grain, it is attached to this redistribution knot One upper side of structure；One second semiconductor grain, it is attached to this upper side of this redistribution structure；One first molding material Material, it is each the one of at least this upper side and this first and second semiconductor grain that cover this redistribution structure Individual other cross side；One substrate, it is the substrate-side of the top including a lower side being attached to this redistribution structure；With And one second molding material, it is at least to cover substrate-side above this, a cross side of this first molding material and this is heavy One cross side of new distributed architecture.
Another aspect of the present invention is a kind of semiconductor device, and it includes：Redistribution structure, it includes：The weight of top New distribution layer, it includes：First dielectric layer, it includes the first dielectric material；And first conduction circuit；Lower section again divide Layer of cloth, it includes：Second dielectric layer, it includes one second dielectric material；And second conduction circuit, it is electrically coupled to described The circuit of the first conduction；And multiple conductive pole, it extends from the redistribution layer of described lower section and is attached to described second Conductive circuit；First semiconductor grain, it is attached to a upper side of described redistribution structure；And second semiconductor die Grain, it is attached to the described upper side of described redistribution structure.
Brief description
Appended schema be included in provide being further understood from of present invention, and be included into here and say In bright book and constitute a part for description.This schema be describe present invention example, and and illustrate together with order to Explain the various principles of present invention.In the drawings：
Figure 1A -1J is the semiconductor packages and showing a kind of example describing the various features according to present invention Plant the cross-sectional view of the method for example manufacturing semiconductor encapsulation.
Fig. 2 is the flow process of a kind of method of example of manufacture semiconductor encapsulation of the various features according to present invention Figure.
Fig. 3 A-3B is the semiconductor packages and showing a kind of example describing the various features according to present invention Plant the cross-sectional view of the method for example manufacturing semiconductor encapsulation.
Fig. 4 A-4D is the semiconductor packages and showing a kind of example describing the various features according to present invention Plant the cross-sectional view of the method for example manufacturing semiconductor encapsulation.
Fig. 5 A-5F is the semiconductor packages and showing a kind of example describing the various features according to present invention Plant the cross-sectional view of the method for example manufacturing semiconductor encapsulation.
Fig. 6 A-6D is the semiconductor packages and showing a kind of example describing the various features according to present invention Plant the cross-sectional view of the method for example manufacturing semiconductor encapsulation.
Fig. 7 A-7L is the semiconductor packages and showing a kind of example describing the various features according to present invention Plant the cross-sectional view of the method for example manufacturing semiconductor encapsulation.
Fig. 8 is the flow process of a kind of method of example of manufacture semiconductor encapsulation of the various features according to present invention Figure.
Fig. 9 is to show a kind of semiconductor packages of the example describing the various features according to present invention and a kind of system Make the cross-sectional view of the method for example of semiconductor encapsulation.
Figure 10 A-10B be the semiconductor packages shown and describe a kind of example according to the various features of present invention and A kind of cross-sectional view of the method for example manufacturing semiconductor encapsulation.
Figure 11 A-11D be the semiconductor packages shown and describe a kind of example according to the various features of present invention and A kind of cross-sectional view of the method for example manufacturing semiconductor encapsulation.
Figure 12 A-12B be the semiconductor packages shown and describe a kind of example according to the various features of present invention and A kind of cross-sectional view of the method for example manufacturing semiconductor encapsulation.
Figure 13 is semiconductor packages and the one kind showing a kind of example describing the various features according to present invention Manufacture the cross-sectional view of the method for example of semiconductor encapsulation.
Figure 14 is semiconductor packages and the one kind showing a kind of example describing the various features according to present invention Manufacture the cross-sectional view of the method for example of semiconductor encapsulation.
Figure 15 is semiconductor packages and the one kind showing a kind of example describing the various features according to present invention Manufacture the cross-sectional view of the method for example of semiconductor encapsulation.
Figure 16 is semiconductor packages and the one kind showing a kind of example describing the various features according to present invention Manufacture the cross-sectional view of the method for example of semiconductor encapsulation.
Specific embodiment
Discussion below is that the various examples by the various features providing present invention to assume those features.This kind of Example is simultaneously nonrestrictive, and the category of the therefore various features of present invention should not be necessarily limited to be provided Any specific feature of example.In the following discussion, this wording " such as ", " such as " and " example " non-limiting , and be synonymous substantially with " illustrating and nonrestrictive ", " for example and nonrestrictive " and fellow.
As utilized at this, " and/or " be represent in table row by " and/or " arbitrary in the project that added Individual or multiple.For example, " x and/or y " is the either element in the set { (x), (y), (x, y) } represent this three elements. In other words, " x and/or y " is to represent " in x and y one or both ".As another example, " x, y and/or z " is to represent this Either element in the set { (x), (y), (z), (x, y), (x, z), (y, z), (x, y, z) } of seven elements.In other words, " x, y And/or one or more in z " being to represent " x, y and z ".
Term as used herein is intended merely to describe the purpose of specific examples, thus is not intended to limit in the present invention Hold.As used herein, odd number shape is intended to also comprise multiple shapes, unless the context otherwise clear contrary pointing out.Further It will be understood that, when those terms " inclusion ", " comprising ", " having " and fellow are with, during in this description, it is to indicate The presence of described feature, integer, step, operation, assembly and/or component, but it is not excluded that one or more other features, whole Number, step, operation, the presence of assembly, component and/or its group or interpolation.
It will be appreciated that, although those terms first, second, etc. can be used in this to describe various groups Part, but these assemblies should not necessarily be limited to these terms.These terms be simply used to distinguish from an assembly and another assembly and ?.Thus, for example in a first assembly of discussion below, a first component or one first section is referred to alternatively as one second group Part, a second component or one second section, without deviating from the teaching of present invention.Similarly, various e.g. " on Side's ", " lower section ", " side " and the term in the space of fellow can by with a kind of relative in the way of and be used in distinguish an assembly and Another assembly.However, it is to be understood that be that component can be so that with being oriented in the way of different, such as semiconductor device can be turned To side, thus its " to push up " surface be horizontally toward, and its " side " surface is vertically, without deviating from the present invention The teaching held.
The various features of present invention are to provide a kind of semiconductor device or encapsulation and its a kind of manufactures (or system Make) method, it can reduce cost, promote reliability and/or the manufacturability promoting this semiconductor device.
The above feature of present invention and other feature will be in the explanations of the embodiment of following various examples In be been described by or substantially learn from this explanation.The various features of present invention now will be with reference to appended schema To be presented so that those who familiarize themselves with the technology can implement this various feature easily.
Figure 1A -1J is the semiconductor packages and showing a kind of example describing the various features according to present invention Plant the cross-sectional view of the method for example manufacturing semiconductor encapsulation.The structure shown in Figure 1A -1J can with Fig. 3 A- Similar shown in 3B, 4A-4D, 5A-5F, 6A-6D, 7A-7L, 9,10A-10B, 11A-11D, 12A-12B, 13,14,15 and 16 Structure share arbitrary or all of feature.Fig. 2 is that a kind of of the various features according to present invention manufactures semiconductor The flow chart of the method 200 of example of encapsulation.Figure 1A -1K for example can be depicted in the method 200 of Fig. 2 various steps (or Block) an example semiconductor packages.Figure 1A -1K and Fig. 2 will be discussed now together.It is noted that should The order of the block of the example of method 200 can change, without deviating from the category of this content of the invention.
The method 200 of this example can include preparing a logic crystalline substance being used for processing (for example, for encapsulating) in block 205 Circle.Block 205 may include in various manners any one come to prepare one for process logic wafer, its nonrestrictive side Formula is that here is presented.
For example, block 205 may include e.g. from supplier transport, from one manufacture position a upstream processing procedure, etc. To receive a logic wafer.This logic wafer for example can include semiconductor wafer, and it is the quasiconductor including multiple actives Crystal grain.This semiconductor grain for example can include a processor crystal grain, internal memory crystal grain, the logic crystal grain of programmable, special should With integrated-circuit die, general logic crystal grain, etc..
Block 205 for example can include forming the interconnection structure of conduction on this logic wafer.This kind of conductive mutual link Structure for example can include the pad of conduction, plane (land), projection or ball, conductive pole, etc..This formation for example can include being attached Preformed interconnection structure to this logic wafer, on this logic wafer electroplated interconnection structures, etc..
In the embodiment of an example, those conductive structures may include conductive pole (it is including copper and/or nickel) and And may include a solder cap (for example, it is including stannum and/or silver).For example, the structure including the conduction of conductive pole may include： A () underbump metallization (" UBM ") structure, it is to comprise (i) (it can by titanium-tungsten (TiW) layer that sputter is formed It is referred to as one " crystal seed layer ") and copper (Cu) layer that formed by sputter on this titanium-tungsten layer of (ii)；B () is at this The upper copper post formed by plating of UBM；And the solder layer or that (c) is formed in this copper post is formed on this Nickel dam in copper post and one is formed on the solder layer on this nickel dam.
Furthermore, in the embodiment of an example, those conductive structures may include a kind of lead and/or unleaded wafer is convex Block.For example, unleaded wafer bumps (or interconnection structure) can at least partly be formed by following：(a) shape Become a underbump metallization (UBM) structure, its be by following (i) by sputter to form a titanium (Ti) or titanium-tungsten (TiW) layer, (ii) on this titanium or titanium-tungsten layer by sputter to form a bronze medal (Cu) layer, (iii) and to borrow in this layers of copper By electroplating to form a nickel (Ni) layer；And (b) on the nickel dam of this UBM structure by plating to form a unleaded solder material Material, wherein this unleaded solder material is the composition with 1% to 4% silver (Ag) by weight, and this is by weight The remainder of composition be stannum (Sn).
Block 205 for example can include executing the part of this logic wafer or comprehensive thinning (for example, grind, etching, Etc.).Block 205 for example can also include cutting this logic wafer becomes other crystal grain or crystal grain group, for follow-up Installation.Block 205 also may include from a manufacturing facility one is adjacent or the manufacturing station of upstream, from another geographical position, Etc. receive this logic wafer.The preparation process that the logic wafer receiving can be for example having prepared or extra can Executed.
In general, block 205 may include the logic wafer that preparation one is used for processing (for example, for encapsulating).Then, this The category of content of the invention should not necessarily be limited to the feature that certain types of logic wafer and/or crystal grain are processed.
The method 200 of this example can include preparing a carrier, substrate or wafer in block 210.Prepared (or Receiving) wafer is referred to alternatively as a redistribution structure wafer or RD wafer.Block 210 may include in various manners Any one come to prepare one for process RD wafer, its nonrestrictive example is that here is presented.
This RD wafer for example can include a mediator wafer, the wafer of base plate for packaging, etc..This RD wafer is for example permissible Form (for example, in the way of crystal grain one by one) redistribution structure on semiconductor (for example, silicon) wafer including a kind of.Should RD wafer for example can only include electrical path, and does not include electronic installation (for example, semiconductor device).This RD wafer is for example also Passive electronic installation can be included, but not including that the semiconductor device of active.For example, this RD wafer may include one or more Conductive layer or circuit, it is to be formed on a substrate or carrier (for example, directly or indirectly thereon) or be coupled to a base Plate or carrier.The example of this carrier or substrate can comprise semiconductor (for example, silicon) wafer or a glass substrate.Lead in half Be used to form on body wafer conductive layer (for example, copper, aluminum, tungsten, etc.) the example of processing procedure be to comprise to utilize semiconductor crystal wafer Processing procedure, its here can also be referred to as back-end process (BEOL).In the embodiment of an example, those conductive layers can utilize One sputter and/or electroplating process come to be deposited on a thereon or on.Those conductive layers are referred to alternatively as redistributing layer.Should A little redistribution layers can be used between the machine of two or more Electricity Federations coiling one electrical signals and/or by an Electricity Federation machine coiling Become a wider or narrower spacing.
In the embodiment of an example, this redistribution structure is (for example, it is possible to be attached to the interconnection structure of electronic installation (for example, plane, circuit, etc.)) various parts can be formed having spacing (or the center to center of time micron Interval) and/or the spacing less than 2 microns.In various other embodiments, the spacing of a 2-5 micron can be sharp With.
In the embodiment of an example, the Silicon Wafer that this redistribution structure is formed on thereon may include ratio can quilt Make full use of the silicon to form the semiconductor grain lower grade being finally attached to this redistribution structure.Reality in another example Apply in mode, this Silicon Wafer can be from the Silicon Wafer reclaiming that the semiconductor device wafer of a failure manufactures.Another In the embodiment of example, this Silicon Wafer may include and is finally attached to this redistribution structure than being fully utilized to be formed The relatively thin silicon layer of semiconductor grain.Block 210 also may include from a manufacturing facility one is adjacent or the manufacturing station of upstream, From another geographical position, etc. receiving this RD wafer.The RD wafer receiving can be for example having prepared or extra Preparation process may be performed.
Figure 1A is the icon of the example of various features providing block 210.With reference to Figure 1A, this RD wafer 100A for example may be used With include a supporting layer 105 (for example, a silicon or other semiconductor layer, a glassy layer, etc.).One redistribution (RD) structure 110 can be formed on this supporting layer 105.This RD structure 110 for example can include a base dielectric layer 111, one first dielectric Layer the 113, first conducting wire 112, one second dielectric layer 116, the second conducting wire 115 and interconnection structure 117.
This base dielectric layer 111 can be for example on this supporting layer 105.This base dielectric layer 111 for example can include Monoxide layer, mononitride layer, etc..This base dielectric layer 111 for example can be formed according to specification, and/or can To be natural.Dielectric layer 111 is referred to alternatively as a protective layer.For example, dielectric layer 111 can be one utilize low pressure chemical phase sink Silicon dioxide layer that long-pending (LPCVD) processing procedure is formed or be including this silicon dioxide layer.
This RD wafer 100A for example can also include the first conducting wire 112 and one first dielectric layer 113.Those first Conducting wire 112 for example can include deposit conducting metal (for example, copper, aluminum, tungsten, etc.).Conducting wire 112 can be by Sputter and/or plating to be formed.Those conducting wires 112 for example can be at one time between micron or secondary two microns Formed under (or interval of center to center).This first dielectric layer 113 for example can include a kind of inorganic dielectric material Material (for example, Si oxide, silicon nitride, etc.).It is noted that in various embodiments, this dielectric layer 113 can be It is formed before first conducting wire 112, it is e.g. formed with hole, and those holes are then to be received in the first conductor wire Road 112 or its a part.In the embodiment of an example for example including copper conductive traces, a kind of dual damascene (dual Damascene) processing procedure can be utilized to deposit those circuits.
In the assembly of a replacement, this first dielectric layer 113 may include a kind of organic dielectric materials.For example, this first Jie Electric layer 113 may include bismaleimide/tri- nitrogen trap (bismaleimidetriazine, BT), phenol resin (phenolic resin), polyimides (PI), benzocyclobutene (benzo cyclo butene, BCB), polybenzoxazoles (poly benz oxazole, PBO), epoxy resin and its equivalent and its compound, but the feature of present invention is simultaneously Not limited to this.This organic dielectric materials any one (e.g. chemical vapor deposition, CVD) in various manners can carry out shape in addition Become.In the assembly of this kind of replacement, those first conducting wires 112 can be for example a 2-5 micron spacing (or in The interval at Xin Zhi center).
This RD wafer 100A for example can also include the second conducting wire 115 and one second dielectric layer 116.Those second Conducting wire 115 for example can include the conducting metal (for example, copper, etc.) depositing.Those second conducting wires 115 for example may be used To pass through an other conductive through hole 114 (for example, in this first dielectric layer 113) to connect to other first conducting wire 112.This second dielectric layer 116 for example can include a kind of Inorganic Dielectric Material (for example, Si oxide, silicon nitride, etc.). In the assembly of a replacement, this second dielectric layer 116 may include a kind of organic dielectric materials.For example, this second dielectric layer 116 can Including bismaleimide/tri- nitrogen trap (BT), phenol resin, polyimides (PI), benzocyclobutene (BCB), polyphenyl and dislike Azoles (PBO), epoxy resin and its equivalent and its compound, but the feature of present invention is not limited to this.This second Dielectric layer 116 for example can be formed using a CVD processing procedure, but the category of this content of the invention is not limited to this.
Although two groups of dielectric layer and conducting wire are depicted in figure ia, it should be appreciated that the RD of this RD wafer 100A Structure 110 may include any number of this kind of layer and circuit.For example, this RD structure 110 can only include a dielectric layer and/or many The conducting wire of group, three groups of dielectric layer and/or conducting wire, etc..
Such as the logic wafer preparation in block 205, block 210 may include and formed on a surface of this RD structure 110 Interconnection structure (for example, conductive projection, conducting sphere, conductive pole, conductive plane or pad, etc.).The example of this kind of interconnection structure 117 It is to be demonstrated in figure ia, wherein this RD structure 110 is including interconnection structure 117, it is to be shown as being formed at this RD structure On 110 front (or top) side, and it is to electrically couple to other the through conductive through hole in this second dielectric layer 116 Two conducting wires 115.This kind of interconnection structure 117 for example can be utilized so that this RD structure 110 is coupled to various electronic components (for example, the semiconductor component of active or crystal grain, passive component, etc.).
Those interconnection structures 117 for example can include various conductive materials any one (for example, copper, nickel, gold, etc. Any one or one combination).Those interconnection structures 117 for example can also include solder.
In general, block 210 may include preparation one redistribution structure wafer (RD wafer).Then, this content of the invention Category should not necessarily be limited to execute the feature of any ad hoc fashion of this kind of preparation.
The method 200 of this example can include being formed interconnection structure (for example, logical nib on this RD wafer in block 215 (TMV) interconnection structure).Block 215 may include in various manners any one forming this kind of interconnection structure.
Those interconnection structures may include any one of various features.For example, those interconnection structures may include solder ball or convex Block, the solder post of many spheroids, elongated solder ball, there is on a metallic core metal (for example, the copper) core of a solder layer Bulbus cordis, the rod structure (for example, copper post, etc.) of plating, conductor structure (for example, the line of wire bonding), etc..
Those interconnection structures may include any one of various sizes.For example, those interconnection structures can prolong from this RD wafer Reach the height that a height is less than being coupled to the electronic component (for example, in block 220) of this RD wafer.Equally for example, Those interconnection structures can extend to a height from this RD wafer and be greater than or equal to be coupled to the electronic component of this RD wafer Highly.It is significantly (for example, in molding thinning, envelope that the importance of this kind of relative height will become in this discussion Dress storehouse, apical substrate attachment, top are again in the discussion of formation of distributed architecture etc.).Those interconnection structures for example also may be used Formed with various spacing (or interval of center to center).For example, those interconnection structures (for example, conductive pole Or cylinder) can be electroplated under a 150-250 micron or less spacing and/or engage.Equally for example It is that those interconnection structures (solder structure that is for example, elongated and/or inserting metal) can in a 250-350 micron or more It is attached under little spacing.Equally for example, those interconnection structures (for example, solder ball) can be in a 350-450 It is attached under micron or less spacing.
Block 215 may include in various manners any one being attached those interconnection structures.For example, block 215 may include On this RD wafer reflow attachment interconnection structure, on this RD wafer electroplated interconnection structures, on this RD wafer, wire bonding is mutual Link structure, using conductive epoxy resin with by preformed interconnection structure be attached to this RD wafer, etc..
Figure 1B is the icon of the example of various features (feature that for example, interconnection structure is formed) providing block 215.? In the assembly 100B of example, interconnection structure 121 (for example, solder ball) be attached (for example, reflow attachment, utilize a solder Ball drip processing procedure to be attached, etc.) to this RD wafer 100A RD structure 110.
Although two row interconnection structures 121 be demonstrated, various embodiments may include single row, three row or Any number of row.As will be discussed herein, the embodiment of various examples can not have this kind of interconnection structure 121, And therefore block 215 can in be contained in the method 200 of example.
Although it is noted that in the method 200 of this example, this block 215 is the wafer moulding process in block 230 It is performed before, but those interconnection structures can alternatively be formed (for example, in this mould after this wafer moulding process Form perforation in prepared material and then this kind of hole is filled with conductive material).Also note that, such as institute in fig. 2 Show, block 215 for example can be executed after the die attachment operation of block 220, rather than before die attachment.
In general, block 215 may include formation interconnection structure on this RD wafer.Then, the category of this content of the invention Any ad hoc fashion that should not necessarily be limited to the feature of certain types of interconnection structure or be limited to be formed this kind of interconnection structure Feature.
The method 200 of this example can include being attached one or more semiconductor grains to this RD structure (example in block 220 As the RD structure of this RD wafer).Block 220 may include in various manners any one being attached this crystal grain to this RD structure, its Nonrestrictive example be that here is provided.
This semiconductor grain may include the feature of any one of various types of semiconductor grains.For example, this semiconductor die Grain may include a processor crystal grain, an internal memory crystal grain, an ASIC crystal grain, general logic crystal grain, active Semiconductor component, etc.).It is noted that passive component can also be attached in block 220.
Block 220 may include in various manners any one being attached this semiconductor grain (for example, as in block 205 Prepared person).For example, block 220 may include using batch reflow (mass reflow), hot press (TCB), conductive ring Oxygen tree fat, etc. being attached this semiconductor grain.
Figure 1B is the icon of the example of various features (e.g. die attachment feature) providing block 220.For example, One crystal grain 125 (for example, it can come in the logic wafer cutting of block 205 preparation from one) is electrical and mechanical It is attached to this redistribution structure 110 likes.Similarly, (for example, it can be in block 205 from one to the second crystal grain 126 The logic wafer cutting of preparation and come) be electrical and be mechanically attached to this redistribution structure 110.For example, as Block 205 is explained, and this logic wafer (or its crystal grain) can be produced has various being formed on thereon Interconnection structure (for example, conductive pad, plane, projection, ball, wafer bumps, conductive pole, etc.).This kind of structure is in fig. ib Substantially it is shown as project 119.Block 220 for example can be included using various attachment processing procedure (for example, batch reflow, hot pressing Engage (TCB), conductive epoxy resin, etc.) any one, heavy to this electrically and to be mechanically attached this kind of interconnection structure New distributed architecture 110.
This first crystal grain 125 and the second crystal grain 126 may include any one of various grain properties.In an example plot In, this first crystal grain 125 may include a processor crystal grain, and this second crystal grain 126 may include an internal memory crystal grain.In another model In example plot, this first crystal grain 125 may include a processor crystal grain, and this second crystal grain 126 may include a coprocessor Crystal grain.In another example plot, this first crystal grain 125 may include a sensor crystal grain, and this second crystal grain 126 may include One sensor processes crystal grain.Although being to be shown as thering is two crystal grain 125,126 in the assembly 100B of Figure 1B, it is permissible There is any number of crystal grain.For example, it can only have a crystal grain, three crystal grain, four crystal grain or more than four crystal grain.
Although additionally, this first crystal grain 125 and the second crystal grain 126 are to be shown as being attached to laterally relative to each other This redistribution structure 110, but they can also be configured with a vertical assembly.This kind of structure various unrestricted The example of property be here be demonstrated and discuss (for example, storehouse on crystal grain for the crystal grain, die attachment to relative substrate-side, etc. Deng).Furthermore, although this first crystal grain 125 and the second crystal grain 126 are to be shown as thering is substantially similar size, this Kind of crystal grain 125,126 may include different individual another characteristic (for example, crystal grain height, the area of coverage, connection spacing, etc.).
This first crystal grain 125 and the second crystal grain 126 are to be depicted as thering is substantially uniform spacing, but this is not necessarily If so.For example, this first crystal grain 125 is big in a region of this second crystal grain 126 of next-door neighbour of the first crystal grain area of coverage All or part of contact 119 and/or this second crystal grain 126 the second crystal grain area of coverage this first crystal grain 125 of next-door neighbour one Most contact 119 in region can have the spacing thinner than other most or all of contact 119 essence.Example If this first crystal grain 125 is near before the second crystal grain 126 (and/or this second crystal grain 126 is near first crystal grain 125) 5th, the contacts 119 of 10 or n row can have one 30 microns of spacing, and other contact 119 substantially can to have 1 micro- Rice and/or 200 microns of spacing.This RD structure 110 therefore can have the corresponding contact structures under this corresponding spacing And/or circuit.
In general, block 220 is to this redistribution structure (for example, one including one or more semiconductor grains of attachment The redistribution structure of redistribution wafer).Then, the category of this content of the invention should not necessarily be limited to any specific crystal grain Feature or be limited to the feature of layout of any specific multiple grain or be limited to be attached any specific of this kind of crystal grain The feature of mode, etc..
The method 200 of this example can include primer filling (underfilling) in block 225 and be attached in block 220 The semiconductor grain of this RD structure and/or other component.Block 225 may include in various manners any one executing this kind of bottom Glue is filled, and its nonrestrictive example is that here is presented.
For example, after the die attachment of block 220, block 225 may include and comes bottom using a kind of filling of capillary tube primer This semiconductor grain filled by glue.For example, the filling of this primer may include a kind of reinforcing polymer material glutinous enough, and it is in a capillary Flow between this attachment crystal grain and RD wafer in pipe effect.
Equally for example, block 225 may include and is just attached (for example, using a thermo-compression bonding in block 220 in this crystal grain Close processing procedure) when, using a kind of non-conductive cream (NCP) and/or a kind of non-conductive film (NCF) or bring primer to fill this semiconductor die Grain.For example, this kind of primer packing material first can be deposited before being attached this semiconductor grain (for example, printing, spraying, Etc.).
Such as all of block described in the method 200 of this example, as long as in this crystal grain and redistribution structure Between space can access, block 225 just can be executed any position in the flow process of the method 200.
The filling of this primer can also occur at a different block of the method 200 of this example.For example, this primer filling The part (for example, using a kind of molding primer filling) that block 230 can be moulded as this wafer to be executed.
Figure 1B is the icon of the example of various features (for example, the feature of this primer filling) providing block 225.This bottom Glue filling 128 is to be arranged between this first semiconductor grain 125 and redistribution structure 110 and the second half lead at this Between body crystal grain 126 and redistribution structure 110, it is, for example, around those contacts 119.
Although this primer filling 128 be substantially be depicted as flat, this primer filling can rise and at this Form fillet (fillet) on the side of semiconductor grain and/or other component.In an example plot, those crystal grain side surfaces At least a quarter or at least half can be capped this primer packing material.In another example plot, those are whole Side surface one or more or all can be capped this primer packing material.Equally for example, directly partly lead at those The portion of the essence in space between body crystal grain, between this semiconductor grain and other component and/or between other components Divide and can be received in this primer packing material.For example, between laterally adjacent semiconductor grain, in this crystal grain and other components Between and/or at least half of space between other components or whole spaces can be received in this primer filling material Material.In the embodiment of an example, this primer filling 128 can cover the whole redistribution structure 110 of this RD wafer.? In this kind of one example implementation, when cut after this RD wafer, this kind of cutting also can cut through this primer filling 128.
In general, block 225 may include primer be filled in block 220 be attached to this RD structure semiconductor grain and/ Or other component.Then, the category of this content of the invention should not necessarily be limited to any certain types of primer filling or executes this Plant the feature of any ad hoc fashion of primer filling.
The method 200 of this example can include moulding this RD wafer (for example, or a RD structure) in block 230.Block 230 may include in various manners any one moulding this RD wafer, and its nonrestrictive example is that here is presented.
For example, block 230 may include on the top surface being molded in this RD wafer, the crystal grain in block 220 attachment and/or Interconnection structure (for example, conducting sphere, ellipsoid, post or cylinder (for example, the plating being formed on other components, in block 215 Post, line or closing line etc.), etc.) on, on the primer filling that block 225 is formed, etc..
Block 230 for example can be included using compression molded (for example, it is using liquid, powder and/or film) or true Empty molding.Equally for example, block 230 may include using a transfer molding processing procedure (for example, a wafer scale transfer molding system Journey).
This molding material for example can include any one of various features.For example, this molding material (for example, epoxy molding Compound (EMC), epoxy resin mould produced compounds, etc.) may include a relatively high modulus, such as in order to the system follow-up Wafer support is provided in journey.Equally for example, this molding material may include a relatively low modulus, with the processing procedure follow-up Middle offer wafer elasticity.
As explained at this, for example, it is related to block 225, the molding processing procedure of block 230 in this crystal grain and can be somebody's turn to do Primer filling is provided between RD wafer.In this kind of example, this molding primer packing material be encapsulated this semiconductor grain Molding material between can have uniform material.
Fig. 1 C is the icon of the example of various features (for example, molded features) providing block 230.For example, molding group Part 100C is to be shown as wherein moulding material 130 to cover those interconnection structures 121, the first semiconductor grain 125, the second half lead The top surface of body crystal grain 126, primer filling 128 and redistribution structure 110.Although (its here is also for this molding material 130 It is referred to alternatively as encapsulation materials) it is shown as this first semiconductor grain 125 and second semiconductor grain 126 are completely covered Side and top, but this is not necessarily so.For example, block 230 may include using one film auxiliary or crystal grain close The molding technique of envelope, does not mould material with the top keeping crystal grain.
In general, this molding material 130 for example can with directly contact and cover those crystal grain 125,126 not by this The part of primer filling 128 covering.For example, at least one Part I in a wherein side for those crystal grain 125,126 be by In the plots of primer filling 128 covering, this molding material 130 with directly contact and can cover the side of crystal grain 125,126 One Part II.The space that this molding material 130 for example can also be filled between crystal grain 125,126 (for example, is not yet received in At least a portion in the space of primer filling 128).
In general, block 230 may include this RD wafer of molding.Then, the category of this content of the invention should not necessarily be limited to The feature of any specific molding material, structure and/or technology.
The method 200 of this example can include grinding the molding that (or thinning) is applied in block 230 in block 235 Material.Block 235 may include in various manners any one grinding (or thinning) this molding material, its nonrestrictive example Son is that here is presented.
Block 235 for example can include this molding material of mechanical polishing, with this molding material of thinning.This kind of thinning is for example This crystal grain and/or interconnection structure can be left cladding molding or this kind of thinning can expose one or more crystal grain and/ Or one or more interconnection structures.
Block 235 for example can include grinding the other components in addition to this mold compound.For example, block 235 can Including grind in block 220 attached by crystal grain tip side (for example, dorsal part or non-active side).Block 235 for example also may be used To include grinding the interconnection structure being formed in block 215.Additionally, at a bottom wherein being applied in block 225 or block 230 Glue filling is in the plot of extension enough upwards, and block 235 also may include this kind of primer packing material of grinding.This kind of grinding example The top of the material as being ground at this produces a flat plane surface.
Block 235 can be for example originally to be formed on a desired thickness in the height once wherein this molding material It is skipped in plot.
Fig. 1 D is the icon of the example of various features (for example, this molded abrasive feature) providing block 235.Assembly 100D is to be depicted as wherein this molding material 130 (for example, with respect to the molding material 130 described in Fig. 1 C) to be thinned, To expose the top surface of crystal grain 125,126.In this kind of example, this crystal grain 125,126 can also be ground (or It is thinned).
Although as painted in Fig. 1 D, the top surface of this molding material is on those interconnection structures 121, and because This interconnection structure 121 is not ground, but those interconnection structures 121 can also be ground.This kind of one example implementation is for example Can with the here stage produce a top surface be comprise crystal grain 125,126 a top surface, molding material 130 a top surface, with And a top surface of interconnection structure 121, all of top surface is all in a common plane.
As explained at this, this molding material 130 can be retained in one Overmolded (overmold) configures To cover this crystal grain 125,126.For example, this molding material 130 can not be ground or this molding material 130 can be ground Mill, but it is less than a height exposing this crystal grain 125,126.
In general, block 235 may include the molding material that grinding (or thinning) is applied in block 230.Then, The category of this content of the invention should not necessarily be limited to amount or the feature of type of any specific grinding (or thinning).
The method 200 of this example can include degrading, in block 240, the molding material being applied in block 230.Block 240 May include in various manners any one degrading this molding material, its nonrestrictive example is that here is provided.
As discussed herein, this molding material can cover the interconnection structure being formed in block 215.If this molding material Material covers interconnection structure, and those interconnection structures need to be exposed (for example, for the weight of follow-up encapsulation attachment, tip side New distribution layer formation, the laminated substrate attachment of tip side, electrical connection, radiator connection, the connection of electromagnetic shielding, etc.), then area Block 240 may include and degrades this molding material to expose those attachment structures.
Block 240 for example can include degrading using laser, to expose those interconnection structures through this molding material.Equally For example, block 240 may include using soft beam boring, mechanical type boring, chemistry boring, etc..
Fig. 1 D is the icon of the example of various features (for example, this degrades feature) providing block 240.For example, this group Part 100D is to be demonstrated to extend to the perforation 140 degrading of interconnection structure 121 including through this molding material 130.Although should The perforation 140 degrading a bit is to be shown as thering is vertical side wall, it should be appreciated that perforation 140 may include variously-shaped appointing A kind of.For example, those side walls can be that (for example, the top surface in this molding material 130 has than in interconnection structure for inclination 121 larger openings).
Although block 240 is to be depicted as immediately preceding the wafer molding of block 230 and the mould in block 235 in fig. 2 System grind after, but block 240 can in the method 200 after any point to be executed.For example, block 240 can Executed with after being removed in this wafer support structure (for example, attached by block 245).
In general, block 240 may include degrades the molding material being applied in block 230 (for example, in order to expose in area The interconnection structure that block 215 is formed).Then, the category of this content of the invention should not necessarily be limited to execute this kind of any spy degraded Determine the feature of mode or the feature being limited to any through-hole construction specifically degrading.
The method 200 of this example can include in block 245 will be attached for this molding RD wafer (for example, its top or molding side) It is connected to a wafer support structure.Block 245 may include in various manners any one this molding RD wafer is attached to this crystalline substance Circle supporting construction, its nonrestrictive example is that here is provided.
This wafer support structure for example can be included by silicon, glass or various other material (for example, dielectric material) The wafer being formed or fixing device.Block 245 for example can include using an adhesive agent, a vacuum fixture, etc. So that this molding RD wafer to be attached to this wafer support structure.It is noted that as described at this and explaining, one again Distributed architecture can this wafer holder attachment before be formed on this crystal grain and molding material tip side (or the back of the body Face) on.
Fig. 1 E is the icon of the example of various features (for example, wafer holder is attached feature) providing block 245.Brilliant Circle supporting construction 150 is the tip side being attached to this molding material 130 and crystal grain 125,126.This wafer support structure 150 Can be for example to be attached using an adhesive agent, and this kind of adhesive agent also can be formed in those perforations 140 and Contact those interconnection structures 121.In the assembly of another example, this adhesive agent is simultaneously introduced into perforation 140 and/or and not in contact with mutual Link structure 121.It is noted that being capped in the assembly of molding material 130 on the top of wherein this crystal grain 125,126, should Wafer support structure 150 may only be coupled directly to the top of this molding material 130.
In general, block 245 may include, and this molding RD wafer (for example, its top or molding side) is attached to a wafer Supporting construction.Then, the category of this content of the invention should not necessarily be limited to any certain types of wafer support structure feature or It is constrained to be attached the feature of any ad hoc fashion of a wafer support structure.
The method 200 of this example can include removing a supporting layer from this RD wafer in block 250.Block 250 may include Removing this supporting layer, its nonrestrictive example is that here is presented in various manners any one.
As discussed herein, this RD wafer may include a RD structure and is formed and/or carries a supporting layer thereon. This supporting layer for example can include a kind of semi-conducting material (for example, silicon).Include a silicon wafer layer in wherein this supporting layer In example plot, block 250 may include remove this silicon (for example, from this RD wafer remove this silicon whole, remove from this RD wafer The almost all (e.g. at least 90% or 95%) of this silicon, etc.).For example, block 250 may include this silicon of mechanical polishing Almost all, is followed by a dry type or wet chemical etch to remove remainder (or almost all of this remainder). It is block in the example plot being loosely attached to and being formed (or carrying) RD structure thereon in wherein this supporting layer 250 may include and pull open or peel off with separately this supporting layer and this RD structure.
Fig. 1 F is the icon of the example of various features (for example, supporting layer removes feature) providing block 250.For example, This supporting layer 105 (shown in fig. ie) is to be removed from this RD structure 110.In this example illustrated, this RD structure 110 still can include one as base dielectric layer discussed herein 111 (for example, monoxide, nitride, etc.).
In general, block 250 may include removes a supporting layer from this RD wafer.Then, the category of this content of the invention is not The feature of any certain types of wafer material should be limited to or be limited to any ad hoc fashion that wafer material removes Feature.
The method 200 of this example can include Jie forming and patterning one first redistribution layer (RDL) in block 255 Electric layer, for etching the monoxide layer of this RD structure.Block 255 may include in various manners any one being formed and to scheme Caseization the first RDL dielectric layer, its nonrestrictive example is that here is presented.
In the example substantially discussed in this, the RD structure of this RD wafer be generally formed on monoxide layer (or Nitride or other dielectric medium) on.For this RD structure that is attached to of enable metal to metal, this RD of the covering of this oxide skin(coating) The part of the circuit (or pad or plane) of structure may, for example, be and is removed by etching.It is noted that this oxide Layer it is not absolutely required to be removed or is removed completely, as long as it has acceptable electric conductivity.
First RDL dielectric layer for example can include polyimides or a polybenzoxazoles (PBO) material.This first RDL dielectric layer for example can include a laminated film or other materials.First RDL dielectric layer for example can generally comprise one Plant organic material.However, in various one example implementation, a RDL dielectric layer may include a kind of inorganic material.
In the embodiment of an example, a RDL dielectric layer may include a kind of substrate being formed on this RD structure Organic material on one first side of dielectric layer (for example, polyimides, PBO, etc.), this base dielectric layer may include an oxidation Thing or nitride or other dielectric material.
First RDL dielectric layer for example can be utilized as one for etch e.g. monoxide or nitride layer base The shielding (for example, in block 260) of bottom dielectric layer.Equally for example, after the etching, a RDL dielectric layer can be protected Stay, be e.g. used in the RDL circuit forming conduction thereon.
(not shown) in the example plot of a replacement, an interim screen layer (for example, an interim photoresist layer) can quilt Using.For example, after the etching, this interim screen layer can be removed, and is replaced by a permanent RDL dielectric layer.
Fig. 1 G is the icon of the example of various features providing block 255.For example, a RDL dielectric layer 171 be It is formed in this base dielectric layer 111 and pattern.First RDL dielectric layer 171 of this patterning for example can include through this The perforation 172 of the first RDL dielectric layer 171, and (for example, this base dielectric layer 111 for example can be etched through perforation 172 In block 260), and first line (or its part) can be formed in perforation 172 (for example, in block 265).
In general, block 255 may include being formed e.g. in this base dielectric layer and patterning one first dielectric layer (for example, one the oneth RDL dielectric layer).Then, the category of this content of the invention should not necessarily be limited to a specific dielectric layer feature, Or be limited to form the feature of an ad hoc fashion of a dielectric layer.
The method 200 of this example can include etching (for example, the oxidation of this base dielectric layer from this RD structure in block 260 Nitride layer, nitride layer, etc.), be, for example, its part not shielded.Block 260 may include in various manners any one To execute this etching, its nonrestrictive example is that here is presented.
For example, block 260 may include execution one dry etch process (or a wet etch process) to be etched through This base dielectric layer (for example, oxide, nitride, etc.) by the perforation institute exposed portion through this first dielectric layer, This first dielectric layer is to act as a shielding being used for this etching.
Fig. 1 G is the icon of the example of various features (for example, dielectric etch feature) providing block 260.For example, This base dielectric layer 111 be demonstrated in figure 1f be part under this first conducting wire 112 be to be removed from Fig. 1 G. This is, for example, a metal in this first conducting wire 112 and between the RDL circuit that block 265 is formed for the enable to gold The contact belonging to.
In general, block 260 for example can include etching this base dielectric layer.Then, the category of this content of the invention is not Should be limited to execute any specific mode of this kind of etching.
The method 200 of this example can include forming the first redistribution layer (RDL) circuit in block 265.Block 265 can To form a RDL circuit including in various manners any one, its nonrestrictive example is that here is presented.
As discussed herein, a RDL dielectric layer (for example, being formed in block 255) can be used in etching (for example, in block 260) and then retain the formation for those RDL circuits.Or, a RDL dielectric Layer can be formed after this etch process and be patterned.In another alternative embodiment discussed herein, this is used for The etch process of base dielectric layer can be skipped, e.g. in wherein this base dielectric layer (for example, a thin oxide or nitrogen Compound layer) be sufficiently conductive, using fully as one in the embodiment of the conductive path between metallic circuit.
Block 265 may include formation the first RDL circuit to be attached to the RDL through this patterning of this RD structure The first conducting wire that dielectric layer is exposed.First RDL circuit also can be formed on a RDL dielectric layer.Block 265 May include any one (e.g. by plating) in various manners to form a RDL circuit, but this content of the invention Category is not limited to form the feature of any ad hoc fashion of this kind of circuit.
Those RDL circuits may include various materials (for example, copper, gold, nickel, etc.) any one.First RDL line Road for example can include any one of the feature of various sizes.For example, one be used for a RDL circuit typical spacing for example It can be 5 microns.In the embodiment of an example, those RDL circuits in a center to center spacing can be for example About or at least one order of magnitude is more than the various circuits of RD structure of this RD wafer and is formed a spacing at place (for example, one The spacing of individual micron, about 0.5 micron of spacing, etc.) to be formed.
Fig. 1 G and 1H is the icon of the example of various features (for example, RDL circuit forms feature) providing block 265. For example, a Part I 181 of a RDL circuit can be formed in the perforation 172 of a RDL dielectric layer 171 and connect Touch first conducting wire 112 exposed by this kind of perforation 172 of this RD structure 110.Equally for example, a RDL line One Part II 182 on road can be formed on a RDL dielectric layer 171.
In general, block 265 may include formation the first redistribution layer (RDL) circuit.Then, the model of this content of the invention Farmland should not necessarily be limited to the feature of any specific RDL circuit or is limited to form any ad hoc fashion of this kind of RDL circuit Feature.
The method 200 of this example can include in those RDL circuits (for example, in 265 shapes of block in block 270 Become) and a RDL dielectric layer (for example, being formed in block 255) on formed and patterning one the 2nd RDL dielectric Layer.Block 270 may include in various manners any one being formed and to pattern this second dielectric layer, its nonrestrictive example Son is that here is presented.
For example, block 270 can share arbitrary or all of feature with block 255.2nd RDL dielectric layer for example may be used To be to be formed using a RDL dielectric layer identical material that is a kind of and being formed in block 255.
2nd RDL dielectric layer for example can include polyimides or a polybenzoxazoles (PBO) material.This second RDL dielectric layer for example can generally comprise a kind of organic material.However, in various one example implementation, a RDL is situated between Electric layer may include a kind of inorganic material.
Fig. 1 H is the icon of the example of various features providing block 270.For example, the 2nd RDL dielectric layer 183 be by It is formed on those RDL circuits 181,182 and on a RDL dielectric layer 171.As, shown in Fig. 1 H, passed through Hole 184 is to be formed in this second RDL layer 183, and can make touching of conduction through perforation 184 and pass through by this kind of The RDL circuit 182 that hole 184 is exposed.
In general, block 270 may include formation and/or patterning one the 2nd RDL dielectric layer.Then, this content of the invention Category any ad hoc fashion of should not necessarily be limited to the feature of any specific dielectric layer or being limited to be formed a dielectric layer Feature.
The method 200 of this example can include forming the second redistribution layer (RDL) circuit in block 275.Block 275 can To form the 2nd RDL circuit including in various manners any one, its nonrestrictive example is that here is presented.Area Block 275 for example can share arbitrary or all of feature with block 265.
Block 275 may include the 2nd RDL line that formation is attached to a RDL circuit (for example, being formed) in block 265 Road, and those RDL circuits are through in the 2nd RDL dielectric layer (for example, being formed in block 270) of this patterning Perforation and be exposed.Those the 2nd RDL circuits also can be formed on the 2nd RDL dielectric layer.Block 275 may include with respectively Any one (e.g. by plating) of kind of mode is forming those the 2nd RDL circuits, but the category of this content of the invention is not It is limited to the feature of any specific mode.
Such as a RDL circuit, those the 2nd RDL circuits may include any one of various materials (for example, copper, etc.). Additionally, the 2nd RDL circuit for example can include any one of the feature of various sizes.
Fig. 1 H and 1I is the icon of the example of various features providing block 275.For example, those the 2nd RDL circuits 191 Can be formed in the perforation 184 in the 2nd RDL dielectric layer 183, to contact the RDL being exposed through this kind of perforation 184 Circuit 181.Additionally, the 2nd RDL circuit 191 can be formed on the 2nd RDL dielectric layer 183.
In general, block 275 may include formation the second redistribution layer (RDL) circuit.Then, the model of this content of the invention Farmland should not necessarily be limited to the feature of any specific RDL circuit or is limited to form any ad hoc fashion of this kind of RDL circuit Feature.
The method 200 of this example can include the 2nd RDL circuit (for example, being formed in block 275) in block 280 And the 2nd form on RDL dielectric layer (for example, being formed in block 270) and patterning one the 3rd RDL dielectric layer.Block 280 may include in various manners any one being formed and to pattern the 3rd dielectric layer, its nonrestrictive example be This is presented.
For example, block 280 can share arbitrary or all of feature with block 270 and 255.3rd RDL dielectric layer Can be for example using one with block 255 (and/or the etching in block 260 and divest an interim screen layer after) institute The RDL dielectric layer identical material and/or identical with the 2nd RDL dielectric layer being formed in block 270 using one being formed Material to be formed.
3rd RDL dielectric layer for example can include polyimides or a polybenzoxazoles (PBO) material.3rd RDL dielectric layer for example can generally comprise a kind of organic material.However, in various one example implementation, the 3rd RDL is situated between Electric layer may include a kind of inorganic material.
Fig. 1 I is the icon of the example of various features providing block 280.For example, the 3rd RDL layer 185 can be formed On those the 2nd RDL circuits 191 and on this second RDL layer 183.As, shown in Fig. 1 I, perforation is to be formed on In 3rd RDL layer 185, and can through those perforations come make conduction touch second being exposed by this kind of perforation RDL circuit 191.
In general, block 280 may include formation and/or patterning one the 3rd RDL dielectric layer.Then, this content of the invention Category any ad hoc fashion of should not necessarily be limited to the feature of any specific dielectric layer or being limited to be formed a dielectric layer Feature.
The method 200 of this example can include on those the 2nd RDL circuits and/or in the 3rd RDL in block 285 Interconnection structure is formed on dielectric layer.Block 285 may include in various manners any one forming those interconnection structures, its non- Restricted example is that here is presented.
Block 285 for example can be included in the 2nd RDL circuit being exposed through the perforation in the 3rd dielectric layer Partly upper formation one projection bottom (underbump) metal.Block 285 then for example can be included conductive projection or ball attachment To this underbump metallization.Other interconnection structures can also be utilized, and its example is that here is assumed (for example, conductive pole Or cylinder, solder ball, solder projection, etc.).
Fig. 1 I is the icon of the example of various features (feature that for example, interconnection structure is formed) providing block 285.Example If interconnection structure 192 is to be attached to those the 2nd RDL lines through the perforation formed in the 3rd RDL dielectric layer 185 Road 191.It is noted that although those interconnection structures 192 are depicted as less than interconnection structure 121, this content of the invention is simultaneously So not limited.For example, those interconnection structures 192 can link with interconnection structure 121 identical size or more than mutual Structure 121.Additionally, those interconnection structures 192 can be interconnection structures with interconnection structure 121 same type or can be one Different types.
Although the redistribution layer (it is also referred to alternatively as front redistribution layer (RDL)) being formed in block 255-285 It is to show greatly a kind of fan-out assembly (for example, extending to outside the area of coverage of crystal grain 125,126) to be described in FIG, but It is that they can also be formed with a kind of fan-in assembly, for example wherein interconnection structure 192 substantially and does not extend into crystal grain 125th, outside 126 area of coverage.The nonrestrictive example of this kind of assembly is that here is presented.
In general, block 285 for example may include on those the 2nd RDL circuits and/or on the 3rd RDL dielectric layer Form interconnection structure.Then, the category of this content of the invention should not necessarily be limited to the feature of any specific interconnection structure or is subject to It is limited to form any specific mode of interconnection structure.
The method 200 of this example block 290 can include de- glutinous (or separation) in block 245 attached by wafer support Part.Block 290 may include in various manners any one is this kind of de- glutinous to execute, its nonrestrictive feature be here in addition Present.
For example, it is that in the example plot being adhesively attached, this adhesive agent can be released (example in wherein this wafer holder As using heat and/or power).Equally for example, chemical releasing agent can be utilized.It is profit in another wherein this wafer holder In example plot with a vacuum power attachment, this vacuum power can be released.It is noted that being related to adhesive agent or other one In the plot to help the installation of this wafer holder for the material, block 285 may include after this takes off and sticks, from this electric devices And/or remove residue from this wafer holder.
Fig. 1 I and 1J is the icon of the example of various features providing block 290.For example, the wafer described in Fig. 1 I Support member 150 is to be removed in Fig. 1 J.
In general, block 290 may include de- this wafer holder glutinous.Then, the category of this content of the invention should not be subject to It is limited to the feature of any certain types of wafer holder or any specific side being limited to a de- glutinous wafer holder Formula.
The method 200 of this example can include cutting this wafer in block 295.Block 295 may include in various manners Cutting this wafer, its nonrestrictive example is that here is presented for any one.
Discussion in this substantially has focussed on the process of the single crystal grain of this RD wafer.This kind of this RD wafer of focusing on Single crystal grain is intended merely to clearly illustrate.It is to be understood that all fabrication steps discussed herein can be It is performed in one whole wafer.For example, each diagram being proposed in Figure 1A -1J and other figure in this can be in list It is replicated tens of or hundreds of times on one wafer.For example, before being cut, in the assembly being illustrated of this wafer Can be indiscrete between the assembly assembly adjacent with.
Block 295 for example can include cutting out from this wafer that (for example, mechanical stamping cutting, mechanical saw cut, laser are cut Cut, soft beam cutting, plasma-based cutting, etc.) individual other encapsulation.The final result of this kind of cutting can be for example in Fig. 1 J Shown encapsulation.For example, the side surface that this cutting can form this encapsulation is the coplanar side of the multiple components including this encapsulation Surface.For example, this molding material 130, the dielectric layer of RD structure 110, various RDL dielectric layers, primer filling 128, etc. Any one or whole side surfaces can be coplanar.
In general, block 295 may include this wafer of cutting.Then, the category of this content of the invention should not necessarily be limited to cut Cut the feature of any ad hoc fashion of a wafer.
Fig. 1 and 2 is the feature of method and its change proposing various examples.The feature of the method for other examples is present Will be proposed with reference to other figure.
As discussed herein, Fig. 1 and 2 discussion in, block 235 may include this molding material of grinding (or thinning) Material 130, to expose one or more in crystal grain 125,126.One example is to be provided in Fig. 1 D.
Also as discussed, do not need to be executed in the molded abrasive (or thinning) of block 235 or can be in addition Going to a scope is still to allow the top of crystal grain 125,126 be capped molding material 130.One example is to be provided in Fig. 3.As Same shown in figure 3 a, this molding material 130 is the top covering semiconductor grain 125,126.It is noted that those interconnection Structure 121 can be shorter or higher than crystal grain 125,126.Continue this to compare, be not to occur as opened up in Fig. 1 J The produced encapsulation 100J showing, but produced encapsulation 300B can occur such as those shown in figure 3b.
Furthermore, as discussed at this, Fig. 1 and 2 discussion in, formed TMV interconnection structure block 215 and The block 240 that TMV molding is degraded can be skipped.One example is to be provided in Fig. 4.As shown in Figure 4 A, with respect to area Block 215 and Figure 1B, it does not form TMV interconnection structure 121.As shown in figure 4b, with respect to block 230 and Fig. 1 C, This molding material 130 does not cover interconnection structure.
Continue this to compare, as explained at this, may be performed one in the molded abrasive (or thinning) of block 235 Scope is one or more exposing the top of crystal grain 125,126 from this molding material 130.Fig. 4 C is provide this kind of process one The icon of example.In general, the assembly 400C of Fig. 4 C is analogous to the assembly 100J of Fig. 1 J, then deduct interconnection structure 121 with And pass through molding material 130 to expose the perforation degrading of those interconnection structures.
Equally for example, as explained at this, can be skipped in the molded abrasive (or thinning) of block 235 or Be be performed to a scope be allow crystal grain 125,126 top be capped molding material 130.Fig. 4 D is provide this kind of process one The icon of example.In general, the assembly 400D of Fig. 4 D is analogous to the assembly 100J of Fig. 1 J, then deduct interconnection structure 121 with And pass through molding material 130 to expose the perforation degrading of those interconnection structures, and wherein molding material 130 is to cover crystal grain 125、126.
In another example, as explained at this, in the discussion of block 215, those TMV interconnection may include various Any one of structure, such as one conductive pole (for example, the post of plating or cylinder, vertical wire, etc.).Fig. 5 A is to provide attachment Icon to an example of the conductive pole 521 of this RD structure 110.Those conductive poles 521 can be for example plating in this RD structure On 110.Those conductive poles 521 for example can also include attachment (for example, the attachment of wire bonding, welding, etc.) to this RD tie Structure 110 and the line (for example, the line of wire bonding) vertically extending.Those conductive poles 521 for example can be from this RD structure 110 Extend to a height be greater than crystal grain 125,126 one height, be equal to crystal grain 125,126 in one or more of height, be less than One height of crystal grain 125,126, etc..In the embodiment of an example, it is micro- more than or equal to 200 that those posts can have one The height of rice, and under the spacing of the center to center of a 100-150 micron.It is noted that any number of row Post 521 can be formed.In general, the assembly 500A of Fig. 5 A is analogous to the assembly 100B of Figure 1B, wherein conductive pole 521 is to make For interconnection structure, rather than conducting sphere 121.
Continue this example, Fig. 5 B is to describe the capped RD structure 110 moulding material 130, conductive pole 521, semiconductor die Grain 125,126 and primer filling 128.This molding for example can be held according to the block 230 of the method 200 of this example OK.In general, the assembly 500B of Fig. 5 B is analogous to the assembly 100C of Fig. 1 C, wherein conductive pole 521 is as interconnection structure, Rather than conducting sphere 121.
Continue to this example, Fig. 5 C be describe this molding material 130 be thinned (for example, being ground) wanted to one Thickness.This thinning for example can be executed according to the block 235 of the method 200 of this example.For example it is to be noted that to, Those conductive poles 521 and/or semiconductor grain 125,126 also can be thinned.In general, the assembly 500D of Fig. 5 D is analogous to The assembly 100D of Fig. 1 D, wherein conductive pole 521 are as interconnection structure, rather than conducting sphere 121, and also do not have Fig. 1 D's The perforation 140 degrading.For example, the thinning of this molding material 130 can expose the top of conductive pole 521.If however, this molding material The top of conductive pole 521 is not exposed in the thinning of material 130, then a molding is degraded operation (for example, according to block 240) and can be held OK.Although it is noted that this assembly is the top being shown as semiconductor grain 125,126 being exposed, those tops Not necessarily it is exposed.For example, those posts 521 can be above semiconductor grain 125,126.The configuration of this kind of example for example may be used With allow those posts 521 can from this molding material 130 expose and/or from this molding material 130 project, this molding material simultaneously 130 is the back surface persistently covering semiconductor grain 125,126, and it for example can provide protection to semiconductor grain 125,126, Avoid or reduce warpage, etc..
It is the embodiment being formed having the example that a height is less than crystal grain 125,126 in wherein those posts 521 In, this thinning may include grinds this molding material 130 first, is followed by grinding this molding material 130 and crystal grain 125,126 The back side (or non-active) side, till those posts 521 are exposed.In this time point, this thinning can be stopped or can continue Continuous, e.g. grind this molding material 130, crystal grain 125,126 and post 521.
Continue this example, assembly 500C shown in figure 5 c can be further by this molding material 130 and crystalline substance Form redistribution layer (RDL) 532 on grain 125,126 to be acted upon.Fig. 5 D is an example showing this kind of process. This redistribution layer 532 here is also referred to alternatively as back side redistribution (RDL) layer 532.Although the formation of this kind of back side RDL is not Clearly it is illustrated in the either block of method 200 of this example, but this kind of operation can be in any one of those blocks It is performed, (example e.g. after the molded abrasive operation of block 235 and before the wafer holder attachment of block 245 As in block 235, in block 240, between any one of block 245 or a little block of here).
As shown in figure 5d, one first backside dielectric layer 533 can this molding material 130 and crystal grain 125, Formed on 126 and patterned.This first backside dielectric layer 533 for example can be formed with a kind of with block 260 The same or similar mode of first RDL dielectric layer 171 and be formed and pattern, although a RDL dielectric layer 171 is one not On same surface.For example, this first backside dielectric layer 533 can be formed on this molding material 130 and in this semiconductor die Grain 125,126 on (for example, the surface of the back surface exposing of crystal grain 125,126, cover crystal grain 125,126 back of the body table On the molding material 130 in face, etc.), and perforation 534 can be formed in this first backside dielectric layer 533 and (e.g. borrow By etching, degrade, etc.), at least to expose the top of those conductive poles 521.It is noted that in wherein this molding material In the configuration of the example of back surface of 130 covering semiconductor grains 125,126, this first backside dielectric layer 533 still can be by shape Become, but it is not necessarily that so (for example, the back side circuit 535 in discussion below can directly be formed on this molding On material 130, rather than in this first backside dielectric layer 533).
Back side circuit 535 can be formed in this first backside dielectric layer 533 and in this first backside dielectric layer 533 Perforation 534 in.Those back side circuits 535 therefore can be electrically connected to conductive pole 521.Those back side circuits 535 are for example permissible It is to be formed with the same or similar mode of a RDL circuit that is a kind of and being formed in block 265.Those back side circuits 535 at least some of (if if not all) for example can from conductive pole 521 extend horizontally to semiconductor grain 125, At the position of 126 surface.At least some of of those back side circuits 535 for example can also extend to simultaneously from conductive pole 521 At the position of the non-surface in semiconductor grain 125,126.
One second backside dielectric layer 536 can be formed in this first backside dielectric layer 533 and back side circuit 535 And patterning.This second backside dielectric layer 536 can be for example with the 2nd RDL dielectric layer that is a kind of and being formed in block 270 183 same or similar modes and be formed and pattern, although the 2nd RDL dielectric layer 183 is on a different surface. For example, this second backside dielectric layer 536 can be formed on this first backside dielectric layer 533 and in those back side circuits On 535, and perforation 537 can be formed in this second backside dielectric layer 536 (for example, by etching, degrade, etc. Deng), to expose the contact area of those back side circuits 535.
Back side interconnection pad 538 (for example, spheroid engagement pad) can be formed in this second backside dielectric layer 536 and/or In the perforation 537 of this second backside dielectric layer 536.Those back side interconnection pads 538 therefore can be electrically connected to back side circuit 535. Those back side interconnection pads 538 can be for example with the same or similar side of the 2nd RDL circuit that is a kind of and being formed in block 275 Formula and be formed.Those back side interconnection pads 538 can be for example by formation metal contact pad and/or to form underbump metallization Change to be formed (for example, being attached to back side circuit 535 in order to strengthening subsequent by interconnection structure).
Although this back side RDL layer 532 is the back side line being shown as having 533,536 and one layer of two backside dielectric layer Road 535, it should be appreciated that any number of dielectric layer and/or line layer all can be formed.
As for example shown in Fig. 5 E, after this back side RDL layer 532 is formed, a wafer support structure 150 Can be attached to this back side RDL layer 532 (for example, directly, using an adhesion layer between, using vacuum power, etc.).Should Wafer holder 150 can be for example with a kind of and in block 245 attached by the same or similar mode of wafer holder 150 To be attached.For example, Fig. 5 E is a kind of the attached in the way of attachment similar to Fig. 1 E of this wafer holder 150 of displaying Connecing, although being wherein attached to this RDL layer 532, rather than being attached to this moulding layer 130 and semiconductor grain 125,126.
As for example described in Fig. 5 F, this supporting layer 105 (shown in Fig. 5 E) can be moved from this RD wafer Remove, a front redistribute layer can be formed on the one of this RD structure 110 with the relative side of crystal grain 125,126, mutually link Structure 192 can be formed, and this wafer holder 150 can be removed.
For example, this supporting layer 105 can with a kind of with discussed in this Correlation block 250 and Fig. 1 E-1F identical or Similar mode to be removed.Equally for example, a front redistribution layer can be with one kind with this Correlation block The same or similar mode that 255-280 and Fig. 1 G-1H is discussed to be formed.In addition for example, interconnection structure 192 Can be to be formed with same or similar mode that is a kind of and being discussed in this Correlation block 285 and Fig. 1 I.And for example It is that this wafer holder 150 can be with same or similar mode that is a kind of and being discussed in this Correlation block 290 and Fig. 1 J And be removed.
In the embodiment of another example, a substrate (for example, a laminated substrate, base plate for packaging, etc.) can be attached On semiconductor grain 125,126, it is, for example, the replacement of back side RDL or extra that here correlation Fig. 5 is discussed.Example As painted in fig. 6, it is the height that will extend to crystal grain 125,126 that interconnection structure 621 can be formed on a height. It is noted that this highly might not exist, for example one wherein this back substrate be have itself interconnection structure or The interconnection structure being wherein extra is to be used in the plot between those interconnection structure 621 and back substrates.Those interconnection Structure 621 can be added with same or similar mode that is a kind of and being discussed in this Correlation block 215 and Figure 1B To be attached.
Continue this example, as painted in fig. 6b, this assembly 600B can be moulded, and if necessary, this mould Thing processed can be thinned.This kind of molding and/or thinning can be for example with one kind with this Correlation block 230 and 235 and Fig. 1 C And the same or similar mode that 1D is discussed to be executed.
As shown in figure 6 c, a wafer holder 150 can be attached, and supporting layer 105 can be removed, and one just Surface side RDL can be formed.For example, a wafer holder 150 can be discussed with a kind of with this Correlation block 245 and Fig. 1 E Same or similar mode to be attached.Equally for example, supporting layer 105 can be with one kind with this Correlation block The same or similar mode that 250 and Fig. 1 F are discussed to be removed.Equally for example, a front RDL can be with one The same or similar mode planted and discussed in this Correlation block 255-280 and Fig. 1 G-1H to be formed.
As painted in figure 6d, interconnection structure 192 can be attached, and this wafer holder 150 can be removed, and carries on the back Face substrate 632 can be attached.For example, this interconnection structure 192 can be discussed with a kind of with this Correlation block 285 and Fig. 1 I The same or similar mode stated to be attached.Equally for example, this wafer holder 150 can be with a kind of and here phase Close the same or similar mode that block 290 and Fig. 1 J discussed to be removed.Again for example, this back substrate 632 Molding material 130 and/or crystal grain 125,126 can be attached to conductive attachment to interconnection structure 621 and/or mechanical type.This back side Substrate 632 can be attached with wafer (or panel) form and/or single packing forms, and for example can be It is attached before cutting (for example, as discussed in block 295) or afterwards.
Shown in figures 1-7 and the method for example discussed herein and assembly are nonrestrictive example, its It is to be presented with the various features describing this content of the invention.This kind of method and assembly can also be with the U.S.s in following co-applications In state's patent application case, arbitrary or all of feature shared by the method shown and discuss and assembly：On January 29th, 2013 Shen Please and entitled " semiconductor device and manufacture semiconductor device method " U.S. patent application case sequence number 13/753,120； On April 16th, 2013 application and the U.S. patent application case sequence number 13/ of entitled " semiconductor device and the method manufacturing it " 863,457；On November 19th, 2013 application and U.S. of entitled " there is the semiconductor device of the well of straight-through silicon perforation-less deep " State's patent application serial no 14/083,779；On March 18th, 2014 application and entitled " semiconductor device and the side manufacturing it The U.S. patent application case sequence number 14/218,265 of method "；On June 24th, 2014 application and entitled " semiconductor device and system The U.S. patent application case sequence number 14/313,724 of the method for making it "；On July 28th, 2014 application and entitled " have thin Redistribution layer semiconductor device " U.S. patent application case sequence number 14/444,450；On October 27th, 2014 application and name It is referred to as the U.S. patent application case sequence number 14/524,443 of " there is the semiconductor device of the thickness of reduction "；On November 4th, 2014 Application and entitled " mediator, its manufacture method, utilize its semiconductor packages and be used for manufacturing this semiconductor packages Method " U.S. patent application case sequence number 14/532,532；On November 18th, 2014 application and entitled " there is sticking up of reduction The U.S. patent application case sequence number 14/546,484 of bent semiconductor device "；And on March 27th, 2015 application and entitled " The U.S. patent application case sequence number 14/671,095 of semiconductor device and the method manufacturing it "；Those U.S. patent application case The content of each hereby here is integrally incorporated by reference with it.
It is noted that semiconductor packages discussed herein any one or all can (but not necessarily) It is attached to a base plate for packaging.This kind of semiconductor device packages and the various nonrestrictive example general now manufacturing its method Can be discussed.
Fig. 7 A-7L is the semiconductor packages and showing a kind of example describing the various features according to present invention Plant the cross-sectional view of the method for example manufacturing semiconductor encapsulation.The structure shown in Fig. 7 A-7L for example can with Similar shown in Figure 1A -1J, 3A-3B, 4A-4D, 5A-5F, 6A-6D, 9,10A-10B, 11A-11D, 12A-12B, 13 and 14 Structure share arbitrary or all of feature.Fig. 8 is that a kind of of the various features according to present invention manufactures semiconductor The flow chart of the method 800 of example of encapsulation.The method 800 of this example for example can with fig. 2 description and here opinion The method 200 of the example stated and and any method discussed herein share arbitrary or all of feature.Fig. 7 A-7L for example may be used To be depicted in the semiconductor packages of the example of the various steps (or block) of the manufacture method 800 of Fig. 8.Fig. 7 A-7L and Fig. 8 is existing Will discussed together.
The method 800 of this example can include preparing a logic crystalline substance being used for processing (for example, for encapsulating) in block 805 Circle.Block 805 may include in various manners any one come to prepare one for process logic wafer, its nonrestrictive example Son is that here is presented.Block 805 for example can be with the area of the method 200 of shown in fig. 2 and example discussed herein Block 205 shares arbitrary or all of feature.
The method 800 of this example can include preparing a redistribution structure wafer (RD wafer) in block 810.Block 810 may include in various manners any one come to prepare one for process RD wafer, its nonrestrictive example is here There is provided.Block 810 for example can be shared with the block 210 of the method 200 of shown in fig. 2 and example discussed herein Arbitrary or all of feature.
Fig. 7 A is the icon of the example of various features providing block 810.Reference picture 7A, this RD wafer 700A for example may be used To include a supporting layer 705 (for example a, silicon layer).One redistribution (RD) structure 710 can be formed on this supporting layer 705. This RD structure 710 for example can include a base dielectric layer 711, one first dielectric layer 713, the first conducting wire 712, one second Dielectric layer 716, the second conducting wire 715 and interconnection structure 717.
This base dielectric layer 711 can be for example on this supporting layer 705.This base dielectric layer 711 for example can include Monoxide layer, mononitride layer, etc..This base dielectric layer 711 for example can be formed according to specification, and/or can To be natural.
This RD wafer 700A for example can also include the first conducting wire 712 and one first dielectric layer 713.Those first Conducting wire 712 for example can include the conducting metal (for example, copper, etc.) depositing.This first dielectric layer 713 for example can wrap Include a kind of Inorganic Dielectric Material (for example, Si oxide, silicon nitride, etc.).In the assembly of a replacement, this first dielectric layer 713 may include a kind of organic dielectric materials.
This RD wafer 700A for example can also include the second conducting wire 715 and one second dielectric layer 716.This second is led Electric line 715 for example can include the conducting metal (for example, copper, etc.) depositing.This second conducting wire 715 for example can be saturating Cross individual other conductive through hole 714 (for example, in this first dielectric layer 713) to connect to individual other first conducting wire 712.Should Second dielectric layer 716 for example can include a kind of Inorganic Dielectric Material (for example, Si oxide, silicon nitride, etc.).Replace one In the assembly in generation, this second dielectric layer 716 may include a kind of organic dielectric materials.
Although two groups of dielectric layer and conducting wire are to be depicted in fig. 7, it should be appreciated that this RD wafer 700A RD structure 710 may include any number of this kind of layer and circuit.For example, this RD structure 710 can only include a dielectric layer and/ Or one group conducting wire, three groups of dielectric layer and/or conducting wire, etc..
Such as the logic wafer preparation in block 805, block 810 may include and formed on a surface of this RD structure 710 Interconnection structure (for example, conductive projection, conducting sphere, conductive pole, conductive plane or pad, etc.).The example of this kind of interconnection structure 717 Son is to be demonstrated in fig. 7, and wherein this RD structure 710 is including interconnection structure 717, and it is to be shown as being formed on this RD On front (or top) side of structure 710, and it is to electrically couple to individually through the conductive through hole in this second dielectric layer 716 The second conducting wire 715.This kind of interconnection structure 717 for example can be utilized to couple this RD structure 710 to various electronics structures Part (for example, the semiconductor component of active or crystal grain, passive component, etc.).
Those interconnection structures 717 for example can include various conductive materials any one (for example, copper, nickel, gold, etc. Any one or one combination).Those interconnection structures 717 for example can also include solder.
In general, block 810 may include preparation one redistribution structure wafer (RD wafer).Then, this content of the invention Category should not necessarily be limited to execute the feature of any ad hoc fashion of this kind of preparation.
The method 800 of this example can include being attached one or more semiconductor grains to this RD structure (example in block 820 As the RD structure of this RD wafer).Block 820 may include in various manners any one being attached this crystal grain to this RD structure, its Nonrestrictive example be that here is provided.Block 820 for example can be with shown in fig. 2 and example discussed herein The block 220 of method 200 share arbitrary or all of feature.
Fig. 7 B is the icon of the example of various features (for example, this die attachment) providing block 820.For example, first Crystal grain 725 (for example, its can be from one in block 805 prepared by logic wafer be cut to) be electrical and mechanical type Be attached to this redistribution structure 710.Similarly, (for example, it can be in block 805 from one to this second crystal grain 726 Prepared logic wafer is cut to) it is electrical and be mechanically attached to this redistribution structure 710.
This first crystal grain 725 and the second crystal grain 726 may include any one of various grain properties.In an example plot In, this first crystal grain 725 may include a processor crystal grain, and this second crystal grain 726 may include an internal memory crystal grain.In another model In example plot, this first crystal grain 725 may include a processor crystal grain, and this second crystal grain 726 may include a coprocessor Crystal grain.In another example plot, this first crystal grain 725 may include a sensor crystal grain, and this second crystal grain 726 may include One sensor processes crystal grain.Although being to be shown as thering is two crystal grain 725,726 in the assembly 700B of Fig. 7 B, it is permissible There is any number of crystal grain.For example, it can only have a crystal grain, three crystal grain, four crystal grain or more than four crystal grain.
Although additionally, this first crystal grain 725 and the second crystal grain 726 are to be shown as being attached to laterally relative to each other This redistribution structure 710, but they can also be configured in a vertical assembly.This kind of structure various non-limiting The assembly of example be that here is demonstrated and discusses that (for example, storehouse on crystal grain for the crystal grain, die attachment are to relative substrate Side, etc.).Furthermore, although this first crystal grain 725 and the second crystal grain 726 are to be shown as thering is substantially similar size, Be this kind of crystal grain 725,726 may include different individual another characteristic (for example, crystal grain height, the area of coverage, connect spacing, etc.).
This first crystal grain 725 and the second crystal grain 726 are to be depicted as thering is substantially uniform spacing, but this is not necessarily If so.For example, this first crystal grain 725 is big in a region of this second crystal grain 726 of next-door neighbour of the first crystal grain area of coverage One region of all or part of contact and/or this second crystal grain 126 this first crystal grain 725 of next-door neighbour in the second crystal grain area of coverage In most contact can have the spacing thinner than other most or all of contacts essence.For example, this first crystalline substance Grain 725 5,10 or n row near before the second crystal grain 726 (and/or this second crystal grain 726 is near first crystal grain 725) Contact can have one 30 microns of spacing, and other contact substantially can have between one 80 microns and/or 200 microns Away from.This RD structure 710 therefore can have corresponding contact structures and/or circuit under this corresponding spacing.
In general, block 820 is to be attached to this redistribution structure (for example, including by one or more semiconductor grains The redistribution structure of one redistribution wafer).Then, the category of this content of the invention should not necessarily be limited to any specific crystal grain Feature or any spy being limited to the feature of layout of any specific multiple grain or being limited to be attached this kind of crystal grain Determine mode feature, etc..
The method 800 of this example can include primer and be filled in being connected to the half of this RD structure appended by block 820 in block 825 Semiconductor die and/or other component.Block 825 may include in various manners any one executing the filling of this kind of primer, its Nonrestrictive example is that here is presented.Block 825 for example can with shown in fig. 2 and example discussed herein The block 225 of method 200 shares arbitrary or all of feature.
Fig. 7 B is the icon of the example of various features (for example, this primer filling) providing block 825.This primer is filled 728 is to be arranged between this first semiconductor grain 725 and redistribution structure 710 and in this second semiconductor grain Between 726 and redistribution structure 710.
Although this primer filling 728 be substantially be depicted as flat, this primer filling can rise and at this Form fillet on the side of semiconductor grain and/or other component.In an example plot, at least the four of those crystal grain side surfaces / mono- or at least half can be capped this primer packing material.In another example plot, those whole side surfaces One or more or all can be capped this primer packing material.Equally for example, directly those semiconductor grains it Between, the essence in space between this semiconductor grain and other component and/or between other components partly can be by Insert this primer packing material.For example, between laterally adjacent semiconductor grain, this semiconductor grain and other components it Between and/or at least half of space between other components or whole spaces can be received in this primer packing material. In the embodiment of an example, this primer filling 728 can cover the whole redistribution structure 710 of this RD wafer.Here Plant in one example implementation, when cut after this RD wafer, this kind of cutting also can cut through this primer filling 728.
In general, block 825 may include primer be filled in block 820 be attached to this RD structure semiconductor grain and/ Or other component.Then, the category of this content of the invention should not necessarily be limited to any certain types of primer filling or executes this Plant the feature of any ad hoc fashion of primer filling.
The method 800 of this example can include moulding this RD wafer (or RD structure) in block 830.Block 830 can wrap Include in various manners any one moulding this RD wafer, its nonrestrictive example is that here is presented.Block 830 As arbitrary or all of spy can be shared with the block 230 of the method 200 of shown in fig. 2 and example discussed herein Levy.
Fig. 7 C is the icon of the example of various features (for example, molded features) providing block 830.For example, this molding Assembly 700C be shown as wherein this molding material 730 cover this first semiconductor grain 725, the second semiconductor grain 726, Primer filling 728 and the top surface of this redistribution structure 710.Although (its here is also referred to alternatively as this molding material 730 Encapsulation materials) it is side and the top being shown as being completely covered this first semiconductor grain 725 and the second semiconductor grain 726 End, but this is not necessarily such.For example, block 830 may include using a film auxiliary or the molding technique of die seal, Material is not moulded with the top keeping crystal grain.
In general, this molding material 730 for example can with directly contact and cover crystal grain 725,726 not by this primer The part of filling 728 covering.For example, at least one Part I in a wherein side for those crystal grain 725,726 is by primer In the plots of filling 728 covering, this molding material 730 can with directly contact and cover crystal grain 725,726 side one the Two parts.The space that this molding material 730 for example can also be filled between crystal grain 725,726 (for example, is not yet received in primer At least a portion in the space of filling 728).
In general, block 830 may include this RD wafer of molding.Then, the category of this content of the invention should not necessarily be limited to The feature of any specific molding material, structure and/or technology.
The method 800 of this example can include grinding the molding that (or thinning) is applied in block 830 in block 835 Material.Block 835 may include in various manners any one grinding (or thinning) this molding material, its nonrestrictive example Son is that here is presented.Block 835 for example can be with the area of the method 200 of shown in fig. 2 and example discussed herein Block 235 shares arbitrary or all of feature.
Fig. 7 D is the icon of the example of various features (for example, this molded abrasive feature) providing block 835.This assembly 700D is to be depicted as this molding material 730 (for example, with respect to the molding material 730 described in Fig. 7 C) to be thinned, to expose The top surface of crystal grain 725,726.In this kind of example, this crystal grain 725,726 can also be ground (or thin Change).
As explained at this, this molding material 730 can be retained to cover crystal grain in an Overmolded assembly 725、726.For example, this molding material 730 can be not ground or this molding material 730 can be ground, but simultaneously Not to a height exposing crystal grain 725,726.
In general, block 835 may include the molding material that grinding (or thinning) is applied in block 830.Then, The category of this content of the invention should not necessarily be limited to grind any specific amount of (or thinning) or the feature of type.
The method 800 of this example can include RD wafer (for example, its top or the molding moulding this in block 845 Side) it is attached to a wafer support structure.Block 845 may include in various manners any one RD wafer attachment of moulding this To this wafer support structure, its nonrestrictive example is that here is provided.Block 845 for example can be with institute in fig. 2 Show and the block 245 of method 200 of example discussed herein shares arbitrary or all of feature.
Fig. 7 E is the icon of the example of various features (for example, the feature of wafer holder attachment) providing block 845. This wafer support structure 750 is the tip side being attached to this molding material 730 and crystal grain 725,726.This wafer support is tied Structure 750 can be attached using an adhesive agent.It is noted that the top in wherein those crystal grain 725,726 End is capped in the assembly of this molding material 730, and this wafer support structure 750 can only be coupled directly to this molding material 730 top.
In general, block 845 may include, and this RD wafer (for example, its top or molding side) moulding is attached to one Wafer support structure.Then, the category of this content of the invention should not necessarily be limited to the spy of any certain types of wafer support structure Levy or be limited to be attached the feature of any ad hoc fashion of a wafer support structure.
The method 200 of this example can include removing a supporting layer from this RD wafer in block 850.Block 850 may include Removing this supporting layer, its nonrestrictive example is that here is presented in various manners any one.Block 850 is for example Arbitrary or all of feature can be shared with the block 250 of the method 200 of shown in fig. 2 and example discussed herein.
As discussed herein, this RD wafer may include a RD structure and is formed and/or carries a supporting layer thereon. This supporting layer for example can include a kind of semi-conducting material (for example, silicon).Include a silicon wafer layer in wherein this supporting layer In example plot, block 850 may include remove this silicon (for example, from this RD wafer remove this silicon whole, remove from this RD wafer The almost all (e.g. at least 90% or 95%) of this silicon, etc.).For example, block 850 may include this silicon of mechanical polishing Almost all, is followed by a dry type or wet chemical etch to remove remainder (or almost all of this remainder). It is block in the example plot being loosely attached to and being formed (or carrying) RD structure thereon in wherein this supporting layer 850 may include and pull open or peel off with separately this supporting layer and this RD structure.
Fig. 7 F is the icon of the example of various features (for example, supporting layer removes feature) providing block 850.For example, This supporting layer 705 (shown in figure 7e) is to be removed from this RD structure 710.In this example illustrated, this RD structure 710 still can include one as base dielectric layer discussed herein 711 (for example, monoxide, nitride, etc.).
In general, block 850 may include removes a supporting layer from this RD wafer.Then, the category of this content of the invention is not The feature of any certain types of wafer material should be limited to or be limited to any ad hoc fashion that wafer material removes Feature.
The method 800 of this example can include forming and pattern redistribution layer (RDL) dielectric layer in block 855, For etching the monoxide layer of this RD structure.Block 855 may include in various manners any one being formed and to pattern This RDL dielectric layer, its nonrestrictive example is that here is presented.Block 855 for example can with shown in fig. 2 and The block 255 of the method 200 of example discussed herein shares arbitrary or all of feature.
Fig. 7 G is the icon of the example of various features providing block 855.For example, this RDL dielectric layer 771 is in this base It is formed on bottom dielectric layer 711 and pattern.The RDL dielectric layer 771 of this patterning for example can be included through RDL dielectric layer 771 perforation 772, such as this base dielectric layer 711 can be etched (for example, in block 860) through perforation 772, and Conducting wire (or its part) can be formed (for example, in block 865) in perforation 772.
In general, block 855 may include being formed e.g. in this base dielectric layer and patterning one dielectric layer (example As a RDL dielectric layer).Then, the category of this content of the invention should not necessarily be limited to the feature of a specific dielectric layer or is subject to It is limited to form the feature of an ad hoc fashion of a dielectric layer.
The method 800 of this example can include etching (for example, the oxidation of this base dielectric layer from this RD structure in block 860 Nitride layer, nitride layer, etc.), be, for example, its part not shielded.Block 860 may include in various manners any one To execute this etching, its nonrestrictive example is that here is presented.Block 860 for example can with fig. 2 shown with And the block 260 of the method 200 of example discussed herein shares arbitrary or all of feature.
Fig. 7 G is the icon of the example of various features providing block 860.For example, being opened up of this base dielectric layer 711 Show that the part under the first conducting wire 712 in figure 7f is to be removed from Fig. 7 G.For example, this to be enable first lead at those Electric line 712 contact with the metal between the RDL circuit that block 865 is formed to metal.
In general, block 860 for example can include etching this base dielectric layer.Then, the category of this content of the invention is not Should be limited to execute any specific mode of this kind of etching.
The method 800 of this example can include forming redistribution layer (RDL) circuit in block 865.Block 865 may include Forming this RDL circuit, its nonrestrictive example is that here is presented in various manners any one.Block 865 As arbitrary or all of spy can be shared with the block 265 of the method 200 of shown in fig. 2 and example discussed herein Levy.
Fig. 7 G and 7H is the figure of the example of various features (feature that for example, RDL circuit is formed) providing block 865 Mark.For example, a Part I 781 of those RDL circuits can be formed in the perforation 772 of this RDL dielectric layer 771, and connects Touch first conducting wire 712 exposed by this kind of perforation 772 of this RD structure 710.Equally for example, a RDL One Part II 782 of circuit can be formed on a RDL dielectric layer 77l.
In general, block 865 may include formation redistribution layer (RDL) circuit.Then, the category of this content of the invention is not The feature of any specific RDL circuit should be limited to or be limited to form the spy of any ad hoc fashion of this kind of RDL circuit Levy.
Although it is noted that the method 800 of this example be block 855 part only have show a RDL dielectric layer and Only have in block 865 part and show a RDL circuit, but such block can be repeated quickly and easily as many times as required according to institute strategic point.
The method 800 of this example can form interconnection structure in block 885 on RDL circuit.Block 885 may include with respectively Forming those interconnection structures, its nonrestrictive example is that here is presented to any one of kind of mode.For example, block 885 can share arbitrary or all of spy with the block 285 of the method 200 of shown in fig. 2 and example discussed herein Levy.
Block 885 for example can be formed on RDL circuit conductive pole (post that for example, metal column, copper post, solder bind, etc. Deng) and/or conductive projection (for example, solder, etc.).For example, block 885 can include plated conductive post, setting or coating lead Electric projection, etc..
Fig. 7 I is the icon of the example of various features (feature that for example, projection is formed) providing block 885.For example, Interconnection structure 792 (for example, it is to be shown as the post that solder binds, e.g. copper post) is to be attached to those RDL circuits 782.
Although the redistribution layer (it is also referred to alternatively as front redistribution layer (RDL)) being formed in block 855-885 It is to show greatly a kind of fan-in assembly (for example, within the substantially interior area of coverage being contained in crystal grain 725,726) to be retouched in the figure 7 Paint, but they can also be formed with a kind of fan-out assembly, at least some of such as wherein interconnection structure 792 is big Cause extends to outside the area of coverage of crystal grain 725,726.The nonrestrictive example of this kind of assembly is that here is presented.
In general, block 885 may include forms interconnection for example on those RDL circuits and/or on this RDL dielectric layer Structure.Then, the category of this content of the invention should not necessarily be limited to the feature of any specific interconnection structure or is limited to be formed Any specific mode of interconnection structure.
The method 800 of this example block 890 can include de- glutinous (or separation) in block 845 attached by wafer support Part.Block 890 may include in various manners any one is this kind of de- glutinous to execute, its nonrestrictive feature be here in addition Present.For example, block 890 can be shared with the block 290 of the method 200 of shown in fig. 2 and example discussed herein and appoint One or all of feature.
Fig. 7 H and 7I is the icon of the example of various features providing block 890.For example, the wafer described in Fig. 7 H Support member 750 is to be removed in Fig. 7 I.
In general, block 890 may include de- this wafer holder glutinous.Then, the category of this content of the invention should not be subject to It is limited to the feature of any certain types of wafer holder or any specific side being limited to a de- glutinous wafer holder Formula.
The method 800 of this example can include cutting this wafer in block 895.Block 895 may include in various manners Cutting this wafer, its nonrestrictive example is that here is presented for any one.Block 895 for example can with Fig. 2 institute Show and the block 295 of method 200 of example discussed herein shares arbitrary or all of feature.
Discussion in this substantially has focussed on the process of the single crystal grain that this RD wafer is discussed.It is this kind of that to focus on this RD brilliant The single crystal grain of circle is intended merely to clearly illustrate.It is to be understood that all fabrication steps discussed herein (or area Block) can be performed in a whole wafer.For example, each figure being proposed in Fig. 7 A-7L and other figure in this Show and can be replicated tens of or hundreds of times on single wafer.For example, before being cut, being illustrated in this wafer Device assembly in the assembly device assembly adjacent between can be indiscrete.
Block 895 for example can include cutting out from this wafer that (for example, mechanical stamping cutting, mechanical saw cut, laser are cut Cut, soft beam cutting, plasma-based cutting, etc.) individual other encapsulation.The final result of this kind of cutting can be for example in Fig. 7 I Shown encapsulation.For example, the side surface that this cutting can form this encapsulation is the coplanar side of the multiple components including this encapsulation Surface.For example, this molding material 730, the dielectric layer of RD structure 710, RDL dielectric layer 771, primer filling 728, etc. arbitrary Individual or whole side surfaces can be coplanar.
In general, block 895 may include this wafer of cutting.Then, the category of this content of the invention should not necessarily be limited to cut Cut the feature of any ad hoc fashion of a wafer.
The method 800 of this example can include preparing a substrate or its wafer or panel in block 896, for This assembly 700I is to its attachment.Block 896 may include in various manners any one preparing a substrate, its non-limiting Example be that here is presented.Block 896 for example can be with shown in fig. 2 and example discussed herein method 200 Block 205 and 210 share any one or all of feature.
This substrate for example can include the feature of any one of various substrates.For example, this substrate may include a base plate for packaging, Motherboard substrate, laminated substrate, mold substrate, semiconductor substrate, glass substrate, etc.).Block 896 for example can include preparing The front surface of this substrate and/or back surface, for electrical and/or mechanical attachment.Block 896 is for example permissible in this stage Allow the substrate of a panel be retained in a panel-form and cut an other encapsulation or can be with the here stage from a panel afterwards Cut an other substrate.
Block 896 also may include from one of manufacturing facility is adjacent or the manufacturing station of upstream, from another geographical position, Etc. receiving this substrate.The preparation process that the substrate that this receives can be for example having prepared or extra can be in addition Execution.
Fig. 7 J is the icon of the example of various features providing block 896.For example, this assembly 700J is to comprise one to be made It is ready for use on the substrate 793 of the example of attachment.
In general, block 896 may include preparation one substrate or its wafer or panel, for this assembly 700I Attachment to it.Then, the category of the various features of this content of the invention should not necessarily be limited to the feature of specific substrate or is subject to It is limited to prepare the feature of any ad hoc fashion of a substrate.
The method 800 of this example can include for an assembly being attached to this substrate in block 897.Block 897 may include use Any one of various modes come to be attached an assembly (for example, one in Fig. 7 I illustrated in assembly 700I or other assembly), its Nonrestrictive example is that here is presented.Block 897 for example can with shown in fig. 2 and example discussed herein The block 220 of method 200 shares arbitrary or all of feature.
This assembly may include the feature of any one of various assemblies, and its nonrestrictive example is that here is presented, E.g. in the related discussion of all of figure and/or here.Block 897 may include in various manners any one being attached this Assembly.For example, block 897 may include using batch reflow, hot press (TCB), conductive epoxy resin, etc. with by this group Part is attached to this substrate.
Fig. 7 J is the icon of the example of various features (for example, assembly is attached feature) providing block 897.For example, exist The assembly 700I that Fig. 7 I is shown is to be attached to this substrate 793.
Although being not shown in Fig. 7 J, in various one example implementation (for example, as shown in Fig. 7 K and 7L), The interconnection structure e.g. wearing mould interconnection structure can be formed on this substrate 793.In this kind of one example implementation, block 897 can share arbitrary or all of spy with the block 215 of the method 200 of shown in fig. 2 and example discussed herein Levy, although relate to that those interconnection structures are formed on this substrate 793.It is noted that this kind of interconnection structure can be at this It is performed before assembly attachment or afterwards or or can also be performed afterwards before the primer filling of block 898.
In general, block 897 is to be attached to this substrate including by an assembly.Then, the category of this content of the invention should not This is limited to the feature of any specific assembly, substrate or the attachment mode to a substrate for one assembly.
The method 800 of this example can include primer filling assembly on the substrate in block 898.Block 898 can wrap Include various modes primer filling any one, its nonrestrictive example is that here is presented.Block 898 is for example permissible With the block 225 of block 825 and/or the method 200 of shown in fig. 2 and example discussed herein share arbitrary or all Feature.
For example, after the assembly of block 897 is attached, block 898 may include and carrys out primer using a capillary tube primer filling Fill this attachment assembly.For example, the filling of this primer may include a kind of polymeric material of strengthening glutinous enough, to make in a capillary tube With middle flowing between this assembly and this substrate.
Equally for example, block 897 may include and is just attached (for example, using a thermo-compression bonding in block 897 in this assembly Close processing procedure) when, using a kind of non-conductive cream (NCP) and/or a kind of non-conductive film (NCF) or band, this semiconductor die is filled with primer Grain.For example, this kind of primer packing material can be attached this assembly before be deposited (for example, printing, spraying, etc.).
Such as all blocks described in the method 800 of this example, block 898 can be in the flow process of the method 800 In any position at be performed, as long as the space between this assembly and this substrate is to access.
The filling of this primer can also occur at the different block of one of method 800 of this example.For example, this primer filling May be performed that substrate moulds the part (for example, using a molding primer filling) of block 899.
Fig. 7 K is the icon of the example of various features (for example, feature filled by this primer) providing block 898.This primer Filling 794 is to be arranged between this assembly 700I and substrate 793.
Although this primer filling 794 be substantially be depicted as flat, this primer filling can rise and at this Form fillet on the side of assembly 700I and/or other component.In an example plot, the side surface of this assembly 700I is at least A quarter or at least half can be capped this primer packing material.In another example plot, this assembly 700I's is whole Individual side surface one or more or all can be capped this primer packing material.Equally for example, directly in this assembly An essence in space between 700I and other component and/or between other components (being shown in various in figures) This primer packing material 794 partly can be received in.For example, between the laterally adjacent component of this assembly 700I and at least The space of half or whole spaces can be received in this primer packing material.
As, shown in Fig. 7 J, this assembly 700J may include one between this crystal grain 725,726 and this RD structure 710 Second primer filling 794 between this RD structure 710 and this substrate 793 for the first primer filling 728 and.This kind of primer Filling 728,794 can be for example different.For example, one wherein between this crystal grain 725,726 and this RD structure 710 away from From less than in this RD structure 710 with the example plot of the distance between this substrate 793, this first primer filling 728 compared to This second primer filling 794 can generally comprise a less packing size (or having higher viscosity).In other words, should Second primer filling 794 can be more cheap than the filling 728 of this first primer.
Furthermore, the individual other primer filling process performed by block 898 and 825 can be different.For example, block 825 may include using a capillary tube primer to-fill procedure, and block 898 may include using non-conductive cream (NCP) primer filling Program.
In another example, block 825 and 898 may include and is performed in an identical primer filling process simultaneously, example In this way after block 897.Additionally, as discussed herein, the primer filling of a molding also can be utilized.In this kind of example In plot, block 899 may include arbitrary or both bottoms executing block 825 and/or 898 during this substrate moulds processing procedure Glue is filled.For example, block 825 may include execution one capillary tube primer filling, and block 898 is to be performed as one in block 899 Molding primer filling process.
In general, block 898 may include primer is filled in assembly and/or the other being connected to this substrate appended by block 897 Component.Then, the category of this content of the invention should not necessarily be limited to any certain types of primer filling or execution primer filling Any specific mode feature.
The method 800 of this example can include moulding this substrate in block 899.Block 899 may include in various manners Executing this kind of molding, its nonrestrictive example is that here is presented for any one.Block 899 for example can and block 830 and/or the block 230 of method 200 of shown in fig. 2 and example discussed herein share arbitrary or all of spy Levy.
For example, block 899 may include be molded on the top surface of this substrate, on the assembly of block 897 attachment, TMV interconnection structure (if it is formed on the substrate, e.g. conducting sphere, ellipsoid, (for example, the plating of post or cylinder Post, line or closing line etc.), etc.) on.
Block 899 for example can include using transfer molding, compression molded, etc..Block 899 for example can include utilizing The processing procedure of one face template die, plurality of substrate is connected in a panel and a molding or block 899 may include together Other ground mold substrate.In the plot of a face template die, after this panel moulds, block 899 may include execution one and cuts system Journey, wherein individual other substrate is with this substrate panel separately.
This molding material for example can include any one of various features.For example, this molding material (for example, epoxy molding Compound (EMC), epoxy resin mould produced compounds, etc.) may include a relatively high modulus, such as with the processing procedure follow-up Middle offer encapsulates support.Equally for example, this molding material may include a relatively low modulus, with the processing procedure follow-up Encapsulation elasticity is provided.
It is different from the molding material being utilized in block 830 that block 899 for example can be included using a kind of molding material. For example, block 899 can be using a kind of molding material with the modulus more relatively low than the molding material being utilized in block 830. In this kind of plot, the middle section of this assembly can be relatively hard compared to the neighboring area of this assembly, this be The absorption of various power is provided in the more strong region of this assembly.
It is different in the molding material 730 of wherein the molding material 735 of this assembly 700K and this assembly 700I, And/or it is formed in the different stages, and/or in the example plot being formed using different types of processing procedure, block 899 (or It is another block) may include and prepare this molding material 730 for being adhered to this molding material 735.For example, this molding material 730 can be etched by physical property or chemical.This molding material 730 for example can be by electric paste etching.Equally for example, ditch Groove, recess, protuberance or other physical characteristics can be formed on this molding material 730.Again for example, an adhesive agent May be disposed on this molding material 730.
Block 899 can be for example different types of molding processing procedure using one and in 830 users of block.In an example In plot, block 830 can utilize a compression molded processing procedure, and block 899 is using a transfer molding processing procedure.In this kind of example In plot, block 830 can using a kind of specific adapt to compression molded molding material, and block 899 can utilize one Plant the specific molding material adapting to transfer molding.This kind of molding material for example can have visibly different material characteristics (example As, flow performance, curing characteristic, stiffness characteristics, particle size feature, chemical compound feature, etc.).
As explained at this, e.g. with regard to block 898, the molding processing procedure of block 899 can be provided in this assembly Primer filling between 700I and this substrate 793, and/or can be provided in primer between this crystal grain 725,726 and this RD structure 710 Filling.In this kind of example, in this molding primer packing material and the molding material being encapsulated substrate 793 and assembly 700I and/or It is encapsulated the uniformity that can have material between RD structure 710 and the molding material of semiconductor grain 725,726.
Fig. 7 K is the icon of the example of various features (for example, those molded features) providing block 899.For example, should Molded assembly 700K is to be shown as wherein this molding material 735 to cover interconnection structure 795 and assembly 700I.Although this molding Material 735 (its here is also referred to alternatively as encapsulation materials) is to be shown as allowing the top of assembly 700I to be exposed, but this is not Necessity is such.For example, block 899 can be completely covered this assembly 700I, and do not need to be followed by a thinning and (or grind Mill) operate and to expose the top of this assembly 700I.
In general, this molding material 735 for example with directly contact and can cover not filled by this primer of assembly 700I The part of 794 coverings.For example, at least one Part I in a wherein side of this assembly 700I is capped primer filling 794 Plot in, this molding material 735 can with directly contact and cover assembly 700I side a Part II.Furthermore, this mould Prepared material 735 can extend transversely to the edge of this substrate 793, and therefore constitutes one and this coplanar side of substrate 793 Surface.This kind of assembly for example can be formed using panel molding, is followed by the simple grain from this panel for an other encapsulation Change.
In general, block 899 may include this substrate of molding.Then, the category of this content of the invention should not necessarily be limited to appoint The feature of what specific molding material, structure and/or technology.
The method 800 of this example can include forming interconnection structure on the substrate in block 886, e.g. in this substrate Relatively this assembly on the side of the side that block 897 is attached to.Those interconnection structures may include various types of interconnection The feature of any one of structure, e.g. can be utilized and be encapsulated to another encapsulation or the knot of a mainboard with connecting semiconductor Structure.For example, those interconnection structures may include conducting sphere (for example, solder ball) or projection, conductive pole, etc..
Fig. 7 K is the icon of the example of various features (for example, the feature of this formation interconnection) providing block 886.Example If those interconnection structures 792 are the planes 791 being depicted as being attached to this substrate 793.
In general, block 886 may include formation interconnection structure on the substrate.Then, the category of this content of the invention is not Any specific mode that the feature of specific interconnection structure should be limited to or be limited to be formed this kind of structure.
As discussed herein, this primer filling 728 can cover at least a portion of the sides of crystal grain 725,726, and/ Or this primer filling 794 can cover at least a portion of the side of assembly 700I.Fig. 7 L is the citing providing this kind of covering Illustrate example.For example, this assembly 700I is to be shown as the side that wherein this primer filling 728 is contact crystal grain 725,726 The part on side.As discussed herein, during one cuts processing procedure, this primer filling 728 also can be cut, and this is generation one Including the assembly 700I of a flat side surface, this side surface is a side surface, this molding material 730 comprising this RD structure 710 A side surface and this primer filling 728 a side surface.
This assembly 700L (it is also referred to alternatively as an encapsulation) is to be shown as wherein primer filling 794 contact this assembly 700I Side a part (for example, the side of this RD structure 710, the side of this primer filling 728 and this molding material 730 Side).It is noted that as discussed herein, in various one example implementation, this primer filling 794 can include The primer filling of molding, it is and this molding material 735 identical material.This molding material 735 is to be shown as being encapsulated substrate 793rd, interconnection structure 795, primer filling 794 and assembly 700I.Although in the icon of this example, assembly 700I and mutually The top linking structure 795 is to be exposed from this molding material 735, but this is not necessarily such.
Fig. 7 and 8 is method characteristic and its change assuming various examples.The method characteristic of other examples now will Can be presented with reference to extra figure.
As discussed herein, Fig. 7 and 8 discussion in, block 835 may include this molding material of grinding (or thinning) Material 730, to expose one or more in crystal grain 725,726.One example is to be provided in Fig. 7 D.
Also as discussed, do not need to be executed in the molded abrasive (or thinning) of block 835 or can be by Going to a scope is still to allow the top of crystal grain 725,726 be capped molding material 730.One example is to be provided in Fig. 9, Wherein this molding material 735 is the top of the crystal grain 725,726 covering this assembly 700I.
Also as discussed herein, e.g. it is relevant to block 897 and Fig. 7 K and 7L, in various one example implementation In, interconnection structure can be formed on the substrate.One example is to be provided in Fig. 9.For example, although those crystal grain interconnection structures 795 top is initially to be capped this molding material 735, and perforation 940 is to be degraded in this molding material 735, to expose mutually Link structure 795.
Furthermore, as Fig. 7 in this and 8 discussion in discussed, in the various one example implementation, TMV interconnects Structure does not need to be formed on the substrate.One example is to be provided in Figure 10 A.As shown in Figure 10 A, with respect to Fig. 7 K, it does not have TMV interconnection structure 795 and is formed.Also as shown in Figure 10 A, with respect to Fig. 1 K, this molding material 735 do not cover interconnection structure.
Equally for example, as explained at this, can be skipped in the molded abrasive (or thinning) of block 899 or Be can be performed to a scope be allow at least one of this assembly 700I and/or crystal grain 725,726 top be capped molding Material 735.Figure 10 A is the icon of the example providing this kind of process.In general, the assembly 1000A of Figure 10 A is analogous to figure The assembly 700K of 7K deducts interconnection structure 795 again, and wherein molding material 735 is to cover this assembly 700I.
Additionally, as explained at this, may be performed a scope in the molded abrasive (or thinning) of block 899 is Expose one or more of this assembly 700I and/or crystal grain 725,726 from this molding material 735 (and/or molding material 730) Top.Figure 10 B is the icon of the example providing this kind of process.In general, the assembly 1000B of Figure 10 B is analogous to Fig. 7 K Assembly 700K, then deduct interconnection structure 795.
In another example, as explained at this, in the discussion of block 897, those TMV interconnection may include various Any one of structure, e.g. one conductive pole (for example, the post of plating or cylinder, vertical wire, etc.).Figure 11 A is to provide It is attached to the icon of an example of the conductive pole 1121 of this substrate 793.Those conductive poles 1121 can be plated at this On substrate 793.Those conductive poles 1121 for example can also include attachment (for example, the attachment of wire bonding, welding, etc.) to this Substrate 793 and the wire (for example, the wire of wire bonding) vertically extending.Those conductive poles 1121 for example can be from this base Plate 793 extend to a height be greater than crystal grain 725,726 one height, be equal to crystal grain 725,726 in one or more of height, Less than crystal grain 725,726 one height, etc..It is noted that the post 1121 of any amount row all can be formed.General and Speech, the assembly 1100A of Figure 11 A is analogous to the assembly 700K of Fig. 7 K (deducting this mold compound 735 again), and it has conductive pole 1121 as interconnection structure, rather than elongated conducting sphere 795.
Continue this example, Figure 11 B is to describe the capped substrate 793 moulding material 735, conductive pole 1121, assembly 700I (for example, semiconductor grain 725,726) and primer filling 794.This molding for example can be according to the method 800 of this example Block 899 to be executed.In general, the assembly 1100B of Figure 11 B is analogous to the assembly 700K of Fig. 7 K, it has conduction Post 1121 is as interconnection structure, rather than elongated conducting sphere 795, and has and be not yet thinned or not yet by enough thin Change to expose the molding material 735 of assembly 700I.
Continue to this example, Figure 11 C is to describe this molding material 735 to be thinned (for example, being ground) to an institute The thickness wanted.This thinning for example can be executed according to the block 899 of the method 800 of this example.For example it is to be noted that arrive It is that those conductive poles 1121 and/or assembly 700I (for example, comprising to mould material 730 and/or semiconductor grain 725,726) are also Can be thinned.For example, the thinning of this molding material 735 can expose the top of conductive pole 1121.If however, this molding material If the top of conductive pole 1121 is not exposed in 735 thinning on the contrary, then a molding is degraded operation and be may be performed.Notice It is, although the top that this assembly 1100C is the semiconductor grain 725,726 being shown as assembly 700I is exposed, those Top is not necessarily exposed.
In general, the assembly 1100C of Figure 11 C is analogous to the assembly 700K of Fig. 7 K, it has conductive pole 1121 conduct Interconnection structure, rather than elongated conducting sphere 795.
Continue this example, the assembly 1100C shown in Figure 11 C can be by this molding material 735 and assembly Form a redistribution layer on 700I (for example, comprising this molding material 730 and/or its semiconductor grain 725,726) (RDL) 1132 and be processed further.Figure 11 D is an example showing this kind of process.This redistribution layer 1132 here is also It is referred to alternatively as back side redistribution (RDL) layer 1132.Although the formation of this kind of back side RDL is not clearly illustrated in this example One of block of method 800, but this kind of operation can be executed in any one of those blocks, e.g. in this area Executed after molded abrasive operation (if if being performed) of block 899.
As, shown in Figure 11 D, one first backside dielectric layer 1133 can be in this molding material 735 and assembly 700I It is formed on (for example, comprising this molding material 730 and/or its semiconductor grain 725,726) and pattern.This first back side Dielectric layer 1133 can be for example with the same or similar mode of RDL dielectric layer 771 that is a kind of and being formed in block 855 and quilt Formed and pattern, despite on the surface different.For example, this first backside dielectric layer 1133 can be formed on this molding On material 735 and/or in this assembly 700I (for example, comprising this molding material 730 and/or its semiconductor grain 725,726) On, e.g. directly it is formed on the back surface exposing of crystal grain 725,726, in the back surface covering crystal grain 725,726 On molding material 730 and/or 735, etc., and perforation 1134 can be formed (example in this first backside dielectric layer 1133 As, by etching, degrade, etc.), at least to expose the top of conductive pole 1121.
Back side circuit 1135 can be formed in this first backside dielectric layer 1133 and in this first backside dielectric layer In 1133 perforation 1134.Those back side circuits 1135 therefore can be electrically connected to conductive pole 1121.Those back side circuits 1135 Can be for example to be formed with the same or similar mode of RDL circuit 782 that is a kind of and being formed in block 865.Those back ofs the body At least some of (if if not all) on upper thread road 1135 for example can extend in this assembly 700I (example from conductive pole 1121 As comprised this molding material 730 and/or its semiconductor grain 725,726) the position of surface at.Those back side circuits 1135 at least some of individual for example can also extending to from this conductive pole 1121 not (for example, comprises this mould in this assembly 700I Prepared material 730 and/or its semiconductor grain 725,726) the position of surface at.
One second backside dielectric layer 1136 can be by shape in this first backside dielectric layer 1133 and back side circuit 1135 Become and pattern.This second backside dielectric layer 1136 for example can be with RDL dielectric layer 771 that is a kind of and being formed in block 855 Same or similar mode and be formed and pattern, despite on the surface different.For example, this second backside dielectric layer 1136 can be formed on this first backside dielectric layer 1133 and on those back side circuits 1135, and perforation 1137 Can be formed in this second backside dielectric layer 1136 (for example, by etching, degrade, etc.), to expose back side circuit 1135 contact area.
Back side interconnection pad 1138 (for example, spheroid engagement pad, plane, terminal, etc.) this second back side can be formed on be situated between In electric layer 1136 and/or in the perforation 1137 of this second backside dielectric layer 1136.Those back side interconnection pads 1138 are therefore permissible It is electrically connected to back side circuit 1135.Those back side interconnection pads 1138 can be for example with RDL that is a kind of and being formed in block 865 The same or similar mode of circuit and be formed.Those back side interconnection pads 1138 can be for example by formation metal contact pad And/or form underbump metallization and be formed and (for example, be attached to the back side in order to strengthening subsequent by other interconnection structures Circuit 1135).
Although this back side RDL layer 1132 is to be shown as thering is 1133,1136 and one layer of back side of two backside dielectric layer Circuit 1135, it should be appreciated that any number of dielectric medium and/or line layer all can be formed.
Although being not shown in Figure 11 D, interconnection structure can be formed on this substrate 793, e.g. in this substrate 793 On the side of one relatively this assembly 700I and molding material 735, as here is for example relevant to block 886 and Fig. 7 K is discussed Person.
In the embodiment of another example, a substrate (for example, a laminated substrate, base plate for packaging, etc.) can be attached It is connected on this assembly 700I (for example, comprising this semiconductor grain 725,726 and molding material 730) and this molding material 735 On, the back side RDL being discussed for example as here correlation Figure 11 A-11D substitutes or extra.
For example, as painted in fig. 12, it is at least to extend that those interconnection structures 795 can be formed on a height Height to this assembly 700I.It is noted that this highly might not exist, e.g. have in wherein this back substrate The interconnection structure of itself or wherein extra interconnection structure is used between those interconnection structure 795 and back substrates Plot in.Those interconnection structures 795 can be for example with a kind of identical with discussed in this Correlation block 897 and Fig. 7 K Or similar mode to be attached.
Continue this example, as painted in fig. 12, this assembly 1200A can be using a molding material 735 come in addition mould System, and if necessary, this molding material 735 can be thinned.This kind of molding and/or thinning can be for example with a kind of and The same or similar mode that this Correlation block 899 and Fig. 7 K are discussed to be executed.
As, shown in Figure 12 B, a back substrate 1232 can be attached.For example, this back substrate 1232 can electricity Connect and be attached to molding material 735 and/or assembly 700I (for example, molding material 730 to interconnection structure 795 and/or mechanical type And/or semiconductor grain 725,726).This back substrate 1232 can be for example with panel-form and/or single packing forms Lai It is attached, and for example can be attached before simple grain or afterwards.
As discussed herein, after this assembly 700I is attached to substrate 793, this substrate 793 and/or assembly 700I A kind of molding material can be capped.Substitute or extra, this substrate 793 and/or assembly 700I can be capped a lid Or strenthening member (stiffener).Figure 13 is to provide an example illustrated.Figure 13 is about showing the assembly of Fig. 7 J 700J, wherein increases by a lid 1310 (or strenthening member).
This lid 1310 for example can include metal, and provides electromagnetic shielding and/or radiating.For example, this lid 1310 A ground path on this substrate 793 can be electrically coupled to, to provide shielding.This lid 1310 for example can utilize solder And/or the epoxy resin of conduction is being coupled to this substrate 793.Although not being demonstrated, thermal interface material can be formed on this In a gap 1315 between assembly 700I and this lid 1310.
Although most of heres are shown and the example of discussion all substantially only shows that this assembly 700I is attached to this substrate 793, but other component (for example, active and/or passive component) can also be attached to this substrate 793.For example, as in figure Shown in 14, semiconductor crystal grain 1427 can be attached (for example, chip bonding, wire bonding, etc.) to this substrate 793.Should Semiconductor grain 1427 is to be attached to this substrate 793 in the way of a kind of laterally adjacent this assembly 700I.In this kind of attachment Afterwards, encapsulating structure discussed herein (for example, interconnection structure, molding, lid, etc.) any one then can be formed.
In the embodiment of another example, other components can be coupled to assembly 700I in the assembly of a vertical stack Tip side.Figure 15 is an example showing this kind of assembly 1500C.One the 3rd crystal grain 1527 and one the 4th crystal grain 1528 (for example, its non-active side) can be attached to the top of this assembly 700I.This kind of attachment for example can be using adhesive agent come in addition Execution.Joint sheet on the master end of the 3rd crystal grain 1527 and the 4th crystal grain 1528 then can extremely should by wire bonding Substrate 793.It is noted that being attached in the plot on this assembly 700I in wherein one RDL and/or substrate, should 3rd crystal grain 1527 and/or the 4th crystal grain 1528 can be joined to this kind of RDL and/or substrate by flip.After this kind of attachment, Encapsulating structure discussed herein (for example, interconnection structure, molding, lid, etc.) any one then can be formed.
In another one example implementation, another component can be coupled to the bottom side of this substrate.Figure 16 is that displaying is this kind of One example of assembly.One the 3rd crystal grain 1699 is the bottom side being attached to this substrate 793, e.g. in this substrate 793 In a gap between interconnection structure on bottom side.After this kind of attachment, encapsulating structure discussed herein (for example, interconnects Structure, molding, lid, etc.) any one then can be formed.
Shown in Fig. 8-16 and the method for example discussed herein and assembly are nonrestrictive example, its It is to be presented with the various features describing this content of the invention.This kind of method and assembly can also be with the U.S.s in following co-applications In state's patent application case, arbitrary or all of feature shared by the method shown and discuss and assembly：On January 29th, 2013 Shen Please and entitled " semiconductor device and manufacture semiconductor device method " U.S. patent application case sequence number 13/753,120； On April 16th, 2013 application and the U.S. patent application case sequence number 13/ of entitled " semiconductor device and the method manufacturing it " 863,457；On November 19th, 2013 application and U.S. of entitled " there is the semiconductor device of the well of straight-through silicon perforation-less deep " State's patent application serial no 14/083,779；On March 18th, 2014 application and entitled " semiconductor device and the side manufacturing it The U.S. patent application case sequence number 14/218,265 of method "；On June 24th, 2014 application and entitled " semiconductor device and system The U.S. patent application case sequence number 14/313,724 of the method for making it "；On July 28th, 2014 application and entitled " have thin Redistribution layer semiconductor device " U.S. patent application case sequence number 14/444,450；On October 27th, 2014 application and name It is referred to as the U.S. patent application case sequence number 14/524,443 of " there is the semiconductor device of the thickness of reduction "；On November 4th, 2014 Application and entitled " mediator, its manufacture method, utilize its semiconductor packages and be used for manufacturing this semiconductor packages Method " U.S. patent application case sequence number 14/532,532；On November 18th, 2014 application and entitled " there is sticking up of reduction The U.S. patent application case sequence number 14/546,484 of bent semiconductor device "；And on March 27th, 2015 application and entitled " The U.S. patent application case sequence number 14/671,095 of semiconductor device and the method manufacturing it "；Those U.S. patent application case The content of each hereby here is integrally incorporated by reference with it.
Discussion in this is the figure of the illustration comprising many, and it is the various portions showing semiconductor package assembling Point.In order to clearly illustrate, these figures do not show all features of the assembly of each example.The example that here presents The assembly that any one of assembly can present with other heres any one or all share arbitrary or all of feature. For example and nonrestrictive, any one or its part that are relevant to the assembly of the example that Fig. 1-7 shows and discusses all may be used Be included into the assembly being relevant to the example that Fig. 8-16 is discussed any one.On the contrary, be relevant to Fig. 8-16 and being shown and discussed Any one of the assembly stated can be included into and be relevant to the assembly that Fig. 1-7 shows and discusses.
In a word, the various features of this content of the invention are to provide a kind of semiconductor device or encapsulating structure and one kind to be used for making The method making it.Although previous content to be described by reference to some features and example, will be familiar with this Operator understands and can make various changes, and equivalent can be replaced, without deviating from the category of present invention. Furthermore, it is possible to make many modifications a specific situation or material to be adapted to the teaching of present invention, without deviating from it Category.Therefore, desired is that present invention is not only restricted to disclosed specific example, but present invention will comprise Fall into all of example in the appended category of claim.

Claims (20)

1. a kind of semiconductor device, it includes：
Redistribution structure, it includes：
First redistribution layer, it includes：
First dielectric layer, it includes the first dielectric material；And
The circuit of the first conduction；And
Second redistribution layer, it includes：
Second dielectric layer, it includes the second dielectric material different from described first dielectric material；And
The circuit of the second conduction, it is electrically coupled to the circuit of described first conduction；
First semiconductor grain, it is attached to described first redistribution layer；
Second semiconductor grain, it is attached to described first redistribution layer；And
Conductive interconnection structure, it is attached to described second redistribution layer.
2. semiconductor device as claimed in claim 1, wherein said first redistribution layer is by shape in a silicon wafer process Become, and described second redistribution layer is to be formed in the processing procedure of wafer after one.
3. semiconductor device as claimed in claim 1, wherein said first dielectric material is a kind of inorganic material, and described Second dielectric material is a kind of organic material.
4. semiconductor device as claimed in claim 1, wherein said redistribution structure include described first dielectric layer with Oxide skin(coating) between described second dielectric layer.
5. semiconductor device as claimed in claim 1, it includes：
Molding material, it covers at least one upper surface of described redistribution structure and first and second semiconductor grain described The individual other lateral side surfaces of each；And
Conductive perforation, it is from that described redistribution structure extends to described molding material through described molding material Surface.
6. semiconductor device as claimed in claim 5, it is included on the described upper surface of described molding material and in institute State the 3rd distribution layer again on first and second semiconductor grain, the described 3rd again distribution layer be electrically connected to described conduction Perforation.
7. semiconductor device as claimed in claim 1, it includes being attached to the base plate for packaging of the interconnection structure of described conduction.
8. semiconductor device as claimed in claim 7, it includes the 3rd crystal grain being electrically coupled to described base plate for packaging.
9. a kind of semiconductor device, it includes：
Redistribution structure, it includes：
The redistribution layer of top, it includes：
First dielectric layer, it includes the first dielectric material；And
The circuit of the first conduction；And
The redistribution layer of lower section, it includes：
Second dielectric layer, it includes the second dielectric material；And
The circuit of the second conduction, it is electrically coupled to the circuit of described first conduction；
First semiconductor grain, it is attached to a upper side of described redistribution structure；
Second semiconductor grain, it is attached to the described upper side of described redistribution structure；
First molding material, it covers at least described upper side of described redistribution structure and described first and second is partly led Individual other cross side of each of body crystal grain；
Substrate, it includes being attached to the substrate-side on a lower side of described redistribution structure；And
Second molding material, it at least covers the substrate-side of described top, a cross side of described first molding material, Yi Jisuo State a cross side of redistribution structure.
10. semiconductor device as claimed in claim 9, wherein said first molding material and described second molding material are Different materials.
11. semiconductor devices as claimed in claim 9, the outer surface of wherein said first molding material includes sticking together strengthening Feature, its strengthening sticking together between the described first molding material and described second molding material.
12. semiconductor devices as claimed in claim 9, wherein：
Described first molding material includes the first molding top surface；And
Described second molding material includes second molding top surface coplanar with the described first molding top surface.
13. semiconductor devices as claimed in claim 9, it includes：
First primer packing material, it is between described redistribution structure and described first semiconductor grain and described Between redistribution structure and described second semiconductor grain；And
Second primer packing material, its between described substrate and described redistribution structure, first and second bottom wherein said Glue packing material is different materials.
14. semiconductor devices as claimed in claim 9, it includes：
First primer packing material, it is between described redistribution structure and described first semiconductor grain and described Between redistribution structure and described second semiconductor grain；And
Second primer packing material,, between described substrate and described redistribution structure, wherein said second primer is filled for it First primer packing material described in material directly contact.
15. semiconductor devices as claimed in claim 9, it includes a kind of primer packing material, and it is in described redistribution knot Between structure and described first semiconductor grain and between described redistribution structure and described second semiconductor grain, its Described in primer packing material include the cross side that is orthogonal of described upper side with described redistribution structure.
16. semiconductor devices as claimed in claim 9, it includes a kind of primer packing material, and it is in described redistribution knot Between structure and described first semiconductor grain and between described redistribution structure and described second semiconductor grain, its Described in primer packing material include and the described first molding described cross side of the material and institute of described redistribution structure State the coplanar cross side of cross side.
A kind of 17. semiconductor devices, it includes：
Redistribution structure, it includes：
The redistribution layer of top, it includes：
First dielectric layer, it includes the first dielectric material；And
The circuit of the first conduction；
The redistribution layer of lower section, it includes：
Second dielectric layer, it includes one second dielectric material；And
The circuit of the second conduction, it is electrically coupled to the circuit of described first conduction；And
Multiple conductive poles, it extends and is attached to the circuit of described second conduction from the redistribution layer of described lower section；
First semiconductor grain, it is attached to a upper side of described redistribution structure；And
Second semiconductor grain, it is attached to the described upper side of described redistribution structure.
18. semiconductor devices as claimed in claim 17, it includes being attached to the substrate of described conductive pole.
19. semiconductor devices as claimed in claim 18, it includes：
First primer packing material, it is between described redistribution structure and described first semiconductor grain and described Between redistribution structure and described second semiconductor grain；And
Second primer packing material, its between described substrate and described redistribution structure, first and second bottom wherein said Glue packing material is different materials.
20. semiconductor devices as claimed in claim 17, wherein said second dielectric material and described first dielectric material It is different materials.
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