CN206564245U - A kind of fan-out-type wafer level packaging structure - Google Patents
A kind of fan-out-type wafer level packaging structure Download PDFInfo
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- CN206564245U CN206564245U CN201720282135.0U CN201720282135U CN206564245U CN 206564245 U CN206564245 U CN 206564245U CN 201720282135 U CN201720282135 U CN 201720282135U CN 206564245 U CN206564245 U CN 206564245U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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Abstract
The utility model provides a kind of fan-out-type wafer level packaging structure, wherein, encapsulating structure at least includes：Re-wiring layer；It is bonded at least one at least two first projection that there is the flip-chip of projection protection structure and the re-wiring layer upper surface is formed at of the re-wiring layer upper surface；The connection gap and the plastic packaging layer of a part for the parcel flip-chip with projection protection structure and first projection being formed between the full flip-chip with projection protection structure of filling of the re-wiring layer upper surface and the re-wiring layer；And it is formed at the second projection of the re-wiring layer lower surface.Plastic packaging layer in the utility model is that seamless bonding and good connected structure are provided between flip-chip and re-wiring layer, it is to avoid the risk of interface debonding, improves the reliability of encapsulating structure；Simultaneously using the flip-chip with projection protection structure, effectively protection and fixed interconnection projection prevents interconnection projection failure.
Description
Technical field
The utility model is related to technical field of semiconductor encapsulation, more particularly to a kind of fan-out-type wafer level packaging structure.
Background technology
It is more inexpensive, more reliable, faster and more highdensity circuit be integrated antenna package pursue target.In future,
Integrated antenna package will improve the integration density of various electronic components by constantly reducing minimum feature size.At present, first
The method for packing entered includes：Wafer chip level chip-scale package (Wafer Level Chip Scale Packaging,
WLCSP), fan-out-type wafer-level packaging (Fan-Out Wafer Level Package, FOWLP), flip-chip (Flip
Chip), stacked package (Package on Package, POP) etc..
Fan-out-type wafer-level packaging is a kind of embedded chip method for packing of wafer level processing, be current a kind of input/
Output port (I/O) is more, one of the integrated preferable Advanced Packaging method of flexibility.Fan-out-type wafer-level packaging is compared to routine
Wafer-level packaging have the advantages that its is unique：1. I/O spacing is flexible, independent of chip size；2. effective nude film is only used
(die), product yield is improved；3. there is flexible 3D package paths, you can to form the figure of General Cell at top；4. have
There are preferable electrical property and hot property；5. frequency applications；6. easily high-density wiring is realized in re-wiring layer (RDL).
At present, fan-out-type wafer-level packaging method is generally：Carrier is provided, in carrier surface formation adhesive layer；First is situated between
Electric layer on adhesive layer photoetching, electroplate out re-wiring layer (Redistribution Layers, RDL)；Using chip bonding/
Semiconductor chip is arranged on re-wiring layer by controlled collapsible chip connec-tion；Carry out overall drying；Carry out capillary underfill
(CUF)；Overall drying is carried out again；Using Shooting Technique by semiconductor chip plastic packaging in capsulation material layer in；Plastic packaging grinds, opened
Through hole；Fill through hole；Photoetching, electroplate out metal layer under ball；Carry out planting ball backflow, form welded ball array；Remove carrier.Its
In, the connection gap between flip-chip and re-wiring layer needs to use a large amount of capillary underfills for loading filler particles
Material carries out capillary underfill, and underfill is extremely important to the reliability of flip chip devices, and it can avoid upside-down mounting
Chip device breaks down because of the coefficient of thermal expansion mismatch (CTE) between chip and organic substrate.
However, with the development of semicon industry, above-mentioned fan-out-type wafer-level packaging method and obtained fan-out-type are brilliant
Circle class encapsulation structure can not increasingly meet package requirements.On the one hand, technique is cumbersome, and cost is higher, can not gradually meet collection
Into the package requirements of circuit.On the other hand, with the integration density more and more higher of semiconductor devices, flip-chip and rewiring
Connection gap between layer also becomes less and less, and capillary underfill can not be smooth and to be rapidly flowing into these narrow
Gap, causes technology difficulty to improve；Also, capillary Underfill layer 6 ' and injection molded layers in fan-out-type wafer level packaging structure
6 have contact interface, part A as shown in Figure 1, and the part is easy to interface debonding occur when being stressed effect, from
And have a strong impact on the reliability of encapsulating structure.
Therefore, how to solve the above problems there is provided a kind of technique it is simpler, it is low into more this, better reliability and more adapt to
The fan-out-type wafer level packaging structure of highly integrated device encapsulation is necessary.
The content of the invention
The shortcoming of prior art in view of the above, the purpose of this utility model is to provide a kind of fan-out-type wafer scale envelope
Assembling structure, the technique for solving fan-out-type wafer-level packaging method in the prior art is cumbersome, and difficulty and cost are higher, and encapsulation
The problem of structure Presence of an interface risk of delamination, influence reliability.
In order to achieve the above objects and other related objects, the utility model provides a kind of fan-out-type wafer level packaging structure,
Wherein, the fan-out-type wafer level packaging structure at least includes：
Re-wiring layer；
It is bonded at least one flip-chip with projection protection structure and the formation of the re-wiring layer upper surface
At least two first projections in the re-wiring layer upper surface, the flip-chip with projection protection structure and described
First projection is realized with the re-wiring layer and is electrically connected with, and the top of first projection higher than described there is projection to protect
The top of the flip-chip of protection structure；
It is formed at the filling full flip-chip and institute with projection protection structure of the re-wiring layer upper surface
State the connection gap between re-wiring layer and wrap up the flip-chip and first projection with projection protection structure
A part plastic packaging layer；And
It is formed at the second projection of the re-wiring layer lower surface.
Preferably, the re-wiring layer at least includes：
Multiple first pads；
It is covered in the first dielectric layer of the first pad upper surface and side wall；
The metal wiring layer being electrically connected with can be realized with first pad by being formed in first dielectric layer, its
In, the metal wiring layer is single metal layer or more metal layers；
Be formed at the first dielectric layer upper surface can with the metal wiring layer realize be electrically connected with it is multiple under
Metal layer, finally gives the re-wiring layer；
Wherein, the flip-chip with projection protection structure is bonded to the upper surface of the lower metal layer, and logical
Cross the lower metal layer realization and the electric connection of the re-wiring layer.
Preferably, the flip-chip with projection protection structure at least includes：
Bare chip；
It is formed at the articulamentum of the bare chip upper surface；And
Be formed at the interconnection projection on the articulamentum, and the interconnection projection by the articulamentum realize with it is described naked
The electric connection of chip；
It is formed at the articulamentum upper surface and surrounds part and interconnect the passivation layer of projection, so as to forms projection protection knot
Structure；
Wherein, the flip-chip with projection protection structure by it is described interconnection bump bond in the lower metallization
The upper surface of layer, so as to realize the electric connection with the re-wiring layer.
Preferably, the articulamentum at least includes：
It is formed at multiple second pads of the bare chip upper surface；
It is covered in second dielectric layer at the chip upper surface and each second pad two ends；And
It is formed at the insulating barrier of the second dielectric layer upper surface.
Preferably, the interconnection projection is formed at upper surface and the covering part insulating barrier of each second pad, and described
Interconnect projection and pass through second pad realization and the electric connection of the bare chip.
Preferably, first projection, second projection and the interconnection projection are respectively by metal column and are formed at
The metallic combination structure of the metal cap composition of the metal column upper surface, or first projection, second projection and institute
It is respectively metal welding pellet to state interconnection projection.
Preferably, the metal column uses Cu or Ni metal materials, and the metal cap and the metal welding pellet are adopted respectively
With a kind of material in tin, copper, nickel, silver-colored gun-metal or kamash alloy.
Preferably, first dielectric layer and second dielectric layer use low k dielectric.
Preferably, the plastic packaging layer is using a kind of curing materials in polyimides, silica gel and epoxy resin.
As described above, fan-out-type wafer level packaging structure of the present utility model, has the advantages that：The utility model
Encapsulating structure in the full connection gap between flip-chip and re-wiring layer of plastic packaging layer filling and wrap up flip-chip, be
Seamless bonding and good connected structure are provided between flip-chip and re-wiring layer, it is to avoid the wind of interface debonding
Danger, improves the reliability of encapsulating structure, is more suitable for highly integrated device encapsulation.Meanwhile, the utility model is used with convex
The flip-chip of block protection structure, effectively can protect and fix interconnection projection, enhancing interconnection projection intensity, prevent stress compared with
The problems such as interconnection projection crack is caused when big and cause interconnection projection failure.Also, the utility model is carried out using capsulation material
Underfill, capsulation material can be rapidly flowing into the connection gap between flip-chip and re-wiring layer with smooth, reduction
Technology difficulty so that the connection gap between flip-chip and re-wiring layer can be smaller.Also, the utility model is more easy to
Prepare, be conducive to simplification of flowsheet, reduce cost, improve packaging efficiency, improve integrated level and yield rate.
Brief description of the drawings
Fig. 1 is shown as the capillary Underfill layer in the fan-out-type wafer level packaging structure of the utility model prior art
There is the schematic diagram of contact interface between injection molded layers.
Fig. 2 is shown as the fan-out-type wafer level packaging structure schematic diagram of the utility model first embodiment.
Fig. 3 is shown as in the fan-out-type wafer level packaging structure of the utility model first embodiment there is projection to protect knot
The structural representation of the flip-chip of structure.
Fig. 4 is shown as the flow of the preparation method of the fan-out-type wafer level packaging structure of the utility model second embodiment
Schematic diagram.
Each step of fan-out-type wafer-level packaging method that Fig. 5~Figure 11 is shown as the utility model second embodiment is in
Existing structural representation.
Figure 12~Figure 22 is shown as step S3 in the fan-out-type wafer-level packaging method of the utility model second embodiment
The structural representation that the middle each step of specific method for preparing the flip-chip with projection protection structure is presented.
Component label instructions
1 carrier
2 adhesive layers
3 re-wiring layers
31 first pads
32 first dielectric layers
33 metal wiring layers
34 times metal layers
4 have the flip-chip of projection protection structure
10 wafers
100 bare chips
200 articulamentums
201 second pads
202 second dielectric layers
203 insulating barriers
300 metal seed layers
400 lithographic mask layers
500 interconnection projections
501 metal columns
502 metal caps
600 passivation materials
601 passivation layers
5 first projections
6 plastic packagings layer
6 ' capillary Underfill layers
7 second projections
S1~S6 steps
Embodiment
Illustrate embodiment of the present utility model below by way of specific instantiation, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages of the present utility model and effect easily.The utility model can also be by addition
Different embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering
With, without departing from it is of the present utility model spirit under carry out various modifications or alterations.
Referring to Fig. 2, first embodiment of the present utility model is related to a kind of fan-out-type wafer level packaging structure.Need
Bright, the diagram provided in present embodiment only illustrates basic conception of the present utility model in a schematic way, then in schema
Only display is drawn with relevant component in the utility model rather than according to component count, shape and the size during actual implement, its
Kenel, quantity and the ratio of each component can be a kind of random change during actual implementation, and its assembly layout kenel may also be more
For complexity.
As shown in Fig. 2 the fan-out-type wafer level packaging structure of present embodiment, it at least includes：
Re-wiring layer 3；
At least one for being bonded to the upper surface of re-wiring layer 3 has the flip-chip 4 and shape of projection protection structure
At least two first projections 5 of the upper surface of re-wiring layer 3 described in Cheng Yu, the flip-chip 4 with projection protection structure
Realize and be electrically connected with the re-wiring layer 3 with first projection 5, and first projection 5 top higher than described
The top of flip-chip 4 with projection protection structure；
It is formed at the full He of flip-chip 4 with projection protection structure of filling of the upper surface of re-wiring layer 3
Connection gap and the parcel flip-chip 4 and described first with projection protection structure between the re-wiring layer 3
The plastic packaging layer 6 of a part for projection 5；And
It is formed at the second projection 7 of the lower surface of re-wiring layer 3.
In the fan-out-type wafer level packaging structure of present embodiment, the filling of plastic packaging layer 6 falling completely with projection protection structure
The flip-chip of connection gap and parcel with projection protection structure between cartridge chip 4 and re-wiring layer 3, on the one hand can
Interconnection portion between flip-chip 4 and re-wiring layer 3 of the protection with projection protection structure, on the other hand for projection
Seamless bonding and good connected structure are provided between the flip-chip and re-wiring layer of protection structure, with good
Packaging effect, it is to avoid the risk of interface debonding, improve the reliability of encapsulating structure, be more suitable for highly integrated device envelope
Dress, is with a wide range of applications in field of semiconductor package.In addition, when forming plastic packaging layer 6, bottom is carried out using capsulation material
Portion fill, capsulation material can be rapidly flowing into smooth flip-chip 4 and re-wiring layer 3 with projection protection structure it
Between connection gap, reduce technology difficulty, can be used in smaller connection gap.
In the present embodiment, please continue to refer to Fig. 2, re-wiring layer 3 at least includes：
Multiple first pads 31；
It is covered in the first dielectric layer 32 of the upper surface of the first pad 31 and side wall；
The metal line being electrically connected with can be realized with first pad 31 by being formed in first dielectric layer 32
Layer 33, wherein, the metal wiring layer 33 is single metal layer or more metal layers；
Be formed at the upper surface of the first dielectric layer 32 can realize many of electric connection with the metal wiring layer 33
Individual lower metal layer 34, finally gives the re-wiring layer 3；
Wherein, the flip-chip 4 with projection protection structure is bonded to the upper surface of the lower metal layer 34, and
The electric connection with the re-wiring layer 3 is realized by the lower metal layer 34.
In the present embodiment, metal wiring layer 33 can be single metal layer or more metal layers.As an example, metal
Wiring layer 33 can use a kind of material or two or more combined materials in copper, aluminium, nickel, gold, silver, titanium.
In addition, in the present embodiment, the second projection 7 is formed at the lower surface of first pad 31, and by described
First pad 31 realizes the electric connection with re-wiring layer 3.
In the present embodiment, as shown in figure 3, the flip-chip 4 with projection protection structure at least includes：
Bare chip 100；
It is formed at the articulamentum 200 of the upper surface of bare chip 100；And
The interconnection projection 500 on the articulamentum 200 is formed at, and the interconnection projection 500 passes through the articulamentum 200
Realize the electric connection with the bare chip 100；
It is formed at the upper surface of articulamentum 200 and surrounds part and interconnect the passivation layer 601 of projection 500, so as to forms projection guarantor
Protection structure；
Wherein, the flip-chip 4 with projection protection structure is bonded to the lower gold by the interconnection projection 500
The upper surface of categoryization layer 34, so as to realize the electric connection with the re-wiring layer 3.The filling of plastic packaging layer 6 completely there is projection to protect
Connection gap between the flip-chip 4 and re-wiring layer 3 of protection structure, has projection protection structure so as to effectively protection
Flip-chip 4 in not passivated layer 601 surround protection interconnection projection 500 top.
Wherein, the articulamentum at least includes：
It is formed at multiple second pads 201 of the upper surface of bare chip 100；
It is covered in second dielectric layer 202 at the upper surface of bare chip 100 and each two ends of second pad 201；And
It is formed at the insulating barrier 203 of the upper surface of the second dielectric layer 202.
Wherein, the interconnection projection 500 is formed at upper surface and the covering part insulating barrier 203 of each second pad 201,
And the interconnection projection 500 realizes the electric connection with the bare chip 100 by second pad 201.
As an example, insulating barrier 203 can be using materials such as silica or PET.
In addition, it is necessary to which what is explained is, although only include in the structural representation shown in Fig. 3 two the second pads 201, two
Projection 500 is interconnected, but Fig. 3 is only in order to which specific explanations have the simple signal that the flip-chip 4 of projection protection structure is drawn
Figure, in fact, the flip-chip with projection protection structure in present embodiment can include multiple second pads 201, it is many
Individual interconnection projection 500, not using the structural representation shown in Fig. 3 as limitation.
In addition, in a preferred scheme of present embodiment, the interconnection projection 500 is by metal column 501 and formed
The metallic combination structure that metal cap 502 in the upper surface of metal column 501 is constituted.
Specifically, interconnection projection 500 at least includes：
It is formed at the metal column 501 of each upper surface of pad 201 and covering part insulating barrier 203；And
It is formed at the metal cap 502 of the upper surface of metal column 501.
Wherein, passivation layer 601 is suitable to form corresponding perforate by surrounding part interconnection projection 500, interconnection projection 500
A part is outside perforate, and another part is located in perforate, and the portion of the passivating layer 601 around perforate and interconnection projection
500 are brought into close contact, and form the structure presented such as Fig. 1.Due to close with the portion of the passivating layer 601 of interconnection projection 500 joint place
Interconnection projection 500 is surrounded, therefore passivation layer 601 effectively can protect and fix interconnection projection 500, enhancing interconnection projection 500
Intensity, the problems such as preventing from causing interconnection 500 crack of projection when stress is larger and cause interconnection projection failure.It is preferred as one
Scheme, passivation layer 601 surrounds metal column 501, i.e.,：Portion of the passivating layer 601 around perforate is surrounded interconnection projection 500 and wrapped
The metal column 501 contained, and be fitted tightly on the outer wall of metal column 501, so, metal cap 502 is on the one hand completely exposed,
Do not interfere with metal cap 502 to be bonded with external substrate, the comprehensive surrounding metal column 601 of another aspect passivation layer 601, can be interconnection
Projection 500 provides more preferable support force, so as to improve the intensity of interconnection projection 500, makes interconnection projection 500 more firm, anti-failure
Effect is also more preferable.Certainly, in other implementations, passivation layer 601 can also only surround part metals post 501.
And first projection 5 and second projection 7 can also be used and the interconnection identical metallic combination knot of projection 500
Structure.It is by metal column 501 and to be formed at the gold that the metal cap 502 of the upper surface of metal column 501 is constituted in first projection 5
When belonging to combining structure, the metal post part of parcel first projection 5 of plastic packaging layer 6, the metal cap part of the first projection 5 is sudden and violent
It is exposed to outside plastic packaging layer 6.
As an example, metal column 501 can use Cu or Ni metal materials.Wherein, metal column 501 is preferred to use Cu posts.
As an example, metal cap 502 can be using a kind of material in tin, copper, nickel, silver-colored gun-metal or kamash alloy
Material, includes but is not limited to this.
And in another scheme of present embodiment, the interconnection projection 500 can also be metal welding pellet (solder
ball).And first projection 5 and second projection 7 can also be metal welding pellet.It is metal in first projection 5
During solder ball, a part for parcel first projection 5 of plastic packaging layer 6, the top of the first projection 5 is exposed to outside plastic packaging layer 6,
The tip height of the first projection 5 outside plastic packaging layer 6 can be adjusted as needed.
As an example, metal welding pellet can be using a kind of material in tin, copper, nickel, silver-colored gun-metal or kamash alloy
Material, includes but is not limited to this.
Relative to the scheme that first projection 5 is only metal welding pellet, first projection 5 is metal column combination metal
The scheme of cap is more beneficial for saving package area.
In the present embodiment, the first dielectric layer 32 and the second dielectric layer 202 use low k dielectric.As an example,
First dielectric layer 32 and the second dielectric layer 202 can using epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and
A kind of material in fluorine-containing glass.
As an example, plastic packaging layer 6 is using a kind of curing materials in polyimides, silica gel and epoxy resin.
The plastic packaging layer 6 not only acts as the effect of the flip-chip 4 with projection protection structure described in plastic packaging, and it combines institute
State the first projection 5, it is possible to achieve stack type package.
In addition, the fan-out-type wafer level packaging structure of present embodiment not only has stack type package ability, it may have many
Sample packaging body binding ability.Packaging body can be bonded directly to the top of the first projection 5 outside plastic packaging layer 6, can also
The second projection is bonded directly to, packaging efficiency is improved, encapsulation process is also simpler, so as to reduce cost.Wherein, encapsulate
Body can Selective type and bonding position as needed, so as to meet various application demand.
Therefore, the encapsulating structure fan-out-type wafer scale of present embodiment completely there is projection to protect by the filling of plastic packaging layer
The flip-chip of connection gap and parcel with projection protection structure between the flip-chip and re-wiring layer of protection structure, be
Seamless bonding and good connected structure are provided between flip-chip and re-wiring layer with projection protection structure,
The risk of interface debonding is avoided, the reliability of encapsulating structure is improved, with good packaging effect, is more suitable for highly integrated
Device encapsulation is spent, is with a wide range of applications in field of semiconductor package.Also, underfill is carried out using capsulation material,
Capsulation material can be rapidly flowing into the connection between the flip-chip with projection protection structure and re-wiring layer with smooth
Gap, reduces technology difficulty so that the connection gap between flip-chip and re-wiring layer with projection protection structure
Can be smaller.In addition, the flip-chip with projection protection structure in present embodiment, by being set up on the surface of chip 100
The passivation layer 601 of interconnection projection 500 is surrounded, so as to form projection protection structure, interconnection projection effectively can be protected and fix
500, the intensity of enhancing interconnection projection 500, the problems such as preventing from causing interconnection 500 crack of projection when stress is larger and cause interconnection convex
Block 500 fails.
Fig. 4-Figure 10 is referred to, the utility model second embodiment is related to a kind of system of fan-out-type wafer level packaging structure
Preparation Method, for preparing the fan-out-type wafer level packaging structure involved by the utility model first embodiment.
As shown in figure 4, the preparation method of the fan-out-type wafer level packaging structure of present embodiment at least comprises the following steps：
Step S1 is there is provided a carrier 100, in forming adhesive layer on the carrier, as shown in Figure 5.
In the present embodiment, carrier 1 provides rigid for follow-up adhesive layer 2, re-wiring layer 3, the plastic packaging layer 6 etc. of making
Structure or matrix.As an example, carrier 100 can use one kind in silicon, glass, silica, ceramics, polymer and metal
Material or two or more composites, its shape can for wafer shape, it is square or it is other it is any needed for shape.
In the present embodiment, adhesive layer 2 in subsequent technique as the separating layer between re-wiring layer 3 and carrier 1,
It is preferably made from the jointing material with smooth finish surface, and it must have certain adhesion with re-wiring layer 3, to protect
Demonstrate,prove situations such as re-wiring layer 3 will not produce mobile in subsequent technique, in addition, its also have with the carrier 1 it is stronger
Adhesion, in general, the adhesion of itself and the carrier 1 needs to be more than the adhesion with the re-wiring layer 3.As
Example, the material of the adhesive layer 2 is selected from the two-sided adhesive tape for being respectively provided with viscosity or the adhesive glue made by spin coating proceeding etc..Institute
State adhesive tape and be preferred to use UV adhesive tapes, it is easy to pull off after UV light irradiations.In other embodiments, the adhesive layer 2
Also the other materials layer that physical vaporous deposition or chemical vapour deposition technique refer to, such as epoxy resin (Epoxy), silicon rubber be can select
Glue (silicone rubber), polyimides (PI), polybenzoxazoles (PBO), benzocyclobutene (BCB) etc..In later separation
During the carrier 1, the adhesive layer 2 can be removed using methods such as wet etching, cmps.
Step S2, forms re-wiring layer 3, as shown in Figure 6 in the upper surface of the adhesive layer 2.
Step S3, prepares the flip-chip with projection protection structure, is bonded in the upper surface of the re-wiring layer
Few one flip-chip with projection protection structure simultaneously forms at least two first projections, described with projection protection structure
Flip-chip and first projection are realized with the re-wiring layer and are electrically connected with, and the top of first projection is higher than
The top of the flip-chip with projection protection structure, as shown in Figure 7 and Figure 8.
In the present embodiment, step S2 specific method is：
Step S201, multiple first pads 31 are formed in the upper surface of the adhesive layer 2.
Step S202, the of the covering upper surface of the first pad 31 and side wall is formed in the upper surface of the adhesive layer 2
One dielectric layer 32.
Step S203, the gold being electrically connected with can be realized in being formed in first dielectric layer 32 with first pad 31
Belong to wiring layer 33, wherein, the metal wiring layer 33 is single metal layer or more metal layers.
Step S204, being formed in the upper surface of first dielectric layer 32 can realize electrically with the metal wiring layer 33
Multiple lower metal layers 34 of connection, finally give the re-wiring layer 3, as shown in Figure 6；Wherein, it is described that there is projection to protect
The flip-chip 4 of protection structure is bonded to the upper surface of the lower metal layer 34, and by the lower metal layer 34 realize with
The electric connection of the re-wiring layer 3, as shown in Figure 7.
As an example, the first pad 31 can use a kind of material or two or more in copper, aluminium, nickel, gold, silver, titanium
Combined material.
In the present embodiment, metal wiring layer 201 can be single metal layer or more metal layers, and more metal layers can
Obtained by the way of the first dielectric layer and metal level is alternately prepared.As an example, metal wiring layer 201 can using copper, aluminium,
A kind of material or two or more combined materials in nickel, gold, silver, titanium, and can select physical vaporous deposition (PVD), chemistry
At least one of vapour deposition process (CVD), sputtering method, plating and chemical plating method is formed.
In the present embodiment, the first dielectric layer 32 uses low k dielectric.As an example, the first dielectric layer 32 can be with
Using a kind of material in epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass, it is possible to use
The techniques such as spin coating, CVD, plasma enhanced CVD the first dielectric layer of formation.
As an example, lower metal layer (Under Bump Metallization, UBM) 34 can be by one layer of conductive layer
Constitute or be made up of plurality of conductive layers, conductive layer can use a kind of material or two in copper, aluminium, nickel, gold, silver, titanium
Plant the combined material of the above, it is possible to prepare using PVD, CVD, plating, chemical deposit or other metal deposition process.
As shown in figure 3, the flip-chip 4 with projection protection structure at least includes：Bare chip 100；It is formed at institute
State the articulamentum 200 of the upper surface of bare chip 100；And the interconnection projection 500 on the articulamentum 200 is formed at, and it is described mutual
Join projection 500 and pass through the articulamentum 200 realization and the electric connection of the bare chip 100；Wherein, it is described that there is projection protection
The flip-chip 4 of structure is bonded to the upper surface of the lower metal layer 34 by the interconnection projection 500, so as to realize and institute
State the electric connection of re-wiring layer 3.Wherein, the upper surface bonding in the re-wiring layer in step S3 is described with convex
The flip-chip of block protection structure, specific method is：
Scaling powder glue-line is formed in the upper surface of the upper surface of the interconnection projection 500 or the lower metal layer 34；
By the position where lower metal layer 34 described in the top alignment of the interconnection projection 500, Reflow Soldering is then carried out
Connect, so that the flip-chip 4 with projection protection structure is bonded to the lower metallization by the interconnection projection 500
The upper surface of layer 34.
It is to be understood that scaling powder glue-line can remove the oxidation on interconnection projection 500 and the lower surface of metal layer 34
Layer, improves the wetting effect of solder flux and the reliability of engagement.Scaling powder glue-line can be formed using modes such as dipping or sprayings,
Should be as thin as possible and uniform.
In addition, the flip-chip 4 with projection protection structure can include a variety of circuit structures, in the present embodiment, can
To be bonded the flip-chip 4 with projection protection structure of multiple same types, can also be bonded multiple different types of has
The flip-chip 4 of projection protection structure, can be selected as needed.When multiple flip-chips 4 with projection protection structure
Height it is inconsistent when, the top of first projection 5 is higher than the top of all flip-chips 4 with projection protection structure.
The preparation method of the fan-out-type wafer level packaging structure of present embodiment makes re-wiring layer on the carrier 1 first
3, then the flip-chip 4 with projection protection structure is connected with re-wiring layer 3 again, it is to avoid during traditional plastic packaging because
Contraction in capsulation material heat curing process causes the problem of chip shifts with re-wiring layer, greatly improved good
Rate.
Step S4, the full upside-down mounting with projection protection structure of filling is formed in the upper surface of the re-wiring layer 3
Connection gap and the parcel flip-chip 4 and institute with projection protection structure between chip 4 and the re-wiring layer 3
The plastic packaging layer 6 of a part for the first projection 5 is stated, as shown in Figure 9.
Wherein, when plastic packaging layer 6 are formed in the upper surface of the re-wiring layer 3, the plastic packaging layer 6 is by molding bottom
Portion's completion method is integrally formed, so that the company between the flip-chip 4 and the re-wiring layer 3 with projection protection structure
Seam gap is filled full, while making a part of quilt of the flip-chip 4 with projection protection structure and first projection 5
Wrap, and another part (tip portion) of first projection 5 is exposed to outside the plastic packaging layer 6.Plastic packaging layer 6 is on the one hand
The interconnection projection 500 between flip-chip 4 and re-wiring layer 3 with projection protection structure can be protected, is on the other hand
Seamless bonding and good engagement knot are provided between flip-chip 4 and re-wiring layer 3 with projection protection structure
Structure, with good packaging effect, it is to avoid the risk of interface debonding, improves the reliability of encapsulating structure, is more suitable for height
Integrated level device is encapsulated, and is with a wide range of applications in field of semiconductor package.In addition, when forming plastic packaging layer 6, using modeling
Closure material carries out molded underfill, and capsulation material can be rapidly flowing into the flip-chip with projection protection structure with smooth
Connection gap between 4 and re-wiring layer 3, will not be restricted as the capillary underfill of prior art,
Technology difficulty is reduced, can be used in smaller connection gap, be more suitable for stacked architecture.
As an example, plastic packaging layer 6 can use a kind of curing materials in polyimides, silica gel and epoxy resin, and
The formation of plastic packaging layer 6 can use spin coating proceeding, Shooting Technique, compressing and forming process, typography, transfer modling technique, liquid
Body sealant cures moulding process and vacuum lamination process etc..Plastic packaging layer 6 can also be effectively ensured with projection protection structure
Flip-chip 4 not by outside contamination.
As an example, the thickness of plastic packaging layer 6 is controlled by controlling the moulding process of plastic packaging layer 6, without subsequently carrying out again
Its thickness is thinned in grinding technics, greatlys save process costs.
In the present embodiment, the top of first projection 5 is outer exposed to plastic packaging layer, can as needed Direct Bonding it is each
Kind of packaging body, it is to avoid be thinned and the laser beam drilling process of plastic packaging layer, not only saves material, reduces pollution, it also avoid
Thinning process causes the damage of circuit structure.
Step S5, removes the carrier 1 and the adhesive layer 2, and the lower surface of exposure re-wiring layer 3 exposes first
The lower surface of pad 31, as shown in Figure 10.
As an example, carrier 1 can be removed using grinding technics, reduction process etc..
Step S6, in lower surface the second projection 7 of formation of the re-wiring layer 3, the second projection 7 is formed at described first
The lower surface of pad 31, and the electric connection with re-wiring layer 3 is realized by first pad 31, as shown in figure 11.
In addition, in a preferred scheme of present embodiment, the interconnection projection 500 is by metal column 501 and formed
The metallic combination structure that metal cap 502 in the upper surface of metal column 501 is constituted.And first projection 5 and described second
Projection 7 can also be used and the interconnection identical metallic combination structure of projection 500.First projection 5 be by metal column 501 and
When being formed at the metallic combination structure of the composition of metal cap 502 of the upper surface of metal column 501, the parcel of plastic packaging layer 6 is described
The metal post part of first projection 5, the metal cap part of the first projection 5 is outside plastic packaging layer 6.
As an example, metal column 501 can use Cu or Ni metal materials.Wherein, metal column 501 is preferred to use Cu posts.
The metal column 501 can be formed by techniques such as conventional thick photoresistance photoetching, development, metal deposits, can also pass through micro-embossing, gold
The techniques such as category deposition form the metal column 501.
As an example, metal cap 502 can be using a kind of material in tin, copper, nickel, silver-colored gun-metal or kamash alloy
Material, includes but is not limited to this.
And in another scheme of present embodiment, the interconnection projection 500 can also be metal welding pellet (solder
ball).And first projection 5 and second projection 7 can also be metal welding pellet.It is metal in first projection 5
During solder ball, a part for parcel first projection 5 of plastic packaging layer 6, the top of the first projection 5 is exposed to outside plastic packaging layer 6,
The tip height of the first projection 5 outside plastic packaging layer 6 can be adjusted as needed.
As an example, metal welding pellet can be using a kind of material in tin, copper, nickel, silver-colored gun-metal or kamash alloy
Material, includes but is not limited to this.
Relative to the scheme that first projection 5 is only metal welding pellet, first projection 5 is metal column combination metal
The scheme of cap is more beneficial for saving package area.
In addition, in the present embodiment, respectively the flip-chip 4 with projection protection structure can include and realize any function
Integrated circuit structure, and their thickness do not limited by the method for packing of present embodiment, can be same thickness,
It can be different-thickness.
In addition, in the present embodiment, falling with projection protection structure is prepared as shown in Figure 12~Figure 22, in step S3
Cartridge chip, specific method is：
Step A, one wafer 10 of offer, wafer 10 at least include several bare chips 100.
Step B, the articulamentum 200 in upper surface all upper surfaces of bare chip 100 of formation covering of wafer 10, such as Figure 12
It is shown.
Step B specific method is：
Step B1, in the upper surface of wafer 10 multiple second pads 201 are formed, as shown in figure 12.
Step B2, formed in the upper surface of wafer 10 and cover all upper surfaces of bare chip 100 and each second pad
Second dielectric layer 202 at 201 two ends, as shown in figure 12.
Step B3, the upper surface formation insulating barrier 203 in the second dielectric layer 202, so that articulamentum 200 is obtained, such as Figure 12
It is shown.
In the present embodiment, the second dielectric layer 202 uses low k dielectric.As an example, the second dielectric layer 202 can
With using a kind of material in epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass.
As an example, insulating barrier 203 can be using materials such as silica or PET.
Step C, on articulamentum 200 formed interconnection projection 500, and interconnection projection 500 by articulamentum 200 realize with it is naked
The electric connection of chip 100, as shown in Figure 13-Figure 18.
In step C, interconnection projection 500 is formed at upper surface and the covering part insulating barrier of each second pad 201
203, and interconnection projection 500 realizes the electric connection with bare chip 100 by the second pad 201.Wherein, step C specific side
Method is：
Step C1, the upper surface formation metal seed layer 300 in the pad 201 of insulating barrier 203 and second, as shown in figure 13.
Step C2, on metal seed layer 300 formed with opening lithographic mask layer 400, opening exposure the second pad
201 and the metal seed layer 300 of the top of partial insulative layer 203, as shown in figure 14.
Step C3, on the metal seed layer 300 in opening formed metal column 501, as shown in figure 15.
Step C4, the upper surface formation metal cap 502 in metal column 501, as shown in Figure 16 and Figure 17, first in metal column
501 upper surface forms metal cap material, it is formed metal cap 502 after flowing back.
Step C5, lithographic mask layer 400 and metal seed layer 300 below are removed, to be formed by metal column 501 and gold
Belong to the projection that cap 502 is constituted, as shown in figure 18.
As an example, when forming metal column 501, metal seed layer 300 of the electric plating method in opening can be used
Upper formation metal column 501.
As an example, metal column 501 can use Cu or Ni metal materials.Wherein, metal column 501 is preferred to use Cu posts.
As an example, metal cap 502 can be using a kind of material in tin, copper, nickel, silver-colored gun-metal or kamash alloy
Material, includes but is not limited to this.
Step D, in articulamentum 200 upper surface formed surround part interconnect projection 500 passivation layer 601, such as Figure 19-figure
Shown in 21.
In the present embodiment, step D specific method is：
Step D1, in articulamentum 200 upper surface formed parcel interconnection projection 500 passivation material 600, such as Figure 19 institutes
Show.
Step D2, the thickness of bare chip 100 according to actual needs are ground to the lower surface of wafer 10, such as Figure 20 institutes
Show.
Step D3, the upper surface to passivation material 600 are ground, until expose portion interconnects projection 500, so that shape
The passivation layer 601 of projection 500 is interconnected into encirclement part, as shown in figure 21.
Step E, to formed passivation layer 601 after wafer 10 carry out cutting burst, there is projection guarantor to form several
The flip-chip of protection structure, as shown in figure 22.In the present embodiment, cutting uses laser cutting parameter, gas flame cuttiug technique
Or plasma cutting process, preferably cut and use laser cutting parameter.
Therefore, the system to the flip-chip with projection protection structure is realized by above-mentioned steps A~step E
It is standby.Wherein, passivation layer 601 forms corresponding perforate when surrounding part interconnection projection 500, and a part for interconnection projection 500 is sudden and violent
It is exposed at outside perforate, another part is located in perforate, and the portion of the passivating layer 601 around perforate and interconnection projection 500 are close
Laminating, forms the structure presented such as Fig. 1.Closely surrounded and interconnected due to the portion of the passivating layer 601 with interconnection projection 500 joint place
Projection 500, therefore passivation layer 601 effectively can protect and fix interconnection projection 500, the intensity of enhancing interconnection projection 500 is prevented
Caused when stress is larger interconnection 500 crack of projection the problems such as and cause projection to fail.It is used as a preferred scheme, the passivation
Layer 601 surrounds the metal column 501, i.e.,：Portion of the passivating layer 601 around perforate surrounds what interconnection projection 500 was included
Metal column 501, and be fitted tightly on the outer wall of metal column 501, so, metal cap 502 is on the one hand completely exposed, will not
Influence metal cap 502 is bonded with external substrate, the comprehensive surrounding metal column 601 of another aspect passivation layer 601, can be interconnection projection
500 provide more preferable support force, so as to improve the intensity of interconnection projection 500, make interconnection projection 500 more firm, anti-failure effect
Also it is more preferable.Certainly, in other implementations, the passivation layer 601 can also only surround part metals post 501.
The preparation method of the flip-chip with projection protection structure of present embodiment, several can be prepared simultaneously
The flip-chip with projection protection structure involved by utility model first embodiment, technique is simple, and cost is low；Meanwhile,
Due to protecting projection using passivation layer 601, in the back-end process of flip-chip is prepared, eliminate stickup and remove diaphragm etc.
Step, technique is simpler, and further saves cost.
By above-mentioned steps S1~step S6, the fan-out-type obtained involved by the utility model first embodiment is made
Wafer level packaging structure.Wherein, the plastic packaging layer 6 not only acts as the flip-chip 4 with projection protection structure described in plastic packaging
Effect, it is with reference to first projection 5, it is possible to achieve stack type package.In addition, the fan-out-type wafer-level packaging of present embodiment
Structure not only has stack type package ability, it may have various packaging body binding ability.Packaging body can be bonded directly to exposure
The top of the first projection 5 outside plastic packaging layer 6, can also be bonded directly to the second projection, packaging efficiency is improved, and encapsulate
Process is also simpler, so as to reduce cost.Wherein, packaging body can Selective type and bonding position as needed, so as to meet many
The application demand of sample.
Therefore, the preparation method of the fan-out-type wafer level packaging structure of present embodiment is more easy to prepare, relative to existing
There is the preparation method in technology, enormously simplify technological process, reduce totle drilling cost, improve packaging efficiency, improve integrated
Degree and yield rate.
The step of various methods are divided above, be intended merely to description it is clear, can be merged into when realizing a step or
Some steps are split, multiple steps are decomposed into, as long as including identical logical relation, all protection domain in this patent
It is interior；To adding inessential modification in algorithm or in flow or introducing inessential design, but its algorithm is not changed
Core design with flow is all in the protection domain of the patent.
It is seen that, present embodiment is the method embodiment corresponding with first embodiment, first embodiment
In the relevant technical details mentioned in the present embodiment still effectively, in order to reduce repetition, repeat no more here.
In summary, the plastic packaging layer filling in encapsulating structure of the present utility model is completely between flip-chip and re-wiring layer
Connection gap and wrap up flip-chip, be seamless bonding to be provided between flip-chip and re-wiring layer and good
Connected structure, it is to avoid the risk of interface debonding, improves the reliability of encapsulating structure, is more suitable for highly integrated device envelope
Dress.Meanwhile, the utility model uses the flip-chip with projection protection structure, effectively can protect and fix interconnection projection,
The intensity of enhancing interconnection projection, the problems such as preventing from causing interconnection projection crack when stress is larger and cause interconnection projection failure.And
And, the utility model using capsulation material carry out underfill, capsulation material can be rapidly flowing into smooth flip-chip and
Connection gap between re-wiring layer, reduces technology difficulty so that the connecting sewing between flip-chip and re-wiring layer
Gap can be smaller.Also, the utility model is more easy to prepare, and is conducive to simplification of flowsheet, reduces cost, improves packaging efficiency,
Improve integrated level and yield rate.So, the utility model effectively overcomes various shortcoming of the prior art and has high industrial
Value.
Above-mentioned embodiment only illustrative principle of the present utility model and its effect are new not for this practicality is limited
Type.Any person skilled in the art can all enter without prejudice under spirit and scope of the present utility model to above-mentioned embodiment
Row modifications and changes.Therefore, such as those of ordinary skill in the art without departing from disclosed in the utility model
Spirit and all equivalent modifications completed under technological thought or change, should be covered by claim of the present utility model.
Claims (9)
1. a kind of fan-out-type wafer level packaging structure, it is characterised in that the fan-out-type wafer level packaging structure at least includes：
Re-wiring layer；
At least one for being bonded to the re-wiring layer upper surface has the flip-chip of projection protection structure and is formed at institute
State at least two first projections of re-wiring layer upper surface, the flip-chip and described first with projection protection structure
Projection is realized with the re-wiring layer and is electrically connected with, and the top of first projection higher than described there is projection to protect knot
The top of the flip-chip of structure；
Be formed at the re-wiring layer upper surface fills the completely described flip-chip with projection protection structure and described heavy
Connection gap between new route layer simultaneously wraps up the one of the flip-chip with projection protection structure and first projection
Partial plastic packaging layer；And
It is formed at the second projection of the re-wiring layer lower surface.
2. fan-out-type wafer level packaging structure according to claim 1, it is characterised in that the re-wiring layer is at least wrapped
Include：
Multiple first pads；
It is covered in the first dielectric layer of the first pad upper surface and side wall；
The metal wiring layer being electrically connected with can be realized with first pad by being formed in first dielectric layer, wherein,
The metal wiring layer is single metal layer or more metal layers；
Be formed at the first dielectric layer upper surface can realize the multiple lower metals being electrically connected with the metal wiring layer
Change layer, finally give the re-wiring layer；
Wherein, the flip-chip with projection protection structure is bonded to the upper surface of the lower metal layer, and passes through institute
State lower metal layer realization and the electric connection of the re-wiring layer.
3. fan-out-type wafer level packaging structure according to claim 2, it is characterised in that described that there is projection protection structure
Flip-chip at least include：
Bare chip；
It is formed at the articulamentum of the bare chip upper surface；And
The interconnection projection on the articulamentum is formed at, and the interconnection projection is realized and the bare chip by the articulamentum
Electric connection；
It is formed at the articulamentum upper surface and surrounds the passivation layer that part interconnects projection, so as to forms projection protection structure；
Wherein, the flip-chip with projection protection structure by it is described interconnection bump bond in the lower metal layer
Upper surface, so as to realize the electric connection with the re-wiring layer.
4. fan-out-type wafer level packaging structure according to claim 3, it is characterised in that the articulamentum at least includes：
It is formed at multiple second pads of the bare chip upper surface；
It is covered in second dielectric layer at the chip upper surface and each second pad two ends；And
It is formed at the insulating barrier of the second dielectric layer upper surface.
5. fan-out-type wafer level packaging structure according to claim 4, it is characterised in that the interconnection projection is formed at often
The upper surface of individual second pad and covering part insulating barrier, and the interconnection projection by second pad realize with it is described naked
The electric connection of chip.
6. fan-out-type wafer level packaging structure according to claim 5, it is characterised in that first projection, described
Two projections and the interconnection projection are respectively by metal column and are formed at the metal that the metal cap of the metal column upper surface is constituted
Combining structure, or first projection, second projection and the interconnection projection are respectively metal welding pellet.
7. fan-out-type wafer level packaging structure according to claim 6, it is characterised in that the metal column uses Cu or Ni
Metal material, the metal cap and the metal welding pellet are respectively adopted in tin, copper, nickel, silver-colored gun-metal or kamash alloy
A kind of material.
8. the fan-out-type wafer level packaging structure according to any one of claim 4~7, it is characterised in that described first is situated between
Electric layer and second dielectric layer use low k dielectric.
9. the fan-out-type wafer level packaging structure according to any one of claim 1~7, it is characterised in that the plastic packaging layer
Using a kind of curing materials in polyimides, silica gel and epoxy resin.
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| CN106684056A (en) * | 2017-03-22 | 2017-05-17 | 中芯长电半导体（江阴）有限公司 | Fan-out type wafer-level packaging structure and preparation method thereof |
| CN106684055A (en) * | 2017-03-22 | 2017-05-17 | 中芯长电半导体（江阴）有限公司 | Fan-out type wafer level encapsulation structure and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106684056A (en) * | 2017-03-22 | 2017-05-17 | 中芯长电半导体（江阴）有限公司 | Fan-out type wafer-level packaging structure and preparation method thereof |
| CN106684055A (en) * | 2017-03-22 | 2017-05-17 | 中芯长电半导体（江阴）有限公司 | Fan-out type wafer level encapsulation structure and preparation method thereof |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |