CN106981467A - Fan-out-type wafer level packaging structure and preparation method thereof - Google Patents

Fan-out-type wafer level packaging structure and preparation method thereof Download PDF

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Publication number
CN106981467A
CN106981467A CN201710338189.9A CN201710338189A CN106981467A CN 106981467 A CN106981467 A CN 106981467A CN 201710338189 A CN201710338189 A CN 201710338189A CN 106981467 A CN106981467 A CN 106981467A
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Prior art keywords
layer
chip
metal
flip
wiring layer
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Inventor
吴政达
林正忠
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SJ Semiconductor Jiangyin Corp
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SJ Semiconductor Jiangyin Corp
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Priority to CN201710338189.9A priority Critical patent/CN106981467A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The present invention provides a kind of fan-out-type wafer level packaging structure and preparation method thereof, and the fan-out-type wafer level packaging structure at least includes：Re-wiring layer；First flip-chip, is bonded to the upper surface of the re-wiring layer；Metal paste conductive pole, is electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；Second flip-chip, is bonded to the upper surface of the metal paste conductive pole；Plastic packaging layer, positioned at the upper surface of the re-wiring layer；Soldered ball projection, positioned at the lower surface of the re-wiring layer.In the fan-out-type wafer level packaging structure of the present invention, metallic conduction post of the prior art is substituted using metal paste conductive pole, metal paste conductive pole can use metal paste typography to be prepared, and preparing metallic conduction post compared to electroplating technology of the prior art has the advantages that cost is low, preparation technology is simple.

Description

Fan-out-type wafer level packaging structure and preparation method thereof
Technical field
The present invention relates to technical field of semiconductor encapsulation, more particularly to a kind of fan-out-type wafer level packaging structure and its system Preparation Method.
Background technology
It is more inexpensive, more reliable, faster and more highdensity circuit be integrated antenna package pursue target.In future, Integrated antenna package will improve the integration density of various electronic components by constantly reducing minimum feature size.At present, first The method for packing entered includes：Wafer chip level chip-scale package (Wafer Level Chip Scale Packaging, WLCSP), fan-out-type wafer-level packaging (Fan-Out Wafer Level Package, FOWLP), flip-chip (Flip Chip), stacked package (Package on Package, POP) etc..
Fan-out-type wafer-level packaging is a kind of embedded chip method for packing of wafer level processing, be current a kind of input/ Output port (I/O) is more, one of the integrated preferable Advanced Packaging method of flexibility.Fan-out-type wafer-level packaging is compared to routine Wafer-level packaging have the advantages that its is unique：1. I/O spacing is flexible, independent of chip size；2. effective nude film is only used (die), product yield is improved；3. there is flexible 3D package paths, you can to form the figure of General Cell at top；4. have There are preferable electrical property and hot property；5. frequency applications；6. easily high-density wiring is realized in re-wiring layer (RDL).
At present, fan-out-type wafer-level packaging method is generally：Carrier is provided, in carrier surface formation adhesive layer；In bonding Photoetching on layer, electroplate out re-wiring layer (Redistribution Layers, RDL)；Using chip bonding/flip-chip work Flip-chip is arranged on re-wiring layer by skill, and metallic conduction post is formed on re-wiring layer using electroplating technology；Adopt With Shooting Technique by flip-chip and metallic conduction post plastic packaging in capsulation material layer；Photoetching, electroplate out metal layer under ball；Enter Row plants ball backflow, forms soldered ball bump array；Remove carrier.However, existing such as in existing fan-out-type wafer level packaging structure Lower problem：1. flip-chip is arranged in individual layer in fan-out-type wafer level packaging structure, routing mode phase is passed through between flip-chip Spacing between connection, the flip-chip being connected is farther out so that the response time is linked up between flip-chip longer；2. metal is led Electric post is formed using electroplating technology, then again together with flip-chip by capsulation material layer plastic packaging；Plating forms metallic conduction post There is the shortcomings of costly, complex process is difficult.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of fan-out-type wafer-level packaging knot Structure and preparation method thereof, for solving fan-out-type wafer level packaging structure of the prior art because flip-chip is arranged in individual layer And exist flip-chip between link up the response time it is longer the problem of, and due to using electroplating technology formation metallic conduction post And exist it is costly, the problem of complex process is difficult.
In order to achieve the above objects and other related objects, the present invention provides a kind of fan-out-type wafer level packaging structure, described Fan-out-type wafer level packaging structure at least includes：
Re-wiring layer；
First flip-chip, is bonded to the upper surface of the re-wiring layer, and electrically connect with the re-wiring layer；
Metal paste conductive pole, is electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；
Second flip-chip, is bonded to the upper surface of the metal paste conductive pole, and positioned at first flip-chip Top, second flip-chip is electrically connected via the metal paste conductive pole with the re-wiring layer；
Plastic packaging layer, positioned at the upper surface of the re-wiring layer, and fills up first flip-chip, the metal paste and leads Gap between electric post, second flip-chip and the re-wiring layer, and by first flip-chip, the metal Cream conductive pole and second flip-chip enveloping plastic packaging；
Soldered ball projection, is electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer.
Preferably, the re-wiring layer at least includes：
First dielectric layer；
Metallic stacked structure, in first dielectric layer, the metallic stacked structure includes what Spaced was arranged Metal line layer and metal plug, the metal plug are located between the adjacent metal line layer, by the adjacent metal wire Layer electrical connection；
Lower metal layer, is electrically connected positioned at the upper surface of first dielectric layer, and with the metal line layer.
Preferably, first flip-chip at least includes：
Bare chip；
Articulamentum, positioned at the upper surface of the bare chip；
Projection is interconnected, on the articulamentum, and the interconnection projection is realized and the naked core by the articulamentum The electric connection of piece；
Wherein, first flip-chip by the interconnection bump bond in the upper surface of the lower metal layer, from And realize the electric connection with the re-wiring layer.
Preferably, the articulamentum at least includes：
Multiple pads, positioned at the upper surface of the bare chip；
Second dielectric layer, is covered in the upper surface of the bare chip and the pad；
Insulating barrier, positioned at the upper surface of second dielectric layer；
Through hole, through the insulating barrier and second dielectric layer, to expose the upper surface of the pad.
Preferably, the interconnection projection is formed at upper surface and the covering part insulating barrier of the pad, and the interconnection Projection realizes the electric connection with the bare chip by the pad.
Preferably, the interconnection projection is by metal column and is formed at the gold that the metal cap of the metal column upper surface is constituted Belong to combining structure, or the interconnection projection is metal welding pellet.
Preferably, the material of the metal column includes Cu or Ni, the material of the metal cap and the metal welding pellet Material includes tin, copper, nickel, silver-colored gun-metal or kamash alloy respectively.
Preferably, first dielectric layer and second dielectric layer use low k dielectric.
Preferably, the material of the plastic packaging layer includes polyimides, silica gel or epoxy resin.
In order to achieve the above objects and other related objects, the preparation method of the fan-out-type wafer level packaging structure is at least wrapped Include following steps：
One carrier is provided, adhesive layer is formed in the upper surface of the carrier；
Re-wiring layer is formed in the upper surface of the adhesive layer；
The first flip-chip, the flip-chip and the re-wiring layer are bonded in the upper surface of the re-wiring layer Realize and be electrically connected with；
The first plastic packaging layer is formed in the upper surface of the re-wiring layer, the first plastic packaging layer fills up first upside-down mounting Gap between chip and the re-wiring layer, and first flip-chip is encapsulated into plastic packaging；
In forming opening in first plastic packaging layer, the opening is described to expose part through first plastic packaging layer Re-wiring layer；
Metal paste conductive pole is formed in the opening using metal paste typography, the metal paste conductive pole with it is described Re-wiring layer is electrically connected；
The second flip-chip is bonded in the upper surface of first plastic packaging layer；Second flip-chip is located at described first The top of flip-chip, and electrically connected via the metal paste conductive pole with the re-wiring layer；
The second plastic packaging layer is formed in the upper surface of first plastic packaging layer, the second plastic packaging layer fills up second upside-down mounting Gap between chip and first plastic packaging layer, and second flip-chip is encapsulated into plastic packaging；
Remove the carrier and the adhesive layer；
In the lower surface formation soldered ball projection of the re-wiring layer.
Preferably, re-wiring layer is formed in the upper surface of the passivation layer to comprise the following steps：
First layer metal line layer is formed in the upper surface of the passivation layer；
The upper surface of metal line layer described in covering first layer is formed in the upper surface of the passivation layer and the first of side wall is situated between Electric layer；
It is adjacent in forming other metal line layers with first layer metal line layer electric connection in first dielectric layer Electrically connected between the metal line layer via metal plug；
Lower metal layer, the lower metal layer and the metal wiring layer are formed in the upper surface of first dielectric layer Electrical connection.
Preferably, first flip-chip at least includes：Bare chip；Articulamentum, positioned at the upper surface of the bare chip； Interconnect projection, on the articulamentum, and the interconnection projection realized by the articulamentum it is electrical with the bare chip Connection；Wherein, first flip-chip by the interconnection bump bond in the upper surface of the lower metal layer so that real Now with the electric connection of the re-wiring layer；Being bonded first flip-chip in the upper surface of the re-wiring layer includes Following steps：
Scaling powder glue-line is formed in the upper surface of the upper surface of the interconnection projection or the lower metal layer；
By the position where lower metal layer described in the top alignment of the interconnection projection, reflow soldering is then carried out, from And make first flip-chip by the interconnection bump bond in the upper surface of the lower metal layer.
Preferably, first plastic packaging is formed in the upper surface of the re-wiring layer using molded underfill technique Layer；The second plastic packaging layer is formed in the upper surface of first plastic packaging layer using molded underfill technique.
Preferably, using laser boring technique in the formation opening in first plastic packaging layer.
As described above, fan-out-type wafer level packaging structure of the present invention and preparation method thereof, has the advantages that：This In the fan-out-type wafer level packaging structure of invention, metallic conduction post of the prior art, metal are substituted using metal paste conductive pole Cream conductive pole can use metal paste typography to be prepared, and preparing metal compared to electroplating technology of the prior art leads Electric post has the advantages that cost is low, preparation technology is simple；Meanwhile, in fan-out-type wafer level packaging structure of the invention, first falls Cartridge chip and the perpendicular storehouse of the second flip-chip are distributed so that between first flip-chip and second flip-chip Spacing reach it is most short, so as to shorten the communication response time of first flip-chip and second flip-chip.
Brief description of the drawings
Fig. 1 is shown as the structural representation of the fan-out-type wafer level packaging structure provided in the embodiment of the present invention one.
Fig. 2 is shown as the first flip-chip in the fan-out-type wafer level packaging structure that is provided in the embodiment of the present invention one Structural representation.
The flow that Fig. 3 is shown as the preparation method of the fan-out-type wafer level packaging structure provided in the embodiment of the present invention two is shown It is intended to.
Each step of fan-out-type wafer-level packaging method that Fig. 4~Figure 13 is shown as providing in the embodiment of the present invention two is presented Structural representation.
Component label instructions
1 re-wiring layer
11 first dielectric layers
12 metallic stacked structures
13 times metal layers
2 first flip-chips
21 bare chips
22 articulamentums
221 pads
222 second dielectric layers
223 insulating barriers
23 interconnection projections
231 metal columns
232 metal caps
3 metal paste conductive poles
4 second flip-chips
5 plastic packagings layer
51 first plastic packagings layer
511 openings
52 second plastic packagings layer
6 soldered ball projections
7 carriers
8 adhesive layers
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from Various modifications or alterations are carried out under the spirit of the present invention.
Fig. 1 is referred to Figure 13.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of invention, though only display is with relevant component in the present invention rather than according to package count during actual implement in diagram Mesh, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its Assembly layout kenel may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present invention provides a kind of fan-out-type wafer level packaging structure, the fan-out-type wafer level packaging structure At least include：Re-wiring layer 1；First flip-chip 2, first flip-chip 2 is bonded to the upper of the re-wiring layer 1 Surface, and electrically connected with the re-wiring layer 1；Metal paste conductive pole 3, the metal paste conductive pole 3 is located at the cloth again The upper surface of line layer 1, and electrically connected with the re-wiring layer 1；Second flip-chip 4, second flip-chip 4 is bonded to The upper surface of the metal paste conductive pole 3, and positioned at first flip-chip 2 top, second flip-chip 2 via The metal paste conductive pole 3 is electrically connected with the re-wiring layer 1；Plastic packaging layer 5, the plastic packaging layer 5 is located at the rewiring The upper surface of layer 1, and fill up first flip-chip 2, the metal paste conductive pole 3, second flip-chip 4 and described Gap between re-wiring layer 1, and by first flip-chip 2, the metal paste conductive pole 3 and the second upside-down mounting core Piece 4 encapsulates plastic packaging；Soldered ball projection 6, the soldered ball projection 6 be located at the re-wiring layer 1 lower surface, and with the cloth again Line layer 1 is electrically connected.In the fan-out-type wafer level packaging structure of the present invention, prior art is substituted using the metal paste conductive pole 3 In metallic conduction post, the metal paste conductive pole 3 can use metal paste typography to be prepared, compared to existing skill Electroplating technology in art, which prepares metallic conduction post, has the advantages that cost is low, preparation technology is simple；Meanwhile, fan-out-type of the invention In wafer level packaging structure, the perpendicular storehouse distribution of 2 and second flip-chip of the first flip-chip 4 so that described first Spacing between flip-chip 2 and second flip-chip 4 reach it is most short so that shorten first flip-chip 2 with The communication response time of second flip-chip 4.
In the fan-out-type wafer level packaging structure of present embodiment, plastic packaging layer 5 fill up first flip-chip 2, Gap between the metal paste conductive pole 3, second flip-chip 4 and the re-wiring layer 1, and described first is fallen Cartridge chip 2, the metal paste conductive pole 3 and second flip-chip 4 enveloping plastic packaging, on the one hand can protect described first to fall Interconnection portion between cartridge chip 2 and second flip-chip 4 and the re-wiring layer 1, is on the other hand described first Connecing there is provided seamless bonding and well between flip-chip 2 and second flip-chip 4 and the re-wiring layer 1 Structure is closed, with good packaging effect, it is to avoid the risk of interface debonding, improve the reliability of encapsulating structure, it is more applicable In highly integrated device encapsulation, it is with a wide range of applications in field of semiconductor package.In addition, forming the plastic packaging layer 5 When, underfill is carried out using capsulation material, capsulation material can be rapidly flowing into first flip-chip 2, institute with smooth The gap between metal paste conductive pole 3, second flip-chip 4 and the re-wiring layer 1 is stated, technology difficulty is reduced, It can be used in smaller connection gap.
As an example, the metal paste conductive pole 3 be located at can as shown in fig. 1, respectively positioned at the first upside-down mounting core The both sides of piece 2, and upper surface of the upper surface greater than or equal to first flip-chip 2 of the metal paste conductive pole 3.It is described Second flip-chip 4 be located at first flip-chip 2 surface, and via with positioned at the both sides of the first flip-chip 2 The metal paste conductive pole 3 electrically connected with the re-wiring layer 1.
As an example, the metal paste conductive pole 3 can be to form opening, then using gold in the plastic packaging layer 5 now Category cream typography prints structure formed by filling metal paste in the opening.Form the gold of the metal paste conductive pole 3 It can be any one conductive metal paste of the prior art to belong to cream.For example, in the present embodiment, the metal paste conductive pole 3 Material can be metal powder granulates or the mixed structure of metal glue material and organic matter, the metal powder granulates or the metal Glue material can be distributed evenly in the organic matter.The organic matter can be but be not limited only to conducting resinl etc..
As an example, the re-wiring layer 1 at least includes：First dielectric layer 11；Metallic stacked structure 12, the metal Laminated construction 12 is located in first dielectric layer 11, and the metallic stacked structure 12 includes the metal line layer that Spaced is arranged And metal plug, the metal plug is located between the adjacent metal line layer, by adjacent metal line layer electrical connection； Lower metal layer 13, the lower metal layer 13 is located at the upper surface of first dielectric layer 11, and electric with the metal line layer Connection.
As an example, the metal line layer can include single metal layer, two layers or more metal layers can also be included.Make For example, the metal line layer and the metal plug can be using a kind of material in copper, aluminium, nickel, gold, silver, titanium or two kinds Combined material above.
As an example, the material of the lower metal layer 13 can be copper, aluminium, nickel, gold, silver, titanium in a kind of material or Two or more combined materials.
As an example, referring to Fig. 2, first flip-chip 2 at least includes：Bare chip 21；Articulamentum 22, the company Connect the upper surface that layer 22 is located at the bare chip 21；Projection 23 is interconnected, the interconnection projection 23 is located on the articulamentum 22, and The interconnection projection 23 realizes the electric connection with the bare chip 21 by the articulamentum 22；Wherein, first upside-down mounting Chip 2 is bonded to the upper surface of the lower metal layer 13 by the interconnection projection 23, so as to realize and the rewiring The electric connection of layer 1.
As an example, the articulamentum 22 at least includes：Multiple pads 221, the pad 221 is located at the bare chip 21 Upper surface；Second dielectric layer 222, second dielectric layer 222 is covered in the upper surface of the bare chip 21 and the pad 221；Insulating barrier 223, the insulating barrier 223 is located at the upper surface of second dielectric layer 222；Through hole, the through hole runs through institute Insulating barrier 223 and second dielectric layer 222 are stated, to expose the upper surface of the pad 221.
As an example, the interconnection projection 23 is formed at upper surface and the covering part insulating barrier 223 of the pad 221, And the interconnection projection 23 realizes the electric connection with the bare chip 21 by the pad 221.
As an example, insulating barrier 223 can be using materials such as silica or PET.
Although it is to be understood that only including two pads 221, two interconnections in structural representation shown in Fig. 2 Projection 23, but Fig. 2 is only the simple schematic diagram drawn for the first flip-chip of specific explanations 2, in fact, present embodiment In first flip-chip 2 can comprising multiple pads 221, it is multiple it is described interconnection projection 23, not with shown in Fig. 2 Structural representation for limitation.
In one example, as shown in Fig. 2 the interconnection projection 23 is by metal column 231 and is formed at the upper table of metal column 231 The metallic combination structure that the metal cap 232 in face is constituted.
As an example, metal column 231 can use Cu or Ni metal materials.Wherein, metal column 231 is preferred to use Cu posts.
As an example, metal cap 232 can be using a kind of material in tin, copper, nickel, silver-colored gun-metal or kamash alloy Material, includes but is not limited to this.
In another example, the interconnection projection 23 can also be metal welding pellet (solder ball).
As an example, metal welding pellet can be using a kind of material in tin, copper, nickel, silver-colored gun-metal or kamash alloy Material, includes but is not limited to this.
As an example, first dielectric layer 11 and second dielectric layer 222 can use low k dielectric.Make For example, the first dielectric layer 11 and the second dielectric layer 222 can use epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorus A kind of material in silica glass and fluorine-containing glass.
As an example, the material of the plastic packaging layer 5 can be polyimides, silica gel or epoxy resin.
Embodiment two
Referring to Fig. 3, the present invention also provides a kind of preparation method of fan-out-type wafer level packaging structure, the fan-out-type is brilliant The preparation method of circle class encapsulation structure is suitable to prepare the fan-out-type wafer level packaging structure as described in embodiment one, described to be fanned out to The preparation method of type wafer level packaging structure at least comprises the following steps：
S1：One carrier is provided, adhesive layer is formed in the upper surface of the carrier；
S2：Re-wiring layer is formed in the upper surface of the adhesive layer；
S3：The first flip-chip, the flip-chip and the cloth again are bonded in the upper surface of the re-wiring layer Line layer, which is realized, to be electrically connected with；
S4：The first plastic packaging layer is formed in the upper surface of the re-wiring layer, the first plastic packaging layer fills up described first Gap between flip-chip and the re-wiring layer, and first flip-chip is encapsulated into plastic packaging；
S5：It is described to be open through first plastic packaging layer to expose part in forming opening in first plastic packaging layer The re-wiring layer；
S6：Metal paste conductive pole is formed in the opening using metal paste typography, the metal paste conductive pole with The re-wiring layer electrical connection；
S7：The second flip-chip is bonded in the upper surface of first plastic packaging layer；Second flip-chip is located at described The top of first flip-chip, and electrically connected via the metal paste conductive pole with the re-wiring layer；
S8：The second plastic packaging layer is formed in the upper surface of first plastic packaging layer, the second plastic packaging layer fills up described second Gap between flip-chip and first plastic packaging layer, and second flip-chip is encapsulated into plastic packaging；
S9：Remove the carrier and the adhesive layer；
S10：In the lower surface formation soldered ball projection of the re-wiring layer.
In step sl, the S1 steps and Fig. 4 in Fig. 3 are referred to there is provided a carrier 7, in the upper surface shape of the carrier 7 Into adhesive layer 8.
As an example, the material of the carrier 7 can be in silicon, glass, silica, ceramics, polymer and metal A kind of material or two or more composites, its shape can for wafer shape, it is square or it is other it is any needed for shape.
As an example, the adhesive layer 8 in subsequent technique as the re-wiring layer 1 being subsequently formed and positioned at institute The separating layer between the other structures on re-wiring layer 1 and the carrier 7 is stated, it is preferably from the bonding with smooth finish surface Material is made, and it must have certain adhesion with re-wiring layer 1, to ensure the re-wiring layer 1 in subsequent technique In situations such as will not produce mobile, in addition, it also has stronger adhesion with the carrier 7, in general, itself and described carry The adhesion of body 7 needs to be more than the adhesion with the re-wiring layer 1.As an example, the material of the adhesive layer 8 is selected from double Face is respectively provided with sticky adhesive tape or the adhesive glue made by spin coating proceeding etc..Adhesive tape is preferred to use UV adhesive tapes, and it is in UV illumination It is easy to pull off after penetrating.In other embodiments, the adhesive layer 8 also can select physical vaporous deposition or chemical gaseous phase The other materials layer of sedimentation formation, such as epoxy resin (Epoxy), silicon rubber (silicone rubber), polyimides (PI), polybenzoxazoles (PBO), benzocyclobutene (BCB) etc..In carrier 7 described in later separation, can using wet etching, The methods such as cmp remove the adhesive layer 8.
In step s 2, S2 steps and Fig. 5 in Fig. 3 are referred to, in the upper surface of the adhesive layer 8 formation again cloth Line layer 1.
Comprise the following steps as an example, forming re-wiring layer 1 in the upper surface of the adhesive layer 8：
S21：First layer metal line layer is formed in the upper surface of the adhesive layer 8；
S22：The of the upper surface of metal line layer described in covering first layer and side wall is formed in the upper surface of the adhesive layer 8 One dielectric layer 11；
S23：In other metal wires formed in first dielectric layer 11 and first layer metal line layer is electrically connected with Electrically connected between layer, the adjacent metal line layer via metal plug；Each layer metal line layer and the metal plug are common Constitute metallic stacked structure 12；
S24：Form lower metal layer 13 in the upper surface of first dielectric layer 11, the lower metal layer 13 with it is described Metal wiring layer is electrically connected.
As an example, the metal line layer can include single metal layer, two layers or more metal layers can also be included.Make For example, the metal line layer and the metal plug can be using a kind of material in copper, aluminium, nickel, gold, silver, titanium or two kinds Combined material above.
As an example, the material of first dielectric layer 11 can be low k dielectric.As an example, described first is situated between Electric layer 11 can use a kind of material in epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass, And first dielectric layer 11 can be formed using techniques such as spin coating, CVD, plasma enhanced CVDs.
As an example, the material of the lower metal layer 13 can be copper, aluminium, nickel, gold, silver, titanium in a kind of material or Two or more combined materials.
In step s3, S3 steps and Fig. 6 in Fig. 3 are referred to, first is bonded in the upper surface of the re-wiring layer 1 Flip-chip 2, the flip-chip 2 is realized with the re-wiring layer 1 and is electrically connected with.
As an example, please continue to refer to Fig. 2 in embodiment one, first flip-chip 2 at least includes：Bare chip 21；Articulamentum 22, the articulamentum 22 is located at the upper surface of the bare chip 21；Interconnect projection 23, the interconnection projection 23 In on the articulamentum 22, and the interconnection projection 23 is realized by the articulamentum 22 and connected with the electrical of the bare chip 21 Connect；Wherein, first flip-chip 2 is bonded to the upper surface of the lower metal layer 13 by the interconnection projection 23, from And realize the electric connection with the re-wiring layer 1；The first upside-down mounting core is bonded in the upper surface of the re-wiring layer 1 Piece 2 comprises the following steps：
Scaling powder glue-line is formed in the upper surface of the upper surface of the interconnection projection 23 or the lower metal layer 13；
By top (i.e. described surface of the interconnection projection 23 away from the articulamentum 22) alignment institute of the interconnection projection 23 The position where lower metal layer 13 is stated, reflow soldering is then carried out, so that first flip-chip 2 passes through the interconnection Projection 23 is bonded to the upper surface of the lower metal layer 13.The structure of formation is as shown in Figure 6.
It is to be understood that the scaling powder glue-line can remove the interconnection projection 23 and the table of lower metal layer 13 Oxide layer on face, improves the wetting effect of solder flux and the reliability of engagement.The scaling powder glue-line can using dipping or The modes such as spraying are formed, should be as thin as possible and uniform.
As an example, the articulamentum 22 at least includes：Multiple pads 221, the pad 221 is located at the bare chip 21 Upper surface；Second dielectric layer 222, second dielectric layer 222 is covered in the upper surface of the bare chip 21 and the pad 221；Insulating barrier 223, the insulating barrier 223 is located at the upper surface of second dielectric layer 222；Through hole, the through hole runs through institute Insulating barrier 223 and second dielectric layer 222 are stated, to expose the upper surface of the pad 221.
In one example, as shown in Fig. 2 in embodiment one, the interconnection projection 23 is by metal column 231 and is formed at gold Belong to the metallic combination structure that the metal cap 232 of the upper surface of post 231 is constituted.
As an example, metal column 231 can use Cu or Ni metal materials.Wherein, metal column 231 is preferred to use Cu posts.
As an example, metal cap 232 can be using a kind of material in tin, copper, nickel, silver-colored gun-metal or kamash alloy Material, includes but is not limited to this.
In another example, the interconnection projection 23 can also be metal welding pellet (solder ball).
As an example, metal welding pellet can be using a kind of material in tin, copper, nickel, silver-colored gun-metal or kamash alloy Material, includes but is not limited to this.
It should be noted that first flip-chip 2 can include a variety of circuit structures, in the present embodiment, can be with First flip-chip 2 of multiple same types is bonded, multiple different types of first flip-chips can also be bonded 2, it can be selected as needed.
In step s 4, S4 steps and Fig. 7 in Fig. 3 are referred to, first is formed in the upper surface of the re-wiring layer 1 Plastic packaging layer 51, the gap that the first plastic packaging layer 51 is filled up between first flip-chip 2 and the re-wiring layer 1, and First flip-chip 2 is encapsulated into plastic packaging.
As an example, forming first modeling in the upper surface of the re-wiring layer 1 using molded underfill technique Sealing 51.The first plastic packaging layer 51, plastic packaging are formed in the upper surface of the re-wiring layer 1 using molded underfill technique The gap that material can be filled up promptly between first flip-chip 2 and the re-wiring layer 1 with smooth, can be effective Avoid interface debonding occurring；And molded underfill will not be limited as capillary underfill technique of the prior art System, greatly reduces technology difficulty, can be used for smaller joint gap, be more suitable for stacked architecture.
In step s 5, S5 steps and Fig. 8 in Fig. 3 are referred to, in formation opening 511 in first plastic packaging layer 51, The opening 511 runs through first plastic packaging layer 51 to expose the part re-wiring layer 1.
As an example, can be using laser boring technique in the formation opening 511 in first plastic packaging layer 51.
As an example, the opening 511 is used to be subsequently formed the metal paste conductive pole 3, the opening 511 is located at can be with As shown in Figure 8, respectively positioned at the both sides of first flip-chip 2.
In step s 6, S6 steps and Fig. 9 in Fig. 3 are referred to, using metal paste typography in the opening 511 Metal paste conductive pole 3 is formed, the metal paste conductive pole 3 is electrically connected with the re-wiring layer 1.
It is dispersed in as an example, the metal paste can be metal powder granulates or metal glue-line in organic matter, this When the metal paste be grume, by typography first capsulation material layer 51 surface repeatedly stencil the metal Cream so that the metal paste fills up the opening 511.
It should be noted that the metal paste can be solid using rapid solidification under certain process conditions or under field conditions (factors) State.
The present invention prepares the metal paste conductive pole 3 using metal paste typography, compared to plating of the prior art Technique, which prepares metallic conduction post, has the advantages that cost is low, preparation technology is simple.
In the step s 7, S7 steps and Figure 10 in Fig. 3 are referred to, in the upper surface bonding the of first plastic packaging layer 51 Two flip-chips 4；Second flip-chip 4 is located at the top of first flip-chip 2, and conductive via the metal paste Post 3 is electrically connected with the re-wiring layer 1.
As shown in Figure 10, second flip-chip 4 is distributed with the perpendicular storehouse of first flip-chip 2 so that institute State the spacing between the first flip-chip 2 and second flip-chip 4 reach it is most short, so as to shorten the first upside-down mounting core The communication response time of piece 2 and second flip-chip 4.
In step s 8, S8 steps and Figure 11 in Fig. 3 are referred to, the is formed in the upper surface of first plastic packaging layer 51 Two plastic packagings layer 52, the gap that the second plastic packaging layer 52 is filled up between second flip-chip 4 and first plastic packaging layer 51, And second flip-chip 4 is encapsulated into plastic packaging.
As an example, forming second modeling in the upper surface of first plastic packaging layer 51 using molded underfill technique Sealing 52.The second plastic packaging layer 52, modeling are formed in the upper surface of first plastic packaging layer 51 using molded underfill technique The gap that closure material can be promptly filled up with smooth between second flip-chip 4 and first plastic packaging layer 51, can be with It is prevented effectively from and interface debonding is occurring；And molded underfill will not as capillary underfill technique of the prior art by To limitation, technology difficulty is greatly reduced, can be used for smaller joint gap, be more suitable for stacked architecture.
It should be noted that in the present embodiment first plastic packaging layer 51 and second plastic packaging layer 52 both be superimposed Come as the plastic packaging layer 5 described in embodiment one.Because the material of first plastic packaging layer 51 and second plastic packaging layer 52 is complete Exactly the same, after the second plastic packaging layer 52 is formed, the first plastic packaging layer 51 is overall with second plastic packaging layer 52 to be One layer of plastic packaging layer, i.e., the plastic packaging layer 5 described in embodiment one.
In step s 9, S9 steps and Figure 12 in Fig. 3 are referred to, the carrier 7 and the adhesive layer 8 is removed.
As an example, the carrier 7 and the adhesive layer 8 can be removed using grinding technics, reduction process etc..It is excellent In selection of land, the present embodiment, use and tear the mode of the adhesive layer 8 to remove the carrier 7.
In step slo, S10 steps and Figure 13 in Fig. 3 are referred to, is formed in the lower surface of the re-wiring layer 1 Soldered ball projection 6.
The technique of the soldered ball projection 6 is formed known to those skilled in the art, is not repeated herein.
In summary, the present invention provides a kind of fan-out-type wafer level packaging structure and preparation method thereof, and the fan-out-type is brilliant Circle class encapsulation structure at least includes：Re-wiring layer；First flip-chip, is bonded to the upper surface of the re-wiring layer, and Electrically connected with the re-wiring layer；Metal paste conductive pole, positioned at the upper surface of the re-wiring layer, and with the cloth again Line layer electrical connection；Second flip-chip, is bonded to the upper surface of the metal paste conductive pole, and positioned at first flip-chip Top, second flip-chip electrically connects via the metal paste conductive pole with the re-wiring layer；Plastic packaging layer, is located at The upper surface of the re-wiring layer, and fill up first flip-chip, the metal paste conductive pole, the second upside-down mounting core Gap between piece and the re-wiring layer, and by first flip-chip, the metal paste conductive pole and described second Flip-chip encapsulates plastic packaging；Soldered ball projection, is electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer Connect.In the fan-out-type wafer level packaging structure of the present invention, metallic conduction post of the prior art is substituted using metal paste conductive pole, Metal paste conductive pole can use metal paste typography to be prepared, and gold is prepared compared to electroplating technology of the prior art Category conductive pole has the advantages that cost is low, preparation technology is simple；Meanwhile, in fan-out-type wafer level packaging structure of the invention, the One flip-chip and the perpendicular storehouse of the second flip-chip are distributed so that first flip-chip and second flip-chip Between spacing reach it is most short so that when the communication for shortening first flip-chip and second flip-chip is responded Between.
The principle and its effect of the above-mentioned embodiment only illustrative present invention, not for the limitation present invention.It is any Those skilled in the art can all be modified or changed to above-mentioned embodiment under the spirit and scope without prejudice to the present invention Become.Therefore, such as those of ordinary skill in the art without departing from disclosed spirit and technological thought Lower all completed equivalent modifications or change, should be covered by the claim of the present invention.

Claims (14)

1. a kind of fan-out-type wafer level packaging structure, it is characterised in that the fan-out-type wafer level packaging structure at least includes：
Re-wiring layer；
First flip-chip, is bonded to the upper surface of the re-wiring layer, and electrically connect with the re-wiring layer；
Metal paste conductive pole, is electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；
Second flip-chip, is bonded to the upper surface of the metal paste conductive pole, and positioned at the top of first flip-chip, Second flip-chip is electrically connected via the metal paste conductive pole with the re-wiring layer；
Plastic packaging layer, positioned at the upper surface of the re-wiring layer, and it is conductive to fill up first flip-chip, the metal paste Gap between post, second flip-chip and the re-wiring layer, and by first flip-chip, the metal paste Conductive pole and second flip-chip enveloping plastic packaging；
Soldered ball projection, is electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer.
2. fan-out-type wafer level packaging structure according to claim 1, it is characterised in that：The re-wiring layer is at least wrapped Include：
First dielectric layer；
Metallic stacked structure, in first dielectric layer, the metallic stacked structure includes the metal that Spaced is arranged Line layer and metal plug, the metal plug are located between the adjacent metal line layer, by adjacent metal line layer electricity Connection；
Lower metal layer, is electrically connected positioned at the upper surface of first dielectric layer, and with the metal line layer.
3. fan-out-type wafer level packaging structure according to claim 2, it is characterised in that：First flip-chip is at least Including：
Bare chip；
Articulamentum, positioned at the upper surface of the bare chip；
Projection is interconnected, on the articulamentum, and the interconnection projection is realized and the bare chip by the articulamentum It is electrically connected with；
Wherein, first flip-chip by the interconnection bump bond in the upper surface of the lower metal layer so that real Now with the electric connection of the re-wiring layer.
4. fan-out-type wafer level packaging structure according to claim 3, it is characterised in that：The articulamentum at least includes：
Multiple pads, positioned at the upper surface of the bare chip；
Second dielectric layer, is covered in the upper surface of the bare chip and the pad；
Insulating barrier, positioned at the upper surface of second dielectric layer；
Through hole, through the insulating barrier and second dielectric layer, to expose the upper surface of the pad.
5. fan-out-type wafer level packaging structure according to claim 4, it is characterised in that：The interconnection projection is formed at institute Upper surface and the covering part insulating barrier of pad are stated, and the interconnection projection realizes the electricity with the bare chip by the pad Property connection.
6. fan-out-type wafer level packaging structure according to claim 5, it is characterised in that：The interconnection projection is by metal Post and be formed at the metal column upper surface metal cap composition metallic combination structure, or it is described interconnection projection be metal welding Pellet.
7. fan-out-type wafer level packaging structure according to claim 6, it is characterised in that：The material of the metal column includes The material of Cu or Ni, the material of the metal cap and the metal welding pellet includes tin, copper, nickel, silver-colored gun-metal or tin respectively Based alloy.
8. the fan-out-type wafer level packaging structure according to any one of claim 4~7, it is characterised in that：Described first is situated between Electric layer and second dielectric layer use low k dielectric.
9. the fan-out-type wafer level packaging structure according to any one of claim 1~7, it is characterised in that：The plastic packaging layer Material include polyimides, silica gel or epoxy resin.
10. a kind of preparation method of fan-out-type wafer level packaging structure, it is characterised in that the fan-out-type wafer level packaging structure Preparation method at least comprise the following steps：
One carrier is provided, adhesive layer is formed in the upper surface of the carrier；
Re-wiring layer is formed in the upper surface of the adhesive layer；
The first flip-chip is bonded in the upper surface of the re-wiring layer, the flip-chip is realized with the re-wiring layer It is electrically connected with；
The first plastic packaging layer is formed in the upper surface of the re-wiring layer, the first plastic packaging layer fills up first flip-chip And the gap between the re-wiring layer, and first flip-chip is encapsulated into plastic packaging；
It is described to be open through first plastic packaging layer to expose described in part again in forming opening in first plastic packaging layer Wiring layer；
Metal paste conductive pole is formed in the opening using metal paste typography, the metal paste conductive pole with it is described again Wiring layer is electrically connected；
The second flip-chip is bonded in the upper surface of first plastic packaging layer；Second flip-chip is located at first upside-down mounting The top of chip, and electrically connected via the metal paste conductive pole with the re-wiring layer；
The second plastic packaging layer is formed in the upper surface of first plastic packaging layer, the second plastic packaging layer fills up second flip-chip With first plastic packaging layer between gap, and will second flip-chip enveloping plastic packaging；
Remove the carrier and the adhesive layer；
In the lower surface formation soldered ball projection of the re-wiring layer.
11. the preparation method of fan-out-type wafer level packaging structure according to claim 10, it is characterised in that：In described blunt The upper surface formation re-wiring layer for changing layer comprises the following steps：
First layer metal line layer is formed in the upper surface of the passivation layer；
The upper surface of metal line layer and the first dielectric layer of side wall described in covering first layer are formed in the upper surface of the passivation layer；
It is adjacent described in forming other metal line layers with first layer metal line layer electric connection in first dielectric layer Electrically connected between metal line layer via metal plug；
Lower metal layer is formed in the upper surface of first dielectric layer, the lower metal layer is electrically connected with the metal wiring layer Connect.
12. the preparation method of fan-out-type wafer level packaging structure according to claim 11, it is characterised in that：Described first Flip-chip at least includes：Bare chip；Articulamentum, positioned at the upper surface of the bare chip；Projection is interconnected, positioned at the articulamentum On, and the interconnection projection realizes the electric connection with the bare chip by the articulamentum；Wherein, the first upside-down mounting core Piece by it is described interconnection bump bond in the upper surface of the lower metal layer, so as to realize electrical with the re-wiring layer Connection；First flip-chip is bonded in the upper surface of the re-wiring layer to comprise the following steps：
Scaling powder glue-line is formed in the upper surface of the upper surface of the interconnection projection or the lower metal layer；
By the position where lower metal layer described in the top alignment of the interconnection projection, reflow soldering is then carried out, so that First flip-chip is by the interconnection bump bond in the upper surface of the lower metal layer.
13. the preparation method of fan-out-type wafer level packaging structure according to claim 10, it is characterised in that：Using molding Underfill process forms the first plastic packaging layer in the upper surface of the re-wiring layer；Using molded underfill technique in The upper surface of the first plastic packaging layer forms the second plastic packaging layer.
14. the preparation method of fan-out-type wafer level packaging structure according to claim 10, it is characterised in that：Using laser Drilling technology is in the formation opening in first plastic packaging layer.
CN201710338189.9A 2017-05-15 2017-05-15 Fan-out-type wafer level packaging structure and preparation method thereof Pending CN106981467A (en)

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* Cited by examiner, † Cited by third party
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CN107768353A (en) * 2017-10-17 2018-03-06 华天科技（昆山）电子有限公司 Stack package structure and preparation method thereof
CN109560091A (en) * 2017-09-27 2019-04-02 中芯长电半导体（江阴）有限公司 A kind of encapsulating structure and packaging method
CN109659282A (en) * 2017-10-11 2019-04-19 中芯长电半导体（江阴）有限公司 A kind of encapsulating structure and packaging method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130010446A1 (en) * 2009-11-10 2013-01-10 Infineon Technologies Ag Laminate electronic device
CN103000593A (en) * 2011-09-09 2013-03-27 台湾积体电路制造股份有限公司 Packaging methods and structures for semiconductor devices
CN105225965A (en) * 2015-11-03 2016-01-06 中芯长电半导体（江阴）有限公司 A kind of fan-out package structure and preparation method thereof
US20160155723A1 (en) * 2014-11-27 2016-06-02 Chengwei Wu Semiconductor package
CN206758428U (en) * 2017-05-15 2017-12-15 中芯长电半导体（江阴）有限公司 Fan-out-type wafer level packaging structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130010446A1 (en) * 2009-11-10 2013-01-10 Infineon Technologies Ag Laminate electronic device
CN103000593A (en) * 2011-09-09 2013-03-27 台湾积体电路制造股份有限公司 Packaging methods and structures for semiconductor devices
US20160155723A1 (en) * 2014-11-27 2016-06-02 Chengwei Wu Semiconductor package
CN105225965A (en) * 2015-11-03 2016-01-06 中芯长电半导体（江阴）有限公司 A kind of fan-out package structure and preparation method thereof
CN206758428U (en) * 2017-05-15 2017-12-15 中芯长电半导体（江阴）有限公司 Fan-out-type wafer level packaging structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109560091A (en) * 2017-09-27 2019-04-02 中芯长电半导体（江阴）有限公司 A kind of encapsulating structure and packaging method
CN109659282A (en) * 2017-10-11 2019-04-19 中芯长电半导体（江阴）有限公司 A kind of encapsulating structure and packaging method
CN107768353A (en) * 2017-10-17 2018-03-06 华天科技（昆山）电子有限公司 Stack package structure and preparation method thereof

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