CN107104090A - Re-wiring layer, the encapsulating structure with the re-wiring layer and preparation method - Google Patents

Re-wiring layer, the encapsulating structure with the re-wiring layer and preparation method Download PDF

Info

Publication number
CN107104090A
CN107104090A CN201710338191.6A CN201710338191A CN107104090A CN 107104090 A CN107104090 A CN 107104090A CN 201710338191 A CN201710338191 A CN 201710338191A CN 107104090 A CN107104090 A CN 107104090A
Authority
CN
China
Prior art keywords
layer
metal
wiring layer
wiring
metal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710338191.6A
Other languages
Chinese (zh)
Other versions
CN107104090B (en
Inventor
吴政达
林正忠
蔡奇风
林章申
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SJ Semiconductor Jiangyin Corp
Original Assignee
SJ Semiconductor Jiangyin Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SJ Semiconductor Jiangyin Corp filed Critical SJ Semiconductor Jiangyin Corp
Priority to CN201710338191.6A priority Critical patent/CN107104090B/en
Publication of CN107104090A publication Critical patent/CN107104090A/en
Application granted granted Critical
Publication of CN107104090B publication Critical patent/CN107104090B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/49527Additional leads the additional leads being a multilayer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The present invention provides a kind of re-wiring layer, the encapsulating structure with the re-wiring layer and preparation method, and the re-wiring layer at least includes:Dielectric layer;Metallic stacked structure, in the dielectric layer, the metallic stacked structure includes the metal line layer and metal plug that Spaced is arranged, and the metal plug is located between the adjacent metal line layer, and the adjacent metal line layer is electrically connected;Metal seed layer, in the dielectric layer, and on a surface of the metallic stacked structure, the material of the metal seed layer is identical with the material of the metal line layer.The re-wiring layer of the present invention is used with its material identical homogenous material as Seed Layer, and the line width and line spacing that metal wire in lateral incision phenomenon, the re-wiring layer is not present when being performed etching to Seed Layer are smaller;When the re-wiring layer is applied in encapsulating structure, more power supply rails can be obtained in identical size.

Description

Re-wiring layer, the encapsulating structure with the re-wiring layer and preparation method
Technical field
The present invention relates to technical field of semiconductor encapsulation, more particularly to a kind of re-wiring layer, with the cloth again The encapsulating structure and preparation method of line layer.
Background technology
All calculating and communication system are required for power transmission system.Power transmission system can turn the high voltage of power supply Change many different low-voltages needed for discrete devices in system into.The efficiency of power transmission system determines the electricity changed downwards Power is lost, and power supply rail number determines the quantity of supported discrete voltage supply or device.
Current power supply technique is faced with following challenge:
First, with the contraction of process interior joint, the reduction of equipment voltage, the efficiency of power Transmission can be decreased, and make work( Rate consumption is bigger.
2nd, adding more power supply rails needs to replicate more Power Supply Assemblies, such as increase number of elements, increasing circuit plate Size, the number of plies for increasing circuit board, increasing system bulk, cost and weight.
3rd, because the line-spacing of re-wiring layer, the limitation of line width are, it is necessary to increase package dimension.
, it is necessary to multilayer re-wiring layer (RDL) goods high density for high I/O (input/output) chip-packaging structure Intermediate plate.However, under limited outer shape and package dimension, the line width of metal wire and line spacing are got in re-wiring layer It is small to mean that more power supply rails are obtained.In existing process, typically all use Ti/Cu Seed Layers as formed again The Seed Layer of wiring layer, but because Ti etch rate of the etch rate than Cu is many slowly, carried out to the Ti/Cu Seed Layers There can be lateral incision phenomenon during etching, so that line width and line spacing very small re-wiring layer are hardly resulted in, and then very Seldom arrive more power supply rail.
The content of the invention
Prior art in view of the above, it is an object of the invention to provide a kind of re-wiring layer, with it is described again The encapsulating structure and preparation method of wiring layer, for solving in the prior art due to using Ti/Cu Seed Layers as rewiring The Seed Layer of layer and exist hardly result in line width and line spacing very small re-wiring layer, and then hardly result in more confession The problem of electric rail.
In order to achieve the above objects and other related objects, the present invention provides a kind of re-wiring layer, the re-wiring layer At least include:
Dielectric layer;
Metallic stacked structure, in the dielectric layer, the metallic stacked structure includes the metal that Spaced is arranged Line layer and metal plug, the metal plug are located between the adjacent metal line layer, by adjacent metal line layer electricity Connection;
Metal seed layer, in the dielectric layer, and on a surface of the metallic stacked structure, the metal The material of Seed Layer is identical with the material of the metal line layer.
Alternatively, many metal lines are included in each layer metal line layer, the line width of the metal wire is less than 2 μm, phase The adjacent metal wire is smaller than 0.4 μm.
Alternatively, surface of the metal seed layer away from the metallic stacked structure is equal with the surface of the dielectric layer Together, surface of the metallic stacked structure away from the metal seed layer and the surface flush of the dielectric layer.
Alternatively, the material of the material of the metal line layer and the metal seed layer is copper.
The present invention also provides a kind of preparation method of re-wiring layer, and the preparation method of the re-wiring layer at least includes Following steps:
One carrier is provided;
Adhesive layer is formed in the upper surface of the carrier;
The re-wiring layer as described in above-mentioned either a program is formed in the upper surface of the adhesive layer;
Remove the adhesive layer and the carrier.
Alternatively, described re-wiring layer is formed in the upper surface of the adhesive layer to comprise the following steps:
Metal seed layer is formed in the upper surface of the adhesive layer;
First layer metal line layer is formed with the upper surface of the metal seed layer;
According to the first layer metal line layer etching metal seed layer, to remove the first layer metal line layer periphery The metal seed layer;
Formed in the upper surface of the adhesive layer and cover the metal seed layer and first layer metal line layer upper surface With the dielectric layer of side wall;
It is adjacent described in forming other metal line layers with first layer metal line layer electric connection in the dielectric layer Electrically connected between metal line layer via metal plug.
The present invention also provides a kind of encapsulating structure, and the encapsulating structure at least includes:
Re-wiring layer as described in above-mentioned either a program;The re-wiring layer includes relative first surface and the Two surfaces, wherein, the re-wiring layer is first surface with the surface that the metal seed layer closes on;
Active module embedded therein, is electrically connected positioned at the second surface of the re-wiring layer, and with the metal line layer;
Passive module, is electrically connected positioned at the second surface of the re-wiring layer, and with the metal line layer;
Metal connecting pole, is electrically connected positioned at the second surface of the re-wiring layer, and with the metal line layer;
First plastic packaging layer, positioned at the second surface of the re-wiring layer, and fills up the active module embedded therein, the passive mould Gap between block and the metal connecting pole;
Solder projection, positioned at surface of first plastic packaging layer away from the re-wiring layer, and is connected with the metal Post is electrically connected;
With electrical chip, positioned at the first surface of the re-wiring layer, and via the metal seed layer and the metal Line layer electrical connection.
Alternatively, the encapsulating structure also includes the second plastic packaging layer, second plastic packaging layer be located at the use electrical chip with Between the re-wiring layer, and the gap filled up between the use electrical chip and the re-wiring layer.
Alternatively, the active device includes controller and step-down transformer;The passive module include electric capacity, inductance and Resistance.
Alternatively, the second surface of the re-wiring layer again be additionally provided with Underbump metallization layer, the active module embedded therein and The passive module is electrically connected via Underbump metallization layer with the metal line layer.
The present invention also provides a kind of preparation method of encapsulating structure, and the preparation method of the encapsulating structure is at least including as follows Step:
One carrier is provided;
Adhesive layer is formed in the upper surface of the carrier;
The re-wiring layer as described in above-mentioned either a program is formed in the upper surface of the adhesive layer;The rewiring Layer includes relative first surface and second surface, and the first surface of the re-wiring layer is in contact with the adhesive layer;
In second surface bonding active module embedded therein, passive module and the metal connecting pole of the re-wiring layer;It is described active Module, the passive module and the metal connecting pole are electrically connected with the metal line layer;
In second surface formation the first plastic packaging layer of the re-wiring layer, the first plastic packaging layer fills up the active mould Gap between block, the passive module and the metal connecting pole;
Solder projection, the solder projection and the gold are formed in surface of first plastic packaging layer away from re-wiring layer Belong to connecting pole electrical connection;
Remove the adhesive layer and the carrier;
In the first surface bonding electrical chip of the re-wiring layer, the use electrical chip is via the metal seed layer Electrically connected with the metal line layer.
Alternatively, described re-wiring layer is formed in the upper surface of the adhesive layer to comprise the following steps:
Metal seed layer is formed in the upper surface of the adhesive layer;
First layer metal line layer is formed with the upper surface of the metal seed layer;
According to the first layer metal line layer etching metal seed layer, to remove the first layer metal line layer periphery The metal seed layer;
Formed in the upper surface of the adhesive layer and cover the metal seed layer and first layer metal line layer upper surface With the dielectric layer of side wall;
It is adjacent described in forming other metal line layers with first layer metal line layer electric connection in the dielectric layer Electrically connected between metal line layer via metal plug.
Alternatively, first plastic packaging is formed in the second surface of the re-wiring layer using molded underfill technique Layer.
Alternatively, in the re-wiring layer second surface bonding active module embedded therein, passive module and metal connecting pole it Before, the step of being also included in the second surface formation Underbump metallization layer of the re-wiring layer;The active module embedded therein and described Passive module is electrically connected via Underbump metallization layer with the metal line layer.
Alternatively, after the first surface bonding electrical chip of the re-wiring layer, also it is included in and described uses battery core The step of the second plastic packaging layer is formed between piece and the re-wiring layer, the second plastic packaging layer fills up the use electrical chip and institute State the gap between re-wiring layer.
As described above, re-wiring layer, the encapsulating structure with the re-wiring layer and the preparation method of the present invention, tool There is following beneficial effect:
The re-wiring layer of the present invention is used with its material identical homogenous material as Seed Layer, is carried out to Seed Layer The line width and line spacing that metal wire in lateral incision phenomenon, the re-wiring layer is not present during etching are smaller.
Re-wiring layer line width and line spacing in the encapsulating structure of the present invention can be very small, can in identical size To obtain more power supply rails.
In the preparation method of the encapsulating structure of the present invention, using molded underfill technique in the of the re-wiring layer Two surfaces form the first plastic packaging layer, and capsulation material can promptly fill up the active module embedded therein, the passive mould with smooth Gap between block and the metal connecting pole, it is possible to prevente effectively from there is interface debonding;And molded underfill will not picture Capillary underfill technique of the prior art is restricted like that, greatly reduces technology difficulty, can be used for smaller company Gap is connect, stacked architecture is more suitable for.
Brief description of the drawings
Fig. 1 is shown as the structural representation of the re-wiring layer provided in the embodiment of the present invention one.
Fig. 2 is shown as the flow chart of the preparation method of the re-wiring layer provided in the embodiment of the present invention two.
Fig. 3 to Fig. 6 is shown as the knot of each step in the preparation method of the re-wiring layer provided in the embodiment of the present invention two Structure schematic diagram.
Fig. 7 is shown as the structural representation of the encapsulating structure provided in the embodiment of the present invention three.
Fig. 8 is shown as the flow chart of the preparation method of the encapsulating structure provided in the embodiment of the present invention four.
Fig. 9 to Figure 19 is shown as the structure of each step in the preparation method of the encapsulating structure provided in the embodiment of the present invention four Schematic diagram.
Component label instructions
1 re-wiring layer
11 dielectric layers
12 metal line layers
13 metal plugs
14 metal seed layers
2 carriers
3 adhesive layers
41 active module embedded thereins
42 passive modules
5 metal connecting line posts
6 first plastic packagings layer
7 solder projections
8 use electrical chip
81 second plastic packagings layer
9 Underbump metallizations layer
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from Various modifications or alterations are carried out under the spirit of the present invention.
Fig. 1 is referred to Figure 19.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of invention, though only display is with relevant component in the present invention rather than according to package count during actual implement in diagram Mesh, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its Assembly layout kenel may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present invention provides a kind of re-wiring layer 1, the re-wiring layer 1 at least includes:Dielectric layer 11; Metallic stacked structure, the metallic stacked structure is located in the dielectric layer 11, and the metallic stacked structure includes Spaced The metal line layer 12 and metal plug 13 of arrangement, the metal plug 13 are located between the adjacent metal line layer 12, by phase The adjacent metal line layer 12 is electrically connected;Metal seed layer 14, the metal seed layer is located in the dielectric layer 11, and is located at On one surface of the metallic stacked structure, the material of the metal seed layer 14 is identical with the material of the metal line layer 12, I.e. described metal seed layer 14 is homogenous material structure.
As an example, including many metal lines in each layer metal line layer 12, the line width of the metal wire is less than 2 μ M, the adjacent metal wire is smaller than 0.4 μm.
As an example, surface of the metal seed layer 14 away from the metallic stacked structure and the table of the dielectric layer 11 Face flush, surface of the metallic stacked structure away from the metal seed layer 14 is equal with the surface of the dielectric layer 11 Together.
As an example, the material of the metal line layer 12, the material of the metal plug 13 and the metal seed layer 14 Material can be but be not limited only to copper.
The re-wiring layer 1 of the present invention is made using the metal seed layer 14 with its material identical homogenous material For Seed Layer, metal in lateral incision phenomenon, the re-wiring layer 14 is not present when being performed etching to the metal seed layer 14 The line width and line spacing of line can reach it is very small, for example, in the present embodiment, metal wire in the re-wiring layer 14 Line width is less than 2 μm, and the adjacent metal wire is smaller than 0.4 μm.
Embodiment two
Referring to Fig. 2, the present invention also provides a kind of preparation method of re-wiring layer, the preparation side of the re-wiring layer Method at least comprises the following steps:
S1:One carrier is provided;
S2:Adhesive layer is formed in the upper surface of the carrier;
S3:The re-wiring layer as described in above-mentioned either a program is formed in the upper surface of the adhesive layer;
S4:Remove the adhesive layer and the carrier.
In step sl, there is provided a carrier 2 for the S1 steps and Fig. 3 for referring in Fig. 2.
As an example, the material of the carrier 2 can be in glass, stainless steel, silicon, silica, metal or ceramics One or more, or other analogs.The carrier 2 can be plate.For example, the carrier 2 can be but be not limited only to With the circular flat board of certain thickness glass.
In step s 2, S2 steps and Fig. 4 in Fig. 2 are referred to, adhesive layer 3 is formed in the upper surface of the carrier 2.
As an example, the adhesive layer 3 in subsequent technique as the separating layer between re-wiring layer 1 and carrier 2, its Preferably it is made from the jointing material with smooth finish surface, it there must be certain adhesion with re-wiring layer 1, to ensure Situations such as re-wiring layer 1 will not produce mobile in subsequent technique, in addition, its also have with the carrier 2 it is stronger Adhesion, in general, the adhesion of itself and the carrier 2 need to be more than the adhesion with the re-wiring layer 1.As showing Example, the material of the adhesive layer 3 is selected from the two-sided adhesive tape for being respectively provided with viscosity or the adhesive glue made by spin coating proceeding etc..It is described Adhesive tape is preferred to use UV adhesive tapes, and it is easy to pull off after UV light irradiations.In other embodiments, the adhesive layer 3 It can select the other materials layer that physical vaporous deposition or chemical vapour deposition technique refer to, such as epoxy resin (Epoxy), silicon rubber (silicone rubber), polyimides (PI), polybenzoxazoles (PBO), benzocyclobutene (BCB) etc..In later separation institute When stating carrier 2, the adhesive layer 3 can be removed using methods such as wet etching, cmps.
In step s3, S3 steps and Fig. 5 in Fig. 2 are referred to, such as embodiment is formed in the upper surface of the adhesive layer 3 Re-wiring layer 1 described in one.
As an example, the specific structural features of the re-wiring layer 1 refer to embodiment one, it is not repeated herein.
Comprise the following steps as an example, forming described re-wiring layer 1 in the upper surface of the adhesive layer 3:
S31:In the bonding:3 upper surface forms the metal seed layer 14;
S32:First layer metal line layer 12 is formed with the upper surface of the metal seed layer 14;
S33:According to the first layer metal line layer etching metal seed layer 14, to remove the first layer metal line The metal seed layer 14 of the periphery of layer 12;
S34:Formed in the upper surface of the adhesive layer 3 and cover the metal seed layer 14 and first layer metal line layer The dielectric layer 11 of 12 upper surfaces and side wall;
S35:In other metal line layers formed in the dielectric layer 11 and first layer metal line layer 12 is electrically connected with 12, electrically connected via metal plug 13 between the adjacent metal line layer 12.
As an example, the material of the metal seed layer 14, each layer metal line layer 12 and the metal plug 13 can Think but be not limited only to copper.Can be using in physical vaporous deposition, chemical vapour deposition technique, sputtering method, plating goods chemical plating At least one form the metal seed layer 14, each layer metal line layer 12 and the metal plug 13.
As an example, the dielectric layer 11 uses low k dielectric.As an example, the dielectric layer 11 can use ring Oxygen tree fat, silica gel, PI, PBO, BCB, silica, phosphosilicate glass or fluorine-containing glass.It can be increased using spin coating, CVD, plasma The techniques such as strong CVD form the dielectric layer 11.
In step s 4, S4 steps and Fig. 6 in Fig. 2 are referred to, the adhesive layer 3 and the carrier 2 is removed.
As an example, can using mechanical lapping, chemical polishing, etching, ultraviolet peel off, one kind in mechanical stripping or It is a variety of to remove the adhesive layer 3 and the carrier 2;Remove the adhesive layer 3 and the carrier 2 is obtained such as embodiment one afterwards Described in re-wiring layer.
Embodiment three
Referring to Fig. 7, the present invention also provides a kind of encapsulating structure, the encapsulating structure at least includes:As in embodiment one Described re-wiring layer 1;The re-wiring layer 1 includes relative first surface and second surface, wherein, the cloth again Line layer 1 is first surface with the surface that the metal seed layer 14 closes on;Active module embedded therein 41, the active module embedded therein 41 is located at described The second surface of re-wiring layer 1, and electrically connected with the metal line layer 12;Passive module 42, the passive module is located at institute The second surface of re-wiring layer 1 is stated, and is electrically connected with the metal line layer 12;Metal connecting pole 5, the metal connecting pole 5 Electrically connected positioned at the second surface of the re-wiring layer 1, and with the metal line layer 12;First plastic packaging layer 6, first modeling Sealing 6 is located at the second surface of the re-wiring layer 1, and fills up the active module embedded therein 41, the passive module 42 and described Gap between metal connecting pole 5;Solder projection 7, the solder projection 7 be located at first plastic packaging layer 6 away from it is described again The surface of wiring layer 1, and electrically connected with the metal connecting pole 5;With electrical chip 8, the use electrical chip 8 is located at the cloth again The first surface of line layer 1, and electrically connected via the metal seed layer 14 with the metal line layer 12.
As an example, re-wiring layer 1 of the concrete structure of the re-wiring layer 1 as described in embodiment one is specific Structure is similar, specifically refers to embodiment one, is not repeated herein.
As an example, the active module embedded therein 41 can include controller and buck converter, the passive module 42 can be with Including electric capacity, inductance and resistance, the active module embedded therein 41 can laterally be arranged in same plane layer with the passive module 42 In, the electrical connection and layout-design of re-wiring layer be easy to and be subsequently formed, certainly, the active module embedded therein 41 with it is described passive The position of the specific arrangement of module 42 can be designed according to actual needs, the invention is not limited in this regard.
It should be noted that in the step, the back side of the active module embedded therein 41 and the back side of the passive module 42 be with The faying face that the re-wiring layer 1 is combined, the re-wiring layer 1 and the active module embedded therein 41 and the passive module 42 Positive weld pad electrical connection, in order to the electrical connection with the re-wiring layer being subsequently formed.
It should be further stated that, when the back side of the active module embedded therein 41 and the back side of the passive module 42 are equipped with During metal pad, alloy-layer can be formed by scaling powder, and using high temperature reflow processes, to realize the active module embedded therein 41 The back side and the metal pad at the back side of the passive module 42 and being welded and fixed for the re-wiring layer 1, so that by institute State active module embedded therein 41 and the passive module 42 is fixed on the re-wiring layer 1;When the active module embedded therein 41 the back side and , can be by bindings such as glue or double faced adhesive tapes by the active mould when back side of the passive module 42 does not have metal pad Block 41 and the passive module 42 are fixed on the re-wiring layer 1.
As an example, the second surface of the re-wiring layer again 1 is additionally provided with Underbump metallization layer 9, the active mould Block 41 and the passive module 42 are electrically connected via Underbump metallization layer 9 with the metal line layer 12.
As an example, the material of the metal connecting pole 5 can include one kind in Cu, Al, Ag, Au, Sn, Ni, Ti, Ta Or it is a variety of, or other suitable conductive metallic materials.Preferably, in the present embodiment, the material of the metal connecting pole 5 can be Cu。
As an example, the material of first plastic packaging layer 6 can for epoxylite, liquid-type thermosetting epoxy resin, Plastic molding compound or the like.
As an example, the solder projection 7 can be solder ball, it is preferable that in the present embodiment, the solder projection 7 is adopted With ball grid array structure (Ball Grid Array, BGA).The encapsulating structure passes through the solder projection 7 and external power source electricity Connection.
As an example, the techniques such as ultrasonic bond, thermocompression bonding or common Reflow Soldering can be used by the use electrical chip 8 Via multiple dimpling block weldings on the re-wiring layer 1.
As an example, described can be but be not limited only to application specific integrated circuit naked core (ASIC Die) with electrical chip 8.
As an example, the encapsulating structure also includes the second plastic packaging layer 81, the second plastic packaging layer 81 is located at the electricity consumption Between chip 8 and the re-wiring layer 1, and the gap filled up between the use electrical chip 8 and the re-wiring layer 1.
Example IV
Referring to Fig. 8, the present invention also provided a kind of preparation method of encapsulating structure, the preparation method of the encapsulating structure Suitable for preparing the encapsulating structure described in embodiment three, the preparation method of the encapsulating structure at least comprises the following steps:
S1:One carrier is provided;
S2:Adhesive layer is formed in the upper surface of the carrier;
S3:The re-wiring layer being performed as described above described in example one is formed in the upper surface of the adhesive layer;Again the cloth Line layer includes relative first surface and second surface, and the first surface of the re-wiring layer is in contact with the adhesive layer;
S4:In second surface bonding active module embedded therein, passive module and the metal connecting pole of the re-wiring layer;It is described to have Source module, the passive module and the metal connecting pole are electrically connected with the metal line layer;
S5:In second surface formation the first plastic packaging layer of the re-wiring layer, first plastic packaging layer, which is filled up, described to be had Gap between source module, the passive module and the metal connecting pole;
S6:Solder projection, the solder projection and institute are formed in surface of first plastic packaging layer away from re-wiring layer State the electrical connection of metal connecting pole;
S7:Remove the adhesive layer and the carrier;
S8:In the first surface bonding electrical chip of the re-wiring layer, the use electrical chip is via the metal kind Sublayer is electrically connected with the metal line layer.
In step sl, there is provided a carrier 2 for the S1 steps and Fig. 9 for referring in Fig. 8.
As an example, the material of the carrier 2 can be in glass, stainless steel, silicon, silica, metal or ceramics One or more, or other analogs.The carrier 2 can be plate.For example, the carrier 2 can be but be not limited only to With the circular flat board of certain thickness glass.
In step s 2, S2 steps and Figure 10 in Fig. 8 are referred to, adhesive layer 3 is formed in the upper surface of the carrier 2.
As an example, the adhesive layer 3 in subsequent technique as the separating layer between re-wiring layer 1 and carrier 2, its Preferably it is made from the jointing material with smooth finish surface, it there must be certain adhesion with re-wiring layer 1, to ensure Situations such as re-wiring layer 1 will not produce mobile in subsequent technique, in addition, its also have with the carrier 2 it is stronger Adhesion, in general, the adhesion of itself and the carrier 2 need to be more than the adhesion with the re-wiring layer 1.As showing Example, the material of the adhesive layer 3 is selected from the two-sided adhesive tape for being respectively provided with viscosity or the adhesive glue made by spin coating proceeding etc..It is described Adhesive tape is preferred to use UV adhesive tapes, and it is easy to pull off after UV light irradiations.In other embodiments, the adhesive layer 3 It can select the other materials layer that physical vaporous deposition or chemical vapour deposition technique refer to, such as epoxy resin (Epoxy), silicon rubber (silicone rubber), polyimides (PI), polybenzoxazoles (PBO), benzocyclobutene (BCB) etc..In later separation institute When stating carrier 2, the adhesive layer 3 can be removed using methods such as wet etching, cmps.
In step s3, S3 steps and Figure 11 in Fig. 8 are referred to, is formed in the upper surface of the adhesive layer 3 as implemented Re-wiring layer 1 described in example one.
As an example, the specific structural features of the re-wiring layer 1 refer to embodiment one, it is not repeated herein.
Comprise the following steps as an example, forming described re-wiring layer 1 in the upper surface of the adhesive layer 3:
S31:The metal seed layer 14 is formed in the upper surface of the adhesive layer 3;
S32:First layer metal line layer 12 is formed with the upper surface of the metal seed layer 14;
S33:According to the first layer metal line layer etching metal seed layer 14, to remove the first layer metal line The metal seed layer 14 of the periphery of layer 12;
S34:Formed in the upper surface of the adhesive layer 3 and cover the metal seed layer 14 and first layer metal line layer The dielectric layer 11 of 12 upper surfaces and side wall;
S35:In other metal line layers formed in the dielectric layer 11 and first layer metal line layer 12 is electrically connected with 12, electrically connected via metal plug 13 between the adjacent metal line layer 12.
As an example, the material of the metal seed layer 14, each layer metal line layer 12 and the metal plug 13 can Think but be not limited only to copper.Can be using in physical vaporous deposition, chemical vapour deposition technique, sputtering method, plating goods chemical plating At least one form the metal seed layer 14, each layer metal line layer 12 and the metal plug 13.
As an example, the dielectric layer 11 uses low k dielectric.As an example, the dielectric layer 11 can use ring Oxygen tree fat, silica gel, PI, PBO, BCB, silica, phosphosilicate glass or fluorine-containing glass.It can be increased using spin coating, CVD, plasma The techniques such as strong CVD form the dielectric layer 11.
Refer to the second surface formation Underbump metallization for being also included in the re-wiring layer 1 after Figure 12, step S3 The step of layer 9;The active module embedded therein 41 and the passive module 42 being subsequently bonded via the Underbump metallization layer 9 with it is described Metal line layer 12 is electrically connected.
In step s 4, the S4 steps and Figure 13 and Figure 14 in Fig. 8 are referred to, in the second table of the re-wiring layer 1 Face bonding active module embedded therein 41, passive module 42 and metal connecting pole 5;The active module embedded therein 41, the passive module 42 and described Metal connecting pole 5 is electrically connected with the metal line layer 12.
As an example, the active module embedded therein 41 can include controller and buck converter, the passive module 42 can be with Including electric capacity, inductance and resistance, the active module embedded therein 41 can laterally be arranged in same plane layer with the passive module 42 In, it is easy to the electrical connection and layout-design with the re-wiring layer 1, certainly, the active module embedded therein 41 and the passive module The position of 42 specific arrangement can be designed according to actual needs, the invention is not limited in this regard.
It should be noted that in the step, the back side of the active module embedded therein 41 and the back side of the passive module 42 be with The faying face that the re-wiring layer 1 is combined, the re-wiring layer 1 and the active module embedded therein 41 and the passive module 42 Positive weld pad electrical connection, in order to the electrical connection with the re-wiring layer being subsequently formed.
It should be further stated that, when the back side of the active module embedded therein 41 and the back side of the passive module 42 are equipped with During metal pad, alloy-layer can be formed by scaling powder, and using high temperature reflow processes, to realize the active module embedded therein 41 The metal pad at the back side and the back side of the passive module 42 is welded and fixed with Underbump metallization layer 9, so that will The active module embedded therein 41 and the passive module 42 are fixed on the re-wiring layer 1;When the back side of the active module embedded therein 41 , can will be described active by bindings such as glue or double faced adhesive tapes and the back side of the passive module 42 is not when having metal pad Module 41 and the passive module 42 are fixed on the re-wiring layer 1 via Underbump metallization layer 9.
As an example, can use but be not limited only to second surface formation institute of the electroplating technology in the re-wiring layer 1 State metal connecting pole 5.
Wrapped as an example, forming the metal connecting pole 5 in the second surface of the re-wiring layer 1 using electroplating technology Include following steps:
The position to form the metal connecting pole 5 is needed to form virtual weld pad in the second surface of the re-wiring layer 1 (not shown);
Photoresist layer (not shown) is formed in the second surface of the re-wiring layer 1 and the virtual weld pad surface;
Need to form the described virtual of the metal connecting pole 5 by exposing, being developed in correspond in the photoresist layer The position of weld pad forms through hole, and the through hole exposes the virtual weld pad;
The metal connecting pole 5 is formed in the through hole using electroplating technology, now, the virtual weld pad can be electricity The Seed Layer of plating;
Remove the photoresist layer.
As an example, the position that needs to form the metal connecting pole 5 on the surface of carrier 21 or forming described virtual Weld pad comprises the following steps:
Metal level is formed in the second surface of the re-wiring layer 1 using metal sputtering or chemical plating;
In layer on surface of metal formation photoresist layer, through hole is formed in the photoresist layer by exposing, being developed in, institute State through hole and define region outside the virtual weld pad;
The metal level of exposure is removed using etching technics, it is to obtain the virtual weld pad to remove the photoresist layer.
As an example, the material of the metal connecting pole 5 can include one kind in Cu, Al, Ag, Au, Sn, Ni, Ti, Ta Or it is a variety of, or other suitable conductive metallic materials.The material of the virtual weld pad equally can include Cu, Al, Ag, Au, Sn, One or more in Ni, Ti, Ta, or other suitable conductive metallic materials.For example, the material of the metal connecting pole 5 can Think Cu, the material of the virtual weld pad can be Ti/Cu.
In step s 5, S5 steps and Figure 15 in Fig. 8 are referred to, is formed in the second surface of the re-wiring layer 1 First plastic packaging layer 6, the first plastic packaging layer 6 fills up the active module embedded therein 41, the passive module 42 and the metal connecting pole 5 Between gap.
As an example, described in being formed using molded underfill technique in the second surface of the re-wiring layer 1 First plastic packaging layer 6.The first plastic packaging layer is formed in the second surface of the re-wiring layer 1 using molded underfill technique 6, capsulation material can promptly fill up the active module embedded therein 41, the passive module 42 and the metal connecting pole 5 with smooth Between gap, it is possible to prevente effectively from there is interface debonding;And molded underfill will not be as capillary bottom of the prior art Portion's fill process is restricted like that, greatly reduces technology difficulty, can be used for smaller joint gap, is more suitable for stacking Framework.
As an example, the material of first plastic packaging layer 6 can for epoxylite, liquid-type thermosetting epoxy resin, Plastic molding compound or the like.
In step s 6, S6 steps and Figure 16 in Fig. 8 are referred to, in first plastic packaging layer 6 away from re-wiring layer 1 Surface form solder projection 7, the solder projection 7 electrically connects with the metal connecting pole 5.
As an example, the solder projection 7 can be solder ball, it is preferable that in the present embodiment, the solder projection 7 is adopted With ball grid array structure (Ball Grid Array, BGA).The encapsulating structure passes through the solder projection 7 and external power source electricity Connection.
In the step s 7, S7 steps and Figure 17 in Fig. 8 are referred to, the adhesive layer 3 and the carrier 2 is removed.
As an example, can using mechanical lapping, chemical polishing, etching, ultraviolet peel off, one kind in mechanical stripping or It is a variety of to peel off the adhesive layer 3 and the carrier 2;Preferably, in the present embodiment, it can be shelled by tearing the adhesive layer 3 From the carrier 2.
In step s 8, S8 steps and Figure 18 in Fig. 8 are referred to, in the rewiring, 1 first surface bonding is used Electrical chip 8, the use electrical chip 8 is electrically connected via the metal seed layer 14 with the metal line layer 12.
As an example, the techniques such as ultrasonic bond, thermocompression bonding or common Reflow Soldering can be used by the use electrical chip 8 Via multiple dimpling block weldings on the metal seed layer 14.
As an example, described can be but be not limited only to application specific integrated circuit naked core (ASIC Die) with electrical chip 8.
As an example, Figure 19 is referred to, after the first surface bonding use battery core of the re-wiring layer 1,8, Also be included in it is described with formed between electrical chip 8 and the re-wiring layer 1 second plastic packaging layer 81 the step of, second plastic packaging The gap that layer 81 is filled up between the use electrical chip 8 and the re-wiring layer 1.
As an example, the area filling bottom between the bottom of use electrical chip 8 and the re-wiring layer 1 can be passed through Portion's packing material to be further secured to described with electrical chip 8 on the re-wiring layer 1, the packing material can be but It is not limited only to underfill.
As an example, can be using capillary underfill process (CUF, Capillary Underfill) or molding bottom Portion's fill process (MUF, Molding UnderFill) is bonded the use battery core, 8 in the first surface of the re-wiring layer 1 Afterwards, also it is included in described with forming second plastic packaging layer 81 between electrical chip 8 and the re-wiring layer 1.
In summary, the present invention provides a kind of re-wiring layer, the encapsulating structure with the re-wiring layer and preparation Method, the re-wiring layer at least includes:Dielectric layer;Metallic stacked structure, it is described metal laminated in the dielectric layer Structure include Spaced arrange metal line layer and metal plug, the metal plug be located at the adjacent metal line layer it Between, the adjacent metal line layer is electrically connected;Metal seed layer, is folded in the dielectric layer, and positioned at the metal On one surface of Rotating fields, the material of the metal seed layer is identical with the material of the metal line layer.The cloth again of the present invention Line layer, as Seed Layer, lateral incision phenomenon is not present when being performed etching to Seed Layer using with its material identical homogenous material, The line width of metal wire and line spacing are smaller in the re-wiring layer;The re-wiring layer is applied in encapsulating structure When, more power supply rails can be obtained in identical size.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as Into all equivalent modifications or change, should by the present invention claim be covered.

Claims (15)

1. a kind of re-wiring layer, it is characterised in that the re-wiring layer at least includes:
Dielectric layer;
Metallic stacked structure, in the dielectric layer, the metallic stacked structure includes the metal line layer that Spaced is arranged And metal plug, the metal plug is located between the adjacent metal line layer, by adjacent metal line layer electrical connection;
Metal seed layer, in the dielectric layer, and on a surface of the metallic stacked structure, the seed metallization The material of layer is identical with the material of the metal line layer.
2. re-wiring layer according to claim 1, it is characterised in that:Include a plurality of gold in each layer metal line layer Belong to line, the line width of the metal wire is less than 2 μm, the adjacent metal wire is smaller than 0.4 μm.
3. re-wiring layer according to claim 1, it is characterised in that:The metal seed layer is away from described metal laminated The surface flush of the surface of structure and the dielectric layer, surface of the metallic stacked structure away from the metal seed layer with The surface flush of the dielectric layer.
4. re-wiring layer according to claim 1, it is characterised in that:The material of the metal line layer and the metal kind The material of sublayer is copper.
5. a kind of preparation method of re-wiring layer, it is characterised in that the preparation method of the re-wiring layer is at least included such as Lower step:
One carrier is provided;
Adhesive layer is formed in the upper surface of the carrier;
The re-wiring layer as any one of Claims 1-4 is formed in the upper surface of the adhesive layer;
Remove the adhesive layer and the carrier.
6. the preparation method of re-wiring layer according to claim 5, it is characterised in that:In the upper surface of the adhesive layer Described re-wiring layer is formed to comprise the following steps:
Metal seed layer is formed in the upper surface of the adhesive layer;
First layer metal line layer is formed with the upper surface of the metal seed layer;
According to the first layer metal line layer etching metal seed layer, to remove the institute of the first layer metal line layer periphery State metal seed layer;
Formed in the upper surface of the adhesive layer and cover the metal seed layer and first layer metal line layer upper surface and side The dielectric layer of wall;
In other metal line layers formed in the dielectric layer and first layer metal line layer is electrically connected with, the adjacent metal Electrically connected between line layer via metal plug.
7. a kind of encapsulating structure, it is characterised in that the encapsulating structure at least includes:
Re-wiring layer as any one of Claims 1-4;The re-wiring layer include relative first surface and Second surface, wherein, the re-wiring layer is first surface with the surface that the metal seed layer closes on;
Active module embedded therein, is electrically connected positioned at the second surface of the re-wiring layer, and with the metal line layer;
Passive module, is electrically connected positioned at the second surface of the re-wiring layer, and with the metal line layer;
Metal connecting pole, is electrically connected positioned at the second surface of the re-wiring layer, and with the metal line layer;
First plastic packaging layer, positioned at the second surface of the re-wiring layer, and fill up the active module embedded therein, the passive module and Gap between the metal connecting pole;
Solder projection, positioned at the surface of the remote re-wiring layer of first plastic packaging layer, and it is electric with the metal connecting pole Connection;
With electrical chip, positioned at the first surface of the re-wiring layer, and via the metal seed layer and the metal line layer Electrical connection.
8. encapsulating structure according to claim 7, it is characterised in that:The encapsulating structure also includes the second plastic packaging layer, institute State the second plastic packaging layer be located between the use electrical chip and the re-wiring layer, and fill up the use electrical chip with it is described again Gap between wiring layer.
9. encapsulating structure according to claim 7, it is characterised in that:The active device includes controller and downconverter Device;
The passive module includes electric capacity, inductance and resistance.
10. encapsulating structure according to claim 7, it is characterised in that:Again the second surface of the re-wiring layer is also Provided with Underbump metallization layer, the active module embedded therein and the passive module are via Underbump metallization layer and the metal line layer Electrical connection.
11. a kind of preparation method of encapsulating structure, it is characterised in that the preparation method of the encapsulating structure at least includes following step Suddenly:
One carrier is provided;
Adhesive layer is formed in the upper surface of the carrier;
The re-wiring layer as any one of Claims 1-4 is formed in the upper surface of the adhesive layer;Again the cloth Line layer includes relative first surface and second surface, and the first surface of the re-wiring layer is in contact with the adhesive layer;
In second surface bonding active module embedded therein, passive module and the metal connecting pole of the re-wiring layer;The active module embedded therein, The passive module and the metal connecting pole are electrically connected with the metal line layer;
In second surface formation the first plastic packaging layer of the re-wiring layer, first plastic packaging layer fill up the active module embedded therein, Gap between the passive module and the metal connecting pole;
Solder projection is formed in surface of first plastic packaging layer away from re-wiring layer, the solder projection connects with the metal Connect post electrical connection;
Remove the adhesive layer and the carrier;
In the first surface bonding electrical chip of the re-wiring layer, the use electrical chip is via the metal seed layer and institute State metal line layer electrical connection.
12. the preparation method of encapsulating structure according to claim 11, it is characterised in that:In the upper surface of the adhesive layer Described re-wiring layer is formed to comprise the following steps:
Metal seed layer is formed in the upper surface of the adhesive layer;
First layer metal line layer is formed with the upper surface of the metal seed layer;
According to the first layer metal line layer etching metal seed layer, to remove the institute of the first layer metal line layer periphery State metal seed layer;
Formed in the upper surface of the adhesive layer and cover the metal seed layer and first layer metal line layer upper surface and side The dielectric layer of wall;
In other metal line layers formed in the dielectric layer and first layer metal line layer is electrically connected with, the adjacent metal Electrically connected between line layer via metal plug.
13. the preparation method of encapsulating structure according to claim 11, it is characterised in that:Using molded underfill technique The first plastic packaging layer is formed in the second surface of the re-wiring layer.
14. the preparation method of encapsulating structure according to claim 11, it is characterised in that:In the of the re-wiring layer Before two surface bond active module embedded thereins, passive module and metal connecting pole, also it is included in the second surface of the re-wiring layer The step of forming Underbump metallization layer;The active module embedded therein and the passive module are via Underbump metallization layer and the gold Belong to line layer electrical connection.
15. the preparation method of encapsulating structure according to claim 11, it is characterised in that:In the of the re-wiring layer After one surface bond electrical chip, be also included in it is described with formed between electrical chip and the re-wiring layer the second plastic packaging layer The step of, the gap that the second plastic packaging layer is filled up between the use electrical chip and the re-wiring layer.
CN201710338191.6A 2017-05-15 2017-05-15 Rewiring layer, packaging structure with same and preparation method Active CN107104090B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710338191.6A CN107104090B (en) 2017-05-15 2017-05-15 Rewiring layer, packaging structure with same and preparation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710338191.6A CN107104090B (en) 2017-05-15 2017-05-15 Rewiring layer, packaging structure with same and preparation method

Publications (2)

Publication Number Publication Date
CN107104090A true CN107104090A (en) 2017-08-29
CN107104090B CN107104090B (en) 2023-09-19

Family

ID=59670697

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710338191.6A Active CN107104090B (en) 2017-05-15 2017-05-15 Rewiring layer, packaging structure with same and preparation method

Country Status (1)

Country Link
CN (1) CN107104090B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108389822A (en) * 2018-01-31 2018-08-10 浙江卓晶科技有限公司 A kind of three-dimensional fan-out-type integrated encapsulation structure and its packaging technology
CN108389823A (en) * 2018-01-31 2018-08-10 浙江卓晶科技有限公司 For multi-chip wafer scale fan-out-type 3 D stereo encapsulating structure and its packaging technology
CN109727848A (en) * 2018-12-29 2019-05-07 长江存储科技有限责任公司 A kind of manufacturing method of three-dimensional storage
CN110034085A (en) * 2017-12-25 2019-07-19 瑞萨电子株式会社 Semiconductor devices
US11145574B2 (en) 2018-10-30 2021-10-12 Microchip Technology Incorporated Semiconductor device packages with electrical routing improvements and related methods

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060057772A1 (en) * 2004-04-09 2006-03-16 Advanced Semiconductor Engineering, Inc. Method for forming a redistribution layer in a wafer structure
CN102623392A (en) * 2011-01-31 2012-08-01 瑞萨电子株式会社 Manufacturing method of semiconductor device and semiconductor device
CN105552059A (en) * 2014-10-22 2016-05-04 日月光半导体制造股份有限公司 Semiconductor package structure and semiconductor process
CN106571356A (en) * 2015-10-08 2017-04-19 美光科技公司 Package-on-package assembly

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060057772A1 (en) * 2004-04-09 2006-03-16 Advanced Semiconductor Engineering, Inc. Method for forming a redistribution layer in a wafer structure
CN102623392A (en) * 2011-01-31 2012-08-01 瑞萨电子株式会社 Manufacturing method of semiconductor device and semiconductor device
CN105552059A (en) * 2014-10-22 2016-05-04 日月光半导体制造股份有限公司 Semiconductor package structure and semiconductor process
CN106571356A (en) * 2015-10-08 2017-04-19 美光科技公司 Package-on-package assembly

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110034085A (en) * 2017-12-25 2019-07-19 瑞萨电子株式会社 Semiconductor devices
CN108389822A (en) * 2018-01-31 2018-08-10 浙江卓晶科技有限公司 A kind of three-dimensional fan-out-type integrated encapsulation structure and its packaging technology
CN108389823A (en) * 2018-01-31 2018-08-10 浙江卓晶科技有限公司 For multi-chip wafer scale fan-out-type 3 D stereo encapsulating structure and its packaging technology
US11145574B2 (en) 2018-10-30 2021-10-12 Microchip Technology Incorporated Semiconductor device packages with electrical routing improvements and related methods
CN109727848A (en) * 2018-12-29 2019-05-07 长江存储科技有限责任公司 A kind of manufacturing method of three-dimensional storage

Also Published As

Publication number Publication date
CN107104090B (en) 2023-09-19

Similar Documents

Publication Publication Date Title
CN107104090A (en) Re-wiring layer, the encapsulating structure with the re-wiring layer and preparation method
CN105070671B (en) A kind of chip packaging method
CN106816421B (en) It is integrated with the packaging method of the encapsulating structure of power transmission chip
CN106887393B (en) It is integrated with the packaging method of the encapsulating structure of power transmission chip
CN107706521A (en) Fan-out-type antenna packages structure and preparation method thereof
CN103681561A (en) Passive devices in package-on-package structures and methods for forming the same
CN104409437B (en) Encapsulating structure rerouted after two-sided BUMP chip packages and preparation method thereof
CN106981468A (en) Fan-out-type wafer level packaging structure and preparation method thereof
CN107301983A (en) Fan-out package structure and preparation method thereof
CN107742778A (en) Fan-out-type antenna packages structure and preparation method thereof
CN107248509A (en) The chip-packaging structure and method for packing of EMI protection
CN107452702A (en) The encapsulating structure and method for packing of semiconductor chip
CN107195551A (en) Fan-out-type laminated packaging structure and preparation method thereof
CN107393885A (en) Fan-out package structure and preparation method thereof
CN107195625A (en) Two-sided system-level laminated packaging structure of plastic packaging fan-out-type and preparation method thereof
CN107611045A (en) A kind of three-dimensional chip encapsulating structure and its method for packing
CN106981467A (en) Fan-out-type wafer level packaging structure and preparation method thereof
CN106898557B (en) It is integrated with the packaging method of the packaging part of power transmission system
CN206931602U (en) The two-sided system-level laminated packaging structure of plastic packaging fan-out-type
CN206758428U (en) Fan-out-type wafer level packaging structure
CN207165556U (en) Re-wiring layer and the encapsulating structure with the re-wiring layer
CN109727934A (en) Encapsulating structure and preparation method thereof
CN110137157A (en) Semiconductor package and preparation method thereof
CN207217505U (en) Semiconductor structure and fan-out package structure
WO2018129906A1 (en) Package method for integrated power supply system packaging piece

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City)

Applicant after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd.

Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province

Applicant before: SJ Semiconductor (Jiangyin) Corp.

CB02 Change of applicant information
GR01 Patent grant
GR01 Patent grant