CN108231611A - The integrated approach of two-sided surface-mount type semiconductor integrated circuit - Google Patents
The integrated approach of two-sided surface-mount type semiconductor integrated circuit Download PDFInfo
- Publication number
- CN108231611A CN108231611A CN201611189633.7A CN201611189633A CN108231611A CN 108231611 A CN108231611 A CN 108231611A CN 201611189633 A CN201611189633 A CN 201611189633A CN 108231611 A CN108231611 A CN 108231611A
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- Prior art keywords
- integrated circuit
- semiconductor integrated
- ceramic substrate
- substrate
- chip
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 239000000919 ceramic Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 239000002184 metal Substances 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 13
- 230000010354 integration Effects 0.000 claims abstract description 9
- 238000005245 sintering Methods 0.000 claims abstract description 7
- 239000011248 coating agent Substances 0.000 claims abstract description 4
- 238000000576 coating method Methods 0.000 claims abstract description 4
- 238000007772 electroless plating Methods 0.000 claims abstract description 4
- 238000000465 moulding Methods 0.000 claims abstract description 4
- 230000008569 process Effects 0.000 claims abstract description 4
- 238000007650 screen-printing Methods 0.000 claims abstract description 4
- 238000001771 vacuum deposition Methods 0.000 claims abstract description 4
- 230000008719 thickening Effects 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 230000008859 change Effects 0.000 abstract description 7
- 238000005516 engineering process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910002796 Si–Al Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004021 metal welding Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4885—Wire-like parts or pins
- H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
In the outer surface of the ceramic pipe cap of advance sinter molding, required metal layer is formed with the mode of the sintering of coating metal paste, electroless plating or vacuum coating for the integrated approach of two-sided surface-mount type semiconductor integrated circuit；Upper and lower ceramic substrate is made with sintering process with low-temperature co-fired ceramics technique and thick film screen printing, semiconductor integrated circuit chip bonding region, surface metal-layer are respectively formed on upper and lower ceramic substrate, to outer pin；Semiconductor integrated circuit chip back bonding is carried out again；Chip is connected by the substrate for being then assembled with chip by two pieces Face to face with surface-mount type Integration Method, electrical pin is drawn respectively from the back side of upper and lower ceramic substrate, High Density Integration and two-sided pin so as to fulfill semiconductor integrated circuit, obtain two-sided surface-mount type semiconductor integrated circuit.The present invention solves the problems, such as that semiconductor integrated circuit is limited in change system miniaturization, integrated and lighting application field, and the device using the present invention is widely used in each industrial circle.
Description
Technical field
The present invention relates to semiconductor integrated circuit, more specifically, are related to two-sided surface-mount type semiconductor integrated circuit
Integrated approach.
Background technology
In the integrated technology of original semiconductor integrated circuit, semiconductor integrated circuit chip is encapsulated in metal base and gold
Belong in pipe cap or be encapsulated in ceramic tube base in ceramic pipe cap, be first attached to semiconductor integrated circuit chip dress on Guan Ji, then adopt
Use bonding wire（Spun gold or Si-Al wire）Carry out the wire bonding of chip and pin, complete entire electric appliance connection, finally by Guan Ji and
Pipe cap is sealed.Main problem of the existing technology is：Interior of IC package is only capable of carrying out single stack package, no
Encapsulated space can be made full use of to carry out the encapsulation of more IC chips；On the other hand, semiconductor integrated circuit package shell
Pin only from single side draw, be not suitable for 3 D stereo assembling.These two aspects is all unfavorable for the miniaturization of change system, collection
Into change and lighting.
The application part of semiconductor integrated circuit involved in Chinese patent database has thousands of, just having since 2015
57, illustrate that the field technology progress is very fast.Such as No. 2015209928947《A kind of anti-interference semiconductor integrated circuit》、
No. 2015209932124《A kind of anti-interference anticorrosive semiconductor integrated circuit》, No. 2015201161706《The void of integrated circuit
Intend pattern and semiconductor integrated circuit》Deng；The application part for being related to semiconductor integrated circuit integrated approach has：
No. 201510881974X《The integrated approach of anti-interference anticorrosive semiconductor integrated circuit》With No. 2015108817903《It is anti-interference
The integrated approach of semiconductor integrated circuit》.However so far, it there is no and be related to the two-sided surface-mount type semiconductor integrated circuit side of integrating
The application part of method.
Invention content
The present invention is intended to provide the integrated approach of two-sided surface-mount type semiconductor integrated circuit, makes full use of encapsulated space to carry out
The encapsulation of more IC chips, the defects of original technology is overcome to be difficult to realize equipment miniaturization, integrated and lighting.
Designer for original semiconductor integrated circuit there are the problem of, the two-sided surface-mount type semiconductor provided integrates electricity
Road integrated approach is：In the outer surface of the ceramic pipe cap of advance sinter molding, using the sintering of coating metal paste, electroless plating or
The mode of vacuum coating forms required metal layer；Using low-temperature co-fired ceramics technique（LTCC techniques）And thick film screen printing and agglomerant
Skill makes upper ceramic substrate and lower ceramic substrate, and semiconductor integrated circuit is respectively formed on upper ceramic substrate and lower ceramic substrate
Chip bonding area, surface metal-layer, to outer pin；The back bonding of semiconductor integrated circuit chip is carried out again；Then by two pieces
The substrate for being assembled with semiconductor integrated circuit chip is connected face-to-face, symmetrically with surface-mount type Integration Method chip, externally
Electrical pin is drawn respectively from the back side of upper ceramic substrate and lower ceramic substrate, so as to fulfill the high density of semiconductor integrated circuit
Integrated and two-sided pin, obtains two-sided surface-mount type semiconductor integrated circuit.
Above-mentioned two pieces of substrates for being assembled with semiconductor integrated circuit chip face-to-face, symmetrically attaching when be with ceramics thicken
Layer is connected to become whole.
Above-mentioned two substrate and ceramic thickening layer have through-hole, and upper ceramic substrate and lower ceramic substrate have semiconductor to integrate respectively
Circuit chip is connect by external electrical connection terminal with metal pins.
There is metal pad between above-mentioned external electrical connection terminal and ceramic substrate.
The metal pins direction of above-mentioned two substrate is on the contrary, metal pins have solder sphere.
The integrated approach of two-sided surface-mount type semiconductor integrated circuit has the following advantages：1. it can realize multiple semiconductor collection
It is integrated into circuit chip bilayer, realizes High Density Integration；2. using two-sided pin, it can be achieved that 3 D stereo assembles；3. it can integrate
More circuit functions realize the system integration；4. realizing surface-mount type installation, equipment volume, the high frequency performance of hoisting device are reduced；
5. improve the reliability of change system；6. extend to the High Density Integration of other circuit modules.
The present invention solves original semiconductor integrated circuit should in the minimizing of change system, integrated and lighting etc.
The problem being restricted with field, the device using the present invention are widely used in space flight, aviation, ship, electronics, communication, medical treatment
The fields such as equipment, Industry Control especially suitable for change system miniaturization, high frequency, highly reliable field, have a vast market
Prospect and application space.
Description of the drawings
Fig. 1 is the semiconductor integrated circuit structure schematic diagram of original technology, and Fig. 2 is upper ceramic substrate, lower ceramic substrate
Back side assembling schematic diagram, Fig. 3 are the assembling schematic diagram of the two-sided surface-mount type semiconductor integrated circuit of the present invention.
In figure, 1 is metal base, and 2 be metab, and 3 be metal pin, and 4 be metal pipe cap, and 5 integrate electricity for semiconductor
Road chip, 6 be bonding wire, and 7 be upper ceramic substrate, and 8 be upper metal pins, and 9 be semiconductor-on-insulator IC chip, and 10 be electrical
Bonding ribbon, 11 be ceramic thickening layer, and 12 be plated-through hole, and 13 be lower ceramic substrate, and 14 be upper ceramic substrate metal welding
Disk, 15 be upper metal pins, and 16 be lower semiconductor IC chip, and 17 connect outdoor electrical for lower semiconductor IC chip
End is connect, 18 be the external electrical connection terminal of semiconductor-on-insulator IC chip, and 19 be the electrical connection terminal of ceramic substrate.
Specific embodiment
Embodiment
The integrated approach of the two-sided surface-mount type semiconductor integrated circuit of structure such as Fig. 3
In the outer surface of the ceramic pipe cap 4 of advance sinter molding, using the sintering of coating metal paste, electroless plating or vacuum coating
Mode form required metal layer；Upper ceramic substrate 7 is made with sintering process using low-temperature co-fired ceramics technique and thick film screen printing
And lower ceramic substrate 13, be respectively formed on upper ceramic substrate 7 and lower ceramic substrate 13 semiconductor integrated circuit chip bonding region,
Surface metal-layer, to outer pin；The back bonding of semiconductor integrated circuit chip 9,16 is carried out again；Then it is assembled with half by two pieces
The substrate of conductor IC chip is connected face-to-face, symmetrically with surface-mount type Integration Method chip 9,16, electrical pin
8th, it 15 is drawn respectively from the back side of upper ceramic substrate 7 and lower ceramic substrate 13, so as to fulfill the high density of semiconductor integrated circuit
Integrated and two-sided pin, obtains two-sided surface-mount type semiconductor integrated circuit.Two substrates 7,13 and ceramic thickening layer 11 have metal
Change through-hole 12, upper ceramic substrate 7 and lower ceramic substrate 13 have semiconductor integrated circuit chip 9,16 by connecting to outdoor electrical respectively
End 17,18 is connect to connect with metal pins 8,15.Externally there is metal pad between electrical connection terminal 17,18 and ceramic substrate 7,13
14.Metal pins 8,15 directions of two substrates 7,13 are on the contrary, metal pins 8,15 have solder sphere.
Claims (5)
1. the integrated approach of two-sided surface-mount type semiconductor integrated circuit, it is characterised in that in the ceramic pipe cap of advance sinter molding
Outer surface forms required metal layer by the way of the sintering of coating metal paste, electroless plating or vacuum coating；It is total to using low temperature
It burns ceramic process and thick film screen printing and makes upper ceramic substrate and lower ceramic substrate with sintering process, in upper ceramic substrate and lower ceramics
Semiconductor integrated circuit chip bonding region, surface metal-layer are respectively formed on substrate, to outer pin；Semiconductor is carried out again integrates electricity
The back bonding of road chip；Then the substrate for being assembled with semiconductor integrated circuit chip by two pieces surface-mount type Integration Method chip face
Opposite is symmetrically connected, and external electrical pin is drawn respectively from the back side of upper ceramic substrate and lower ceramic substrate, so as to
It realizes the High Density Integration of semiconductor integrated circuit and two-sided pin, obtains two-sided surface-mount type semiconductor integrated circuit.
2. integrated approach as described in claim 1, it is characterised in that described two pieces are assembled with semiconductor integrated circuit chip
Substrate face-to-face, symmetrically attaching when with ceramics thickening layer be connected to become it is whole.
3. integrated approach as described in claim 1, it is characterised in that two substrate and ceramic thickening layer have through-hole, upper pottery
Ceramic chip and lower ceramic substrate have semiconductor integrated circuit chip to be connect by external electrical connection terminal with metal pins respectively.
4. integrated approach as described in claim 1, it is characterised in that have between the external electrical connection terminal and ceramic substrate
Metal pad.
5. integrated approach as described in claim 1, it is characterised in that the metal pins direction of two substrate is on the contrary, metal draws
Foot has solder sphere.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611189633.7A CN108231611A (en) | 2016-12-21 | 2016-12-21 | The integrated approach of two-sided surface-mount type semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611189633.7A CN108231611A (en) | 2016-12-21 | 2016-12-21 | The integrated approach of two-sided surface-mount type semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108231611A true CN108231611A (en) | 2018-06-29 |
Family
ID=62650967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611189633.7A Pending CN108231611A (en) | 2016-12-21 | 2016-12-21 | The integrated approach of two-sided surface-mount type semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108231611A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080157295A1 (en) * | 2006-12-20 | 2008-07-03 | Custom One Design, Inc. | Methods and apparatus for multichip module packaging |
| CN104157619A (en) * | 2014-08-22 | 2014-11-19 | 山东华芯半导体有限公司 | Novel PoP stack packaging structure and manufacture method thereof |
| CN104332457A (en) * | 2014-09-05 | 2015-02-04 | 华进半导体封装先导技术研发中心有限公司 | High-density IO interconnection package-on-package (PoP) structure and manufacturing process thereof |
| CN105514087A (en) * | 2016-01-26 | 2016-04-20 | 中芯长电半导体（江阴）有限公司 | Double-faced fan-out type wafer-level packaging method and packaging structure |
-
2016
- 2016-12-21 CN CN201611189633.7A patent/CN108231611A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080157295A1 (en) * | 2006-12-20 | 2008-07-03 | Custom One Design, Inc. | Methods and apparatus for multichip module packaging |
| CN104157619A (en) * | 2014-08-22 | 2014-11-19 | 山东华芯半导体有限公司 | Novel PoP stack packaging structure and manufacture method thereof |
| CN104332457A (en) * | 2014-09-05 | 2015-02-04 | 华进半导体封装先导技术研发中心有限公司 | High-density IO interconnection package-on-package (PoP) structure and manufacturing process thereof |
| CN105514087A (en) * | 2016-01-26 | 2016-04-20 | 中芯长电半导体（江阴）有限公司 | Double-faced fan-out type wafer-level packaging method and packaging structure |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180629 |
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| RJ01 | Rejection of invention patent application after publication |