CN110120385A - Semiconductor package and preparation method thereof - Google Patents
Semiconductor package and preparation method thereof Download PDFInfo
- Publication number
- CN110120385A CN110120385A CN201910477411.2A CN201910477411A CN110120385A CN 110120385 A CN110120385 A CN 110120385A CN 201910477411 A CN201910477411 A CN 201910477411A CN 110120385 A CN110120385 A CN 110120385A
- Authority
- CN
- China
- Prior art keywords
- layer
- antenna
- glass substrate
- electric connection
- connection structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000002360 preparation method Methods 0.000 title claims abstract description 30
- 239000011521 glass Substances 0.000 claims abstract description 138
- 239000000758 substrate Substances 0.000 claims abstract description 135
- 239000004033 plastic Substances 0.000 claims abstract description 76
- 229920003023 plastic Polymers 0.000 claims abstract description 76
- 238000004806 packaging method and process Methods 0.000 claims abstract description 75
- 239000000463 material Substances 0.000 claims description 45
- 229910052751 metal Inorganic materials 0.000 claims description 44
- 239000002184 metal Substances 0.000 claims description 44
- 238000005530 etching Methods 0.000 claims description 9
- 239000004744 fabric Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 238000012546 transfer Methods 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 211
- 238000000034 method Methods 0.000 description 35
- 230000008569 process Effects 0.000 description 20
- 238000005516 engineering process Methods 0.000 description 15
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 239000004642 Polyimide Substances 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 239000004411 aluminium Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 229920000647 polyepoxide Polymers 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 239000000741 silica gel Substances 0.000 description 6
- 229910002027 silica gel Inorganic materials 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 238000000465 moulding Methods 0.000 description 5
- 238000004528 spin coating Methods 0.000 description 5
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 229920002577 polybenzoxazole Polymers 0.000 description 4
- 238000003475 lamination Methods 0.000 description 3
- 238000010295 mobile communication Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 238000007641 inkjet printing Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 208000032365 Electromagnetic interference Diseases 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Variable-Direction Aerials And Aerial Arrays (AREA)
Abstract
The present invention provides a kind of semiconductor package and preparation method thereof, and semiconductor package includes: glass substrate；First antenna layer, positioned at the first surface of glass substrate；Second antenna stack, positioned at the second surface of glass substrate；First electric connection structure extends to second surface from the first surface of glass substrate；Second electric connection structure, the surface positioned at the second antenna stack far from glass substrate；Plastic packaging layer, positioned at the second surface of glass substrate；Re-wiring layer, the surface positioned at plastic packaging layer far from glass substrate；Chip, back bonding is in surface of the re-wiring layer far from plastic packaging layer；Soldered ball convex block, the surface positioned at re-wiring layer far from plastic packaging layer, and be electrically connected with re-wiring layer.Semiconductor package of the invention can be reduced significantly the size and volume of semiconductor package, improve device integration；It does not need additional carrier and is packaged transfer, significantly simplify preparation process, save the preparation cost.
Description
Technical field
The invention belongs to field of semiconductor package, more particularly to a kind of semiconductor package and preparation method thereof.
Background technique
With the development of economy with the progress of science and technology, various high-tech electronic products emerge one after another, greatly convenient and rich
Rich people's lives, among these with the hair for the various portable mobile communication terminals that mobile phone and tablet computer (PAD) are representative
It opens up especially noticeable.
Existing portable mobile communication terminal is usually built-in with antenna structure for communication function, for example, realize voice and
Video connects and surfs the web.The common method of built-in antenna is that antenna is directly made in the surface of circuit board at present,
But this method causes the conformability of device poor because antenna need to occupy additional board area, constrains mobile communication terminal
Miniaturise.Simultaneously as electronic circuit is relatively more on circuit board, there are electromagnetic interferences between antenna and All other routes
The problems such as, or even there is also the risks that antenna and other metallic circuits are shorted.
Although having occurred the technology for encapsulating antenna and chip together in encapsulation field, need in encapsulation process by load
Body carries out transfer encapsulation, needs carrier carrying out removing removal, complex process and higher cost after transfer encapsulation.In addition, existing
Antenna packages be mostly single layer structure, size is larger, and conformability is lower, and antenna efficiency is lower, has been insufficient for antenna
The increasing demand of performance.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of semiconductor package and its
Preparation method, for solving, antenna packages structural integration is lower in the prior art, size is larger, preparation process is complicated and preparation
The problems such as higher cost.
In order to achieve the above objects and other related objects, the present invention provides a kind of semiconductor package, the semiconductor
Encapsulating structure includes:
Glass substrate, the glass substrate include first surface and the second surface opposite with the first surface；
First antenna layer, positioned at the first surface of the glass substrate；
Second antenna stack, positioned at the second surface of the glass substrate；
First electric connection structure extends to the second surface of the glass substrate from the first surface of the glass substrate,
And it is electrically connected with the first antenna layer and second antenna stack；
Second electric connection structure, positioned at the surface of second antenna stack far from the glass substrate；
Plastic packaging layer is electrically connected positioned at the second surface of the glass substrate, and by second antenna stack and described second
Structure plastic packaging；
Re-wiring layer, positioned at the surface of the plastic packaging layer far from the glass substrate, the re-wiring layer with it is described
The electrical connection of second electric connection structure；
Chip, back bonding in surface of the re-wiring layer far from the plastic packaging layer, and with the re-wiring layer
Electrical connection；
Soldered ball convex block, the surface positioned at the re-wiring layer far from the plastic packaging layer, and it is electric with the re-wiring layer
Connection.
Optionally, the first antenna layer includes multiple first antennas being intervally arranged, and second antenna stack includes more
A the second antenna being intervally arranged, the quantity of first electric connection structure are multiple；The first antenna, second antenna
And the quantity of first electric connection structure is identical, the first antenna is correspondingly arranged up and down one by one with second antenna, institute
It states the first electric connection structure and is electrically connected the first antenna with second antenna one-to-one correspondence.
Optionally, first electric connection structure includes metal wire or metallic conduction post, second electric connection structure
Including metal wire or metallic conduction post.
Optionally, the re-wiring layer includes:
It is routed dielectric layer, positioned at the surface of the plastic packaging layer far from the glass substrate；
Metallic stacked structure is located in the wiring dielectric layer, and the metallic stacked structure includes what Spaced was arranged
Metal line layer and metal plug, the metal plug is between the adjacent metal line layer, by the adjacent metal line layer
Electrical connection.
Optionally, the semiconductor package further includes Underfill layer, and the Underfill layer is filled in the core
Between piece and the re-wiring layer.
The present invention also provides a kind of preparation method of semiconductor package, the preparation method of the semiconductor package
Comprising steps of
Glass substrate is provided, the glass substrate includes first surface and the second surface opposite with the first surface；
In forming the first electric connection structure in the glass substrate, and first is formed in the first surface of the glass substrate
Antenna stack, and the second antenna stack is formed in the second surface of the glass substrate；First electric connection structure is from the glass
The first surface of substrate extends to the second surface of the glass substrate；The first antenna layer and second antenna stack and institute
State the electrical connection of the first electric connection structure；
The second electric connection structure is formed far from the surface of the glass substrate in second antenna stack；
Plastic packaging layer is formed in the second surface of the glass substrate, and the plastic packaging layer is by second antenna stack and described the
Two electric connection structure plastic packagings；
In the plastic packaging layer far from the glass substrate surface formed re-wiring layer, the re-wiring layer with it is described
The electrical connection of second electric connection structure；
Chip is provided, the flip-chip is bonded to surface of the re-wiring layer far from the plastic packaging layer, and with
The re-wiring layer electrical connection；
In the re-wiring layer far from the plastic packaging layer surface formed soldered ball convex block, the soldered ball convex block with it is described heavy
The electrical connection of new route layer.
Optionally, the first surface of Yu Suoshu glass substrate forms first antenna layer, and in the second of the glass substrate
Surface forms the second antenna stack and includes the following steps:
First antenna material layer is formed in the first surface of the glass substrate；
Perform etching to the first antenna material layer includes described the of multiple first antennas being intervally arranged to obtain
One antenna stack, the first antenna are electrically connected with first electric connection structure one-to-one correspondence；
The second antenna material layer is formed in the second surface of the glass substrate；
Perform etching to the second antenna material layer includes described the of multiple the second antennas being intervally arranged to obtain
Two antenna stacks, second antenna are electrically connected with first electric connection structure one-to-one correspondence.
Optionally, the flip-chip is bonded to after surface of the re-wiring layer far from the plastic packaging layer and is also wrapped
Include the step of Underfill layer is formed between the chip and the re-wiring layer.
Optionally, several described flip-chips are bonded to surface of the re-wiring layer far from the plastic packaging layer,
Each chip two sides are each formed with the soldered ball convex block；Institute is formed far from the surface of the plastic packaging layer in the re-wiring layer
State and further include the steps that after soldered ball convex block resulting structures carrying out slicing treatment, if with obtain several include one single chip and
The semiconductor package of the dry soldered ball convex block.
As described above, semiconductor package and preparation method thereof of the invention have the following beneficial effects: it is of the invention
Semiconductor package by by first antenna layer and the second antenna stack be respectively arranged at the opposite first surface of glass substrate and
Second surface can be reduced significantly the size and volume of semiconductor package, improve device integration；Glass substrate is directly made
It for first antenna layer and the bearing substrate of the second antenna stack, does not need additional carrier and is packaged transfer, also shelled without carrier
Separating process significantly simplifies preparation process, saves the preparation cost.
Detailed description of the invention
Fig. 1 is shown as the flow chart of the preparation method of the semiconductor package provided in the embodiment of the present invention one.
Fig. 2 to Fig. 9 is shown as each step in the preparation method of the semiconductor package provided in the embodiment of the present invention one
The cross section structure schematic diagram of resulting structures；Wherein, Fig. 9 is also cutting for the semiconductor package provided in the embodiment of the present invention two
Face structural schematic diagram.
Component label instructions
10 glass substrates
11 first antenna layers
111 first antennas
12 second antenna stacks
121 second antennas
13 first electric connection structures
14 second electric connection structures
15 plastic packaging layers
16 re-wiring layers
161 wiring dielectric layers
162 metallic stacked structures
17 chips
18 soldered ball convex blocks
19 Underfill layers
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Please refer to FIG. 1 to FIG. 9.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shown in diagram then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present invention provides a kind of preparation method of semiconductor package, the semiconductor package
Preparation method includes the following steps:
1) glass substrate is provided, the glass substrate includes first surface and second table opposite with the first surface
Face；
2) it forms the first electric connection structure in Yu Suoshu glass substrate, and forms the in the first surface of the glass substrate
One antenna stack, and the second antenna stack is formed in the second surface of the glass substrate；First electric connection structure is from the glass
The first surface of glass substrate extends to the second surface of the glass substrate；The first antenna layer and second antenna stack with
The first electric connection structure electrical connection；
3) the second antenna stack of Yu Suoshu forms the second electric connection structure far from the surface of the glass substrate；
4) second surface of Yu Suoshu glass substrate forms plastic packaging layer, and the plastic packaging layer is by second antenna stack and described
Second electric connection structure plastic packaging；
5) Yu Suoshu plastic packaging layer forms re-wiring layer, the re-wiring layer and institute far from the surface of the glass substrate
State the electrical connection of the second electric connection structure；
6) chip is provided, the flip-chip is bonded to surface of the re-wiring layer far from the plastic packaging layer, and
It is electrically connected with the re-wiring layer；
7) Yu Suoshu re-wiring layer far from the plastic packaging layer surface formed soldered ball convex block, the soldered ball convex block with it is described
Re-wiring layer electrical connection.
In step 1), S1 step and Fig. 2 in Fig. 1 are please referred to, glass substrate 10 is provided, the glass substrate 10 includes
First surface (for example, the lower surface of the glass substrate 10 in Fig. 2) and the second surface (example opposite with the first surface
Such as, the upper surface of the glass substrate 10 in Fig. 2).
As an example, the glass substrate 10 can be the substrate that any one existing glass is made into, it is preferable that described
Glass substrate 10 may include the unorganic glass such as silicate substrate or pmma substrate etc..
As an example, the thickness of the glass substrate 10 can be set according to actual needs, herein without limitation.
In step 2), S2 step and Fig. 3 in Fig. 1 are please referred to, forms the first electrical connection in Yu Suoshu glass substrate 10
Structure 13, and first antenna layer 11 is formed in the first surface of the glass substrate 10, and in the second of the glass substrate 10
Surface forms the second antenna stack 12；The first surface of first electric connection structure 13 from the glass substrate 10 extends to described
The second surface of glass substrate 10；The first antenna layer 11 and second antenna stack 12 and first electric connection structure 13
Electrical connection.
As an example, step 2) may include steps of:
2-1) form through-hole (not shown) in Yu Suoshu glass substrate 10, the through-hole from the glass substrate 10 first
Surface extends to the second surface of the glass substrate 10；In forming the first electric connection structure 13 in the through-hole；The through-hole
And the quantity of first electric connection structure 13 can be set according to actual needs, it is preferable that described logical in the present embodiment
The quantity and second antenna of the quantity of hole and first electric connection structure 13 and the first antenna 111 being subsequently formed
121 quantity is identical, only includes four first antennas 111 using in the first antenna layer 11 in Fig. 3 as example；
2-2) first surface of Yu Suoshu glass substrate 10 forms first antenna material layer (not indicating)；Specifically, can
To form the first antenna using sputtering technology, electroplating technology, physical gas-phase deposition or chemical vapor deposition process etc.
Material layer；
2-3) perform etching to the first antenna material layer includes multiple first antennas 111 being intervally arranged to obtain
The first antenna layer 11；Specifically, lithographic etch process can be used to perform etching to obtain the first antenna material layer
To the first antenna layer 11；The quantity of first antenna 111 described in the first antenna layer 11 can according to actual needs into
Row setting only includes four first antennas 111 using in the first antenna layer 11 herein without limitation, in Fig. 3 as showing
Example；The shape of the first antenna 111 can be blocky, helical form or ring-type etc.；The first antenna 111 and described first
Electric connection structure 13 corresponds electrical connection；
2-4) second surface of Yu Suoshu glass substrate 10 forms the second antenna material layer (not indicating)；Specifically, can
To form second antenna using sputtering technology, electroplating technology, physical gas-phase deposition or chemical vapor deposition process etc.
Material layer；
2-5) performing etching to the second antenna material layer includes multiple the second antennas 121 being intervally arranged to obtain
Second antenna stack 12；Specifically, lithographic etch process can be used to perform etching to obtain the second antenna material layer
To second antenna stack 12；The quantity of second antenna 121 described in second antenna stack 12 can according to actual needs into
Row setting only includes four second antennas 121 using in second antenna stack 12 herein without limitation, in Fig. 3 as showing
Example；The shape of second antenna 121 can be blocky, helical form or ring-type etc.；Second antenna 121 and described first
Electric connection structure 13 corresponds electrical connection.
In other examples, it can also be initially formed the first antenna layer 11, then in the glass substrate 10
Form first connection structure 13；Finally re-form second antenna stack 12.
In other examples, the method for forming the first antenna layer 11 and second antenna stack 12 may be: first
First, while in the first surface of the glass substrate 10 and second surface the first antenna material layer and described the are respectively formed
Then two antenna material layers again respectively perform etching to obtain the first antenna material layer and the second antenna material layer
The first antenna layer 11 and second antenna stack 12.
As an example, the material of the first antenna 111 may include but be not limited only in copper, aluminium, silver, nickel, gold and titanium
At least one；The material of second antenna 121 may include but be not limited only in copper, aluminium, silver, nickel, gold and titanium at least
It is a kind of.
As an example, in the first antenna layer 11 in the quantity of the first antenna 111 and second antenna stack 12
The quantity of second antenna 121 is identical, and the first antenna 111 is correspondingly arranged up and down one by one with second antenna 121.
As an example, the first antenna 111 and second antenna 121 may each comprise but be not limited only to oscillator day
Line.
As an example, first electric connection structure 13 may include metal wire or metallic conduction post.
In step 3), S3 step and Fig. 4 in Fig. 1 are please referred to, the second antenna stack of Yu Suoshu 12 is far from the glass base
The surface of plate 10 forms the second electric connection structure 14.
As an example, can use routing technique or column bonding technology in second antenna stack 12 far from the glass base
The surface of plate 10 forms second electric connection structure 14；Second electric connection structure 14 may include metal wire or metal
Conductive column.
As an example, the quantity of second electric connection structure 14 can be set according to actual needs, it is preferable that this
In embodiment, the quantity of the second antenna 121 described in the quantity of second electric connection structure 14 and second antenna stack 12
It is identical, and second electric connection structure 14 is arranged in a one-to-one correspondence with second antenna 121, i.e. second antenna
Second electric connection structure 14 is arranged in 121 surfaces far from the glass substrate 10, to ensure second electrical connection
Structure 14 is electrically connected with second antenna 121 one-to-one correspondence.
In step 4), the S4 step and Fig. 5 to Fig. 6 in Fig. 1, the second surface shape of Yu Suoshu glass substrate 10 are please referred to
At plastic packaging layer 15, the plastic packaging layer 15 is by second antenna stack 12 and 14 plastic packaging of the second electric connection structure.
As an example, as an example, can use but be not limited only to molded underfill technique, coining moulding technology, pass
Pass the second table that moulding technology, hydraulic seal plastic package process, vacuum lamination process or spin coating proceeding are equal to the glass substrate 10
Face forms the plastic packaging layer 15；Preferably, in the present embodiment, using molded underfill technique in the of the glass substrate 10
Two surfaces form the plastic packaging layer 15.The plastic packaging layer 15 is formed using molded underfill technique, the plastic packaging layer 15 can be with
It is smooth and promptly fill up the gap between i.e. described second electric connection structure 14 in the gap between second antenna 121, it can
Effectively to avoid the occurrence of interface debonding；And molded underfill technique will not as capillary underfill technique in the prior art that
Sample is restricted, and greatly reduces technology difficulty, be can be used for smaller joint gap, is more suitable for stacked structure.
As an example, the material of the plastic packaging layer 15 may include but be not limited only to polymer-based material, resin-based materials,
Polyimides, silica gel or epoxy resin etc..
As an example, surface of the plastic packaging layer 15 being initially formed far from the glass substrate 10 (is moulded described in Fig. 5
The upper surface of sealing 15) surface (i.e. in Fig. 5 institute of second electric connection structure 14 far from the glass substrate 10 can be higher than
State the top of the second electric connection structure 14), as shown in figure 5, at this point, also needing to execute institute after forming the plastic packaging layer 15
It states plastic packaging layer 15 and carries out thinned technique, specifically, can use but be not limited only to chemical mechanical milling tech to the plastic packaging
Layer 15 carry out it is thinned so that retain the plastic packaging layer 15 upper surface it is equal with the top of second electric connection structure 14
Together, as shown in Figure 6.Certainly, in other examples, the upper surface for the plastic packaging layer 15 being initially formed is electrically connected with described second
The top flush of binding structure 14, as shown in fig. 6, carrying out thinned technique to the plastic packaging layer 15 at this point, can then save.
In step 5), S5 step and Fig. 7 in Fig. 1 are please referred to, Yu Suoshu plastic packaging layer 15 is far from the glass substrate 10
Surface form re-wiring layer 16, the re-wiring layer 16 is electrically connected with second electric connection structure 14.
As an example, the re-wiring layer 16 may include being routed dielectric layer 161 and metallic stacked structure 162, it is described
Wiring dielectric layer 161 is located at surface of the plastic packaging layer 15 far from the glass substrate 10；The metallic stacked structure 162 is located at
In the wiring dielectric layer 161, the metallic stacked structure 162 include Spaced arrangement metal line layer (not shown) and
Metal plug (does not indicate), and the metal plug is between the adjacent metal line layer, by the adjacent metal line layer
Electrical connection.
As an example, the material of the wiring dielectric layer 161 may include low k dielectric.As an example, the wiring
Dielectric layer 161 can using epoxy resin, silica gel, PI (polyimides), PBO (polybenzoxazoles), BCB (benzocyclobutene),
One of silica, phosphorosilicate glass and fluorine-containing glass material, and can be using spin coating, CVD, plasma enhanced CVD etc.
Technique forms the wiring dielectric layer 161.
As an example, the metal line layer may include single metal layer, it also may include two or more layers metal layer.Make
For example, the material of the material of the metal line layer and the metal plug may include copper, aluminium, nickel, gold, silver, one in titanium
Kind material or two or more combined materials.
As an example, the metal line layer is electrically connected with second electric connection structure 14.
In step 6), please refer to S6 step and Fig. 8 in Fig. 1, chip 17 be provided, by 17 back bonding of chip in
Surface of the re-wiring layer 16 far from the plastic packaging layer 15, and the chip 17 is electrically connected with the re-wiring layer 14.
As an example, the chip 17 can be any one functional chip, device could be formed in the chip 17
Structure (not shown), the front of the chip 17 could be formed with connection weld pad (not indicating), the connection weld pad with it is described
Device architecture electrical connection.
As an example, can using any one existing bonding technology by 17 back bonding of chip in it is described again
Surface of the wiring layer 16 far from the re-wiring layer 14；The connection weld pad and the re-wiring layer 14 of the chip 17
In the metal line layer electrical connection.
As an example, further including forming bottom between the chip 17 and the re-wiring layer 16 to fill out after step 6)
The step of filling layer 19；Specifically, ink-jetting process, gluing process, compressing and forming process, transfer modling can be used but be not limited only to
At least one of moulding process, fluid-tight moulding process, vacuum lamination process or spin coating proceeding form the Underfill layer 19；
The material of the Underfill layer 19 at least one of may include but be not limited only to polyimides, silica gel and epoxy resin.
The bond strength of the chip 17 and the re-wiring layer 16 can be enhanced in the Underfill layer 19, and protection is described again
Wiring layer 16.
In step 7), S7 step and Fig. 9 in Fig. 1 are please referred to, Yu Suoshu re-wiring layer 16 is far from the plastic packaging layer
15 surface forms soldered ball convex block 18, and the soldered ball convex block 18 is electrically connected with the re-wiring layer 16.
As an example, the material of the soldered ball convex block 18 may include at least one of copper and tin.
As an example, the soldered ball convex block 18 is electrically connected with the metal line layer.
As an example, in step 6) that several described 17 back bondings of chip are separate described in the re-wiring layer 16
The surface of plastic packaging layer 15, each 17 two sides of chip are each formed with the soldered ball convex block 18；It further include by step after step 7)
7) resulting structures carry out the step of slicing treatment, include one single chip 17 and several described soldered ball convex blocks 18 to obtain several
Semiconductor package.
The preparation method of semiconductor package of the invention is by by the first antenna layer 11 and second antenna
Layer 12 is respectively formed in the glass substrate 10 opposite first surface and second surface, can be reduced significantly semiconductor packages knot
The size and volume of structure improve device integration；The glass substrate 10 is directly as the first antenna layer 11 and described
The bearing substrate of two antenna stacks 12 does not need additional carrier and is packaged transfer, is also not necessarily to carrier stripping technology, significant to simplify
Preparation process, saves the preparation cost.
Embodiment two
Incorporated by reference to Fig. 2 to Fig. 8 refering to Fig. 9, the present invention also provides a kind of semiconductor package, the semiconductor packages knot
Structure includes: glass substrate 10, and the glass substrate 10 includes first surface and the second surface opposite with the first surface；The
One antenna stack 11, the first antenna layer 11 are located at the first surface of the glass substrate 10；Second antenna stack 12, described second
Antenna stack 12 is located at the second surface of the glass substrate 10；First electric connection structure 13, first electric connection structure 13 is certainly
The first surface of the glass substrate 10 extends to the second surface of the glass substrate 10, and first electric connection structure 13
It is electrically connected with the first antenna 11 and second antenna 12；Second electric connection structure 14, second electric connection structure 14
Surface positioned at second antenna stack 12 far from the glass substrate 10；Plastic packaging layer 15, the plastic packaging layer 15 are located at the glass
The second surface of glass substrate 10, and the plastic packaging layer 15 moulds second antenna stack 12 and second electric connection structure 14
Envelope；Re-wiring layer 16, the re-wiring layer 16 is located at surface of the plastic packaging layer 15 far from the glass substrate 10, described
Re-wiring layer 16 is electrically connected with second electric connection structure 14；Chip 17,17 back bonding of chip in it is described again
Surface of the wiring layer 16 far from the plastic packaging layer 15, and the chip 17 is electrically connected with the re-wiring layer 16；Soldered ball convex block
18, the soldered ball convex block 18 is located at surface of the re-wiring layer 16 far from the plastic packaging layer 15, and the soldered ball convex block 18
It is electrically connected with the re-wiring layer 16.
As an example, the glass substrate 10 can be the substrate that any one existing glass is made into, it is preferable that described
Glass substrate 10 may include the unorganic glass such as silicate substrate or pmma substrate etc..
As an example, the thickness of the glass substrate 10 can be set according to actual needs, herein without limitation.
As an example, the first antenna layer 11 may include multiple first antennas 111 being intervally arranged, described second day
Line layer 12 may include multiple the second antennas 121 being intervally arranged, and the quantity of first electric connection structure 13 is multiple；It is described
The quantity of first antenna 111, second antenna 121 and first electric connection structure 13 is identical；The first antenna 111 with
Second antenna 121 is correspondingly arranged up and down one by one, and first electric connection structure 13 is by the first antenna 111 and described the
Two antennas 121 correspond electrical connection.
As an example, the material of the first antenna 111 may include but be not limited only in copper, aluminium, silver, nickel, gold and titanium
At least one；The material of second antenna 121 may include but be not limited only in copper, aluminium, silver, nickel, gold and titanium at least
It is a kind of.
As an example, the quantity of first antenna 111 described in the first antenna layer 11 can carry out according to actual needs
Setting only includes four first antennas 111 using in the first antenna layer 11 herein without limitation, in Fig. 9 as example；
The shape of the first antenna 111 can be blocky, helical form or ring-type etc.；Second day described in second antenna stack 12
The quantity of line 121 can be set according to actual needs, herein without limitation, in Fig. 9 only in second antenna stack 12
Example is used as including four second antennas 121；The shape of second antenna 121 can be blocky, helical form or ring-type
Etc..
As an example, in the first antenna layer 11 in the quantity of the first antenna 111 and second antenna stack 12
The quantity of second antenna 121 is identical, and the first antenna 111 is correspondingly arranged up and down one by one with second antenna 121.
As an example, the first antenna 111 and second antenna 121 may each comprise but be not limited only to oscillator day
Line.
For example, first electric connection structure 13 may include metal wire or metallic conduction post.
As an example, second electric connection structure 14 may include metal wire or metallic conduction post.
As an example, the quantity of second electric connection structure 14 can be set according to actual needs, it is preferable that this
In embodiment, the quantity of the second antenna 121 described in the quantity of second electric connection structure 14 and second antenna stack 12
It is identical, and second electric connection structure 14 is arranged in a one-to-one correspondence with second antenna 121, i.e. second antenna
Second electric connection structure 14 is arranged in 121 surfaces far from the glass substrate 10, to ensure second electrical connection
Structure 14 is electrically connected with second antenna 121 one-to-one correspondence.
As an example, the material of the plastic packaging layer 15 may include but be not limited only to polymer-based material, resin-based materials,
Polyimides, silica gel or epoxy resin etc..
As an example, surface of the plastic packaging layer 15 far from the glass substrate 10 and second electric connection structure 14 are remote
Surface flush from the glass substrate 10.
As an example, the re-wiring layer 16 may include being routed dielectric layer 161 and metallic stacked structure 162, it is described
Wiring dielectric layer 161 is located at surface of the plastic packaging layer 15 far from the glass substrate 10；The metallic stacked structure 162 is located at
In the wiring dielectric layer 161, the metallic stacked structure 162 include Spaced arrangement metal line layer (not shown) and
Metal plug (does not indicate), and the metal plug is between the adjacent metal line layer, by the adjacent metal line layer
Electrical connection.
As an example, the material of the wiring dielectric layer 161 may include low k dielectric.As an example, the wiring
Dielectric layer 161 can using epoxy resin, silica gel, PI (polyimides), PBO (polybenzoxazoles), BCB (benzocyclobutene),
One of silica, phosphorosilicate glass and fluorine-containing glass material, and can be using spin coating, CVD, plasma enhanced CVD etc.
Technique forms the wiring dielectric layer 161.
As an example, the metal line layer may include single metal layer, it also may include two or more layers metal layer.Make
For example, the material of the material of the metal line layer and the metal plug may include copper, aluminium, nickel, gold, silver, one in titanium
Kind material or two or more combined materials.
As an example, the metal line layer is electrically connected with second electric connection structure 14.
As an example, the chip 17 can be any one functional chip, device could be formed in the chip 17
Structure (not shown), the front of the chip 17 could be formed with connection weld pad (not indicating), the connection weld pad with it is described
Device architecture electrical connection；The connection weld pad of the chip 17 is electrically connected with the metal line layer in the re-wiring layer 14
It connects.
As an example, the semiconductor package further includes Underfill layer 19, the Underfill layer 19 is filled in
Between the chip 17 and the re-wiring layer 16.Specifically, can use but be not limited only to ink-jetting process, gluing process,
At least one of compressing and forming process, Transfer molding technique, fluid-tight moulding process, vacuum lamination process or spin coating proceeding
Form the Underfill layer 19；The material of the Underfill layer 19 may include but be not limited only to polyimides, silica gel and
At least one of epoxy resin.The knot of the chip 17 and the re-wiring layer 16 can be enhanced in the Underfill layer 19
Intensity is closed, and protects the re-wiring layer 16.
Semiconductor package of the invention is by distinguishing shape for the first antenna layer 11 and second antenna stack 12
Glass substrate 10 described in Cheng Yu opposite first surface and second surface, can be reduced significantly semiconductor package size and
Volume improves device integration；The glass substrate 10 is directly as the first antenna layer 11 and second antenna stack 12
Bearing substrate, do not need additional carrier and be packaged transfer, also be not necessarily to carrier stripping technology, significantly simplify preparation work
Skill saves the preparation cost.
In conclusion the present invention provides a kind of semiconductor package and preparation method thereof, the semiconductor package
Including glass substrate, the glass substrate includes first surface and the second surface opposite with the first surface；First antenna
Layer, positioned at the first surface of the glass substrate；Second antenna stack, positioned at the second surface of the glass substrate；First is electrically connected
Binding structure, extends to the second surface of the glass substrate from the first surface of the glass substrate, and with the first antenna
Layer and second antenna stack electrical connection；Second electric connection structure, positioned at second antenna stack far from the glass substrate
Surface；Plastic packaging layer, positioned at the second surface of the glass substrate, and by second antenna stack and second electric connection structure
Plastic packaging；Re-wiring layer, positioned at the surface of the plastic packaging layer far from the glass substrate, the re-wiring layer and described second
Electric connection structure electrical connection；Chip, back bonding in surface of the re-wiring layer far from the plastic packaging layer, and with it is described heavy
The electrical connection of new route layer；Soldered ball convex block, the surface positioned at the re-wiring layer far from the plastic packaging layer, and with the cloth again
The electrical connection of line layer.Semiconductor package of the invention is by being respectively arranged at glass base for first antenna layer and the second antenna stack
Plate opposite first surface and second surface can be reduced significantly the size and volume of semiconductor package, improve device collection
Cheng Du；Glass substrate does not need additional carrier and is sealed directly as first antenna layer and the bearing substrate of the second antenna stack
Dress transfer, is also not necessarily to carrier stripping technology, significantly simplifies preparation process, save the preparation cost.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (9)
1. a kind of semiconductor package characterized by comprising
Glass substrate, the glass substrate include first surface and the second surface opposite with the first surface；
First antenna layer, positioned at the first surface of the glass substrate；
Second antenna stack, positioned at the second surface of the glass substrate；
First electric connection structure, extends to the second surface of the glass substrate from the first surface of the glass substrate, and with
The first antenna layer and second antenna stack electrical connection；
Second electric connection structure, positioned at the surface of second antenna stack far from the glass substrate；
Plastic packaging layer, positioned at the second surface of the glass substrate, and by second antenna stack and second electric connection structure
Plastic packaging；
Re-wiring layer, positioned at the surface of the plastic packaging layer far from the glass substrate, the re-wiring layer and described second
Electric connection structure electrical connection；
Chip, back bonding are electrically connected in surface of the re-wiring layer far from the plastic packaging layer, and with the re-wiring layer
It connects；
Soldered ball convex block, the surface positioned at the re-wiring layer far from the plastic packaging layer, and be electrically connected with the re-wiring layer.
2. semiconductor package according to claim 1, it is characterised in that: the first antenna layer includes multiple intervals
The first antenna of arrangement, second antenna stack include multiple the second antennas being intervally arranged, first electric connection structure
Quantity is multiple；The quantity of the first antenna, second antenna and first electric connection structure is identical, and described first day
Line and second antenna are correspondingly arranged up and down one by one, and first electric connection structure was by the first antenna and described second day
Line corresponds electrical connection.
3. semiconductor package according to claim 1, it is characterised in that: first electric connection structure includes metal
Bonding wire or metallic conduction post, second electric connection structure include metal wire or metallic conduction post.
4. semiconductor package according to claim 1, it is characterised in that: the re-wiring layer includes:
It is routed dielectric layer, positioned at the surface of the plastic packaging layer far from the glass substrate；
Metallic stacked structure is located in the wiring dielectric layer, and the metallic stacked structure includes the metal of Spaced arrangement
The adjacent metal line layer is electrically connected by line layer and metal plug, the metal plug between the adjacent metal line layer
It connects.
5. semiconductor package according to any one of claim 1 to 4, it is characterised in that: the semiconductor packages
Structure further includes Underfill layer, and the Underfill layer is filled between the chip and the re-wiring layer.
6. a kind of preparation method of semiconductor package, which comprises the steps of:
Glass substrate is provided, the glass substrate includes first surface and the second surface opposite with the first surface；
In forming the first electric connection structure in the glass substrate, and first antenna is formed in the first surface of the glass substrate
Layer, and the second antenna stack is formed in the second surface of the glass substrate；First electric connection structure is from the glass substrate
First surface extend to the second surface of the glass substrate；The first antenna layer and second antenna stack and described the
The electrical connection of one electric connection structure；
The second electric connection structure is formed far from the surface of the glass substrate in second antenna stack；
Plastic packaging layer is formed in the second surface of the glass substrate, and the plastic packaging layer will second antenna stack and described second electric
Connection structure plastic packaging；
Re-wiring layer, the re-wiring layer and described second are formed far from the surface of the glass substrate in the plastic packaging layer
Electric connection structure electrical connection；
Chip is provided, the flip-chip is bonded to surface of the re-wiring layer far from the plastic packaging layer, and with it is described
Re-wiring layer electrical connection；
Soldered ball convex block, the soldered ball convex block and the cloth again are formed far from the surface of the plastic packaging layer in the re-wiring layer
The electrical connection of line layer.
7. the preparation method of semiconductor package according to claim 6, it is characterised in that: Yu Suoshu glass substrate
First surface forms first antenna layer, and forms the second antenna stack in the second surface of the glass substrate and include the following steps:
First antenna material layer is formed in the first surface of the glass substrate；
Perform etching to the first antenna material layer includes described first day of multiple first antennas being intervally arranged to obtain
Line layer, the first antenna are electrically connected with first electric connection structure one-to-one correspondence；
The second antenna material layer is formed in the second surface of the glass substrate；
Perform etching to the second antenna material layer includes described second day of multiple the second antennas being intervally arranged to obtain
Line layer, second antenna are electrically connected with first electric connection structure one-to-one correspondence.
8. the preparation method of semiconductor package according to claim 6, it is characterised in that: by the flip-chip key
Further include after surface together in the re-wiring layer far from the plastic packaging layer in the chip and the re-wiring layer it
Between formed Underfill layer the step of.
9. the preparation method of the semiconductor package according to any one of claim 6 to 8, it is characterised in that: if will
The dry flip-chip is bonded to surface of the re-wiring layer far from the plastic packaging layer, and each chip two sides are respectively formed
There is the soldered ball convex block；Further include after the re-wiring layer forms the soldered ball convex block far from the surface of the plastic packaging layer
The step of resulting structures are carried out slicing treatment includes one single chip and the half of several soldered ball convex blocks to obtain several
Conductor package structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910477411.2A CN110120385A (en) | 2019-06-03 | 2019-06-03 | Semiconductor package and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910477411.2A CN110120385A (en) | 2019-06-03 | 2019-06-03 | Semiconductor package and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110120385A true CN110120385A (en) | 2019-08-13 |
Family
ID=67523616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910477411.2A Pending CN110120385A (en) | 2019-06-03 | 2019-06-03 | Semiconductor package and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110120385A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110620106A (en) * | 2019-08-22 | 2019-12-27 | 上海先方半导体有限公司 | Wafer-level antenna packaging structure and preparation method |
| CN112701444A (en) * | 2019-10-22 | 2021-04-23 | 华为技术有限公司 | Antenna, antenna packaging method and terminal |
| CN112993525A (en) * | 2021-02-03 | 2021-06-18 | 维沃移动通信有限公司 | Display device and electronic apparatus |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018004684A1 (en) * | 2016-07-01 | 2018-01-04 | Intel Corporation | Semiconductor packages with antennas |
| CN107706521A (en) * | 2017-10-25 | 2018-02-16 | 中芯长电半导体（江阴）有限公司 | Fan-out-type antenna packages structure and preparation method thereof |
| CN108511400A (en) * | 2018-03-16 | 2018-09-07 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and packaging method of antenna |
| CN209691748U (en) * | 2019-06-03 | 2019-11-26 | 中芯长电半导体（江阴）有限公司 | Semiconductor package |
-
2019
- 2019-06-03 CN CN201910477411.2A patent/CN110120385A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018004684A1 (en) * | 2016-07-01 | 2018-01-04 | Intel Corporation | Semiconductor packages with antennas |
| CN107706521A (en) * | 2017-10-25 | 2018-02-16 | 中芯长电半导体（江阴）有限公司 | Fan-out-type antenna packages structure and preparation method thereof |
| CN108511400A (en) * | 2018-03-16 | 2018-09-07 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and packaging method of antenna |
| CN209691748U (en) * | 2019-06-03 | 2019-11-26 | 中芯长电半导体（江阴）有限公司 | Semiconductor package |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110620106A (en) * | 2019-08-22 | 2019-12-27 | 上海先方半导体有限公司 | Wafer-level antenna packaging structure and preparation method |
| CN110620106B (en) * | 2019-08-22 | 2021-04-13 | 上海先方半导体有限公司 | Wafer-level antenna packaging structure and preparation method |
| CN112701444A (en) * | 2019-10-22 | 2021-04-23 | 华为技术有限公司 | Antenna, antenna packaging method and terminal |
| WO2021078038A1 (en) * | 2019-10-22 | 2021-04-29 | 华为技术有限公司 | Antenna, antenna encapsulating method and terminal |
| CN112701444B (en) * | 2019-10-22 | 2022-06-28 | 华为技术有限公司 | Antenna, antenna packaging method and terminal |
| CN112993525A (en) * | 2021-02-03 | 2021-06-18 | 维沃移动通信有限公司 | Display device and electronic apparatus |
| CN112993525B (en) * | 2021-02-03 | 2024-03-19 | 维沃移动通信有限公司 | Display device and electronic apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105225965B (en) | A kind of fan-out package structure and preparation method thereof | |
| CN110277356A (en) | The encapsulating structure and packaging method of antenna feeder | |
| CN110085575A (en) | Semiconductor package and preparation method thereof | |
| CN207852653U (en) | Semiconductor package with antenna module | |
| CN108305856A (en) | The encapsulating structure and packaging method of antenna | |
| CN110120385A (en) | Semiconductor package and preparation method thereof | |
| CN108417982A (en) | The encapsulating structure and packaging method of antenna | |
| CN109742056A (en) | The encapsulating structure and packaging method of antenna | |
| CN109768031A (en) | The encapsulating structure and packaging method of antenna | |
| CN108336494A (en) | The encapsulating structure and packaging method of antenna | |
| CN207938809U (en) | The encapsulating structure of antenna | |
| CN110047820A (en) | Antenna packages structure and packaging method with air chamber | |
| CN107195625A (en) | Two-sided system-level laminated packaging structure of plastic packaging fan-out-type and preparation method thereof | |
| CN109473765A (en) | Three-dimension packaging antenna and its packaging method | |
| CN209691748U (en) | Semiconductor package | |
| CN209328893U (en) | The encapsulating structure of antenna | |
| CN209804651U (en) | Semiconductor packaging structure | |
| CN110085973A (en) | Antenna packages structure and packaging method | |
| CN209328892U (en) | The encapsulating structure of antenna | |
| CN109841599A (en) | A kind of encapsulating structure and packaging method | |
| CN208835263U (en) | The encapsulating structure of antenna | |
| CN206931602U (en) | The two-sided system-level laminated packaging structure of plastic packaging fan-out-type | |
| CN110429068A (en) | A kind of antenna packages structure and preparation method thereof, communication equipment | |
| CN209641654U (en) | Antenna packages structure | |
| CN209641820U (en) | Antenna packages structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Applicant after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Applicant before: SJ Semiconductor (Jiangyin) Corp. |
|
| CB02 | Change of applicant information |