CN209691748U

CN209691748U - Semiconductor package

Info

Publication number: CN209691748U
Application number: CN201920824530.6U
Authority: CN
Inventors: 陈彦亨; 林正忠; 吴政达
Original assignee: Zhongxin Changdian Semiconductor (jiangyin) Co Ltd
Current assignee: SJ Semiconductor Jiangyin Corp
Priority date: 2019-06-03
Filing date: 2019-06-03
Publication date: 2019-11-26
Anticipated expiration: 2029-06-03

Abstract

The utility model provides a kind of semiconductor package, and semiconductor package includes: glass substrate；First antenna layer, positioned at the first surface of glass substrate；Second antenna stack, positioned at the second surface of glass substrate；First electric connection structure extends to second surface from the first surface of glass substrate；Second electric connection structure, the surface positioned at the second antenna stack far from glass substrate；Plastic packaging layer, positioned at the second surface of glass substrate；Re-wiring layer, the surface positioned at plastic packaging layer far from glass substrate；Chip, back bonding is in surface of the re-wiring layer far from plastic packaging layer；Soldered ball convex block, the surface positioned at re-wiring layer far from plastic packaging layer, and be electrically connected with re-wiring layer.The semiconductor package of the utility model can be reduced significantly the size and volume of semiconductor package, improve device integration；It does not need additional carrier and is packaged transfer, significantly simplify preparation process, save the preparation cost.

Description

Semiconductor package

Technical field

The utility model belongs to field of semiconductor package, more particularly to a kind of semiconductor package.

Background technique

With the development of economy with the progress of science and technology, various high-tech electronic products emerge one after another, greatly convenient and rich Rich people's lives, among these with the hair for the various portable mobile communication terminals that mobile phone and tablet computer (PAD) are representative It opens up especially noticeable.

Existing portable mobile communication terminal is usually built-in with antenna structure for communication function, for example, realize voice and Video connects and surfs the web.The common method of built-in antenna is that antenna is directly made in the surface of circuit board at present, But this method causes the conformability of device poor because antenna need to occupy additional board area, constrains mobile communication terminal Miniaturise.Simultaneously as electronic circuit is relatively more on circuit board, there are electromagnetic interferences between antenna and All other routes The problems such as, or even there is also the risks that antenna and other metallic circuits are shorted.

Although having occurred the technology for encapsulating antenna and chip together in encapsulation field, need in encapsulation process by load Body carries out transfer encapsulation, needs carrier carrying out removing removal, complex process and higher cost after transfer encapsulation.In addition, existing Antenna packages be mostly single layer structure, size is larger, and conformability is lower, and antenna efficiency is lower, has been insufficient for antenna The increasing demand of performance.

Utility model content

In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of semiconductor packages knots Structure, for solve antenna packages structural integration is lower in the prior art, size is larger, preparation process is complicated and preparation cost compared with The problems such as high.

In order to achieve the above objects and other related objects, the utility model provides a kind of semiconductor package, and described half Conductor package structure includes:

Glass substrate, the glass substrate include first surface and the second surface opposite with the first surface；

First antenna layer, positioned at the first surface of the glass substrate；

Second antenna stack, positioned at the second surface of the glass substrate；

First electric connection structure extends to the second surface of the glass substrate from the first surface of the glass substrate, And it is electrically connected with the first antenna layer and second antenna stack；

Second electric connection structure, positioned at the surface of second antenna stack far from the glass substrate；

Plastic packaging layer is electrically connected positioned at the second surface of the glass substrate, and by second antenna stack and described second Structure plastic packaging；

Re-wiring layer, positioned at the surface of the plastic packaging layer far from the glass substrate, the re-wiring layer with it is described The electrical connection of second electric connection structure；

Chip, back bonding in surface of the re-wiring layer far from the plastic packaging layer, and with the re-wiring layer Electrical connection；

Soldered ball convex block, the surface positioned at the re-wiring layer far from the plastic packaging layer, and it is electric with the re-wiring layer Connection.

Optionally, the first antenna layer includes multiple first antennas being intervally arranged, and second antenna stack includes more A the second antenna being intervally arranged, the quantity of first electric connection structure are multiple；The first antenna, second antenna And the quantity of first electric connection structure is identical, the first antenna is correspondingly arranged up and down one by one with second antenna, institute It states the first electric connection structure and is electrically connected the first antenna with second antenna one-to-one correspondence.

Optionally, first electric connection structure includes metal wire or metallic conduction post, second electric connection structure Including metal wire or metallic conduction post.

Optionally, the re-wiring layer includes:

It is routed dielectric layer, positioned at the surface of the plastic packaging layer far from the glass substrate；

Metallic stacked structure is located in the wiring dielectric layer, and the metallic stacked structure includes what Spaced was arranged Metal line layer and metal plug, the metal plug is between the adjacent metal line layer, by the adjacent metal line layer Electrical connection.

Optionally, the semiconductor package further includes Underfill layer, and the Underfill layer is filled in the core Between piece and the re-wiring layer.

The utility model also provides a kind of preparation method of semiconductor package, the preparation of the semiconductor package Method comprising steps of

Glass substrate is provided, the glass substrate includes first surface and the second surface opposite with the first surface；

In forming the first electric connection structure in the glass substrate, and first is formed in the first surface of the glass substrate Antenna stack, and the second antenna stack is formed in the second surface of the glass substrate；First electric connection structure is from the glass The first surface of substrate extends to the second surface of the glass substrate；The first antenna layer and second antenna stack and institute State the electrical connection of the first electric connection structure；

The second electric connection structure is formed far from the surface of the glass substrate in second antenna stack；

Plastic packaging layer is formed in the second surface of the glass substrate, and the plastic packaging layer is by second antenna stack and described the Two electric connection structure plastic packagings；

In the plastic packaging layer far from the glass substrate surface formed re-wiring layer, the re-wiring layer with it is described The electrical connection of second electric connection structure；

Chip is provided, the flip-chip is bonded to surface of the re-wiring layer far from the plastic packaging layer, and with The re-wiring layer electrical connection；

In the re-wiring layer far from the plastic packaging layer surface formed soldered ball convex block, the soldered ball convex block with it is described heavy The electrical connection of new route layer.

Optionally, the first surface of Yu Suoshu glass substrate forms first antenna layer, and in the second of the glass substrate Surface forms the second antenna stack and includes the following steps:

First antenna material layer is formed in the first surface of the glass substrate；

Perform etching to the first antenna material layer includes described the of multiple first antennas being intervally arranged to obtain One antenna stack, the first antenna are electrically connected with first electric connection structure one-to-one correspondence；

The second antenna material layer is formed in the second surface of the glass substrate；

Perform etching to the second antenna material layer includes described the of multiple the second antennas being intervally arranged to obtain Two antenna stacks, second antenna are electrically connected with first electric connection structure one-to-one correspondence.

Optionally, the flip-chip is bonded to after surface of the re-wiring layer far from the plastic packaging layer and is also wrapped Include the step of Underfill layer is formed between the chip and the re-wiring layer.

Optionally, several described flip-chips are bonded to surface of the re-wiring layer far from the plastic packaging layer, Each chip two sides are each formed with the soldered ball convex block；Institute is formed far from the surface of the plastic packaging layer in the re-wiring layer State and further include the steps that after soldered ball convex block resulting structures carrying out slicing treatment, if with obtain several include one single chip and The semiconductor package of the dry soldered ball convex block.

As described above, the semiconductor package of the utility model has the following beneficial effects: partly leading for the utility model Body encapsulating structure is by being respectively arranged at the opposite first surface of glass substrate and second for first antenna layer and the second antenna stack Surface can be reduced significantly the size and volume of semiconductor package, improve device integration；Glass substrate is directly as The bearing substrate of one antenna stack and the second antenna stack does not need additional carrier and is packaged transfer, also removes work without carrier Skill significantly simplifies preparation process, saves the preparation cost.

Detailed description of the invention

Fig. 1 is shown as the flow chart of the preparation method of the semiconductor package provided in the utility model embodiment one.

Fig. 2 to Fig. 9 is shown as in the preparation method of the semiconductor package provided in the utility model embodiment one each The cross section structure schematic diagram of step resulting structures；Wherein, Fig. 9 is also the semiconductor packages provided in the utility model embodiment two The cross section structure schematic diagram of structure.

Component label instructions

10 glass substrates

11 first antenna layers

111 first antennas

12 second antenna stacks

121 second antennas

13 first electric connection structures

14 second electric connection structures

15 plastic packaging layers

16 re-wiring layers

161 wiring dielectric layers

162 metallic stacked structures

17 chips

18 soldered ball convex blocks

19 Underfill layers

Specific embodiment

Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer With carrying out various modifications or alterations under the spirit without departing from the utility model.

Please refer to FIG. 1 to FIG. 9.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of utility model is only shown with related component in the utility model rather than when according to actual implementation in diagram then Component count, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind Become, and its assembly layout kenel may also be increasingly complex.

Embodiment one

Referring to Fig. 1, the utility model provides a kind of preparation method of semiconductor package, the semiconductor packages knot The preparation method of structure includes the following steps:

1) glass substrate is provided, the glass substrate includes first surface and second table opposite with the first surface Face；

2) it forms the first electric connection structure in Yu Suoshu glass substrate, and forms the in the first surface of the glass substrate One antenna stack, and the second antenna stack is formed in the second surface of the glass substrate；First electric connection structure is from the glass The first surface of glass substrate extends to the second surface of the glass substrate；The first antenna layer and second antenna stack with The first electric connection structure electrical connection；

3) the second antenna stack of Yu Suoshu forms the second electric connection structure far from the surface of the glass substrate；

4) second surface of Yu Suoshu glass substrate forms plastic packaging layer, and the plastic packaging layer is by second antenna stack and described Second electric connection structure plastic packaging；

5) Yu Suoshu plastic packaging layer forms re-wiring layer, the re-wiring layer and institute far from the surface of the glass substrate State the electrical connection of the second electric connection structure；

6) chip is provided, the flip-chip is bonded to surface of the re-wiring layer far from the plastic packaging layer, and It is electrically connected with the re-wiring layer；

7) Yu Suoshu re-wiring layer far from the plastic packaging layer surface formed soldered ball convex block, the soldered ball convex block with it is described Re-wiring layer electrical connection.

In step 1), S1 step and Fig. 2 in Fig. 1 are please referred to, glass substrate 10 is provided, the glass substrate 10 includes First surface (for example, the lower surface of the glass substrate 10 in Fig. 2) and the second surface (example opposite with the first surface Such as, the upper surface of the glass substrate 10 in Fig. 2).

As an example, the glass substrate 10 can be the substrate that any one existing glass is made into, it is preferable that described Glass substrate 10 may include the unorganic glass such as silicate substrate or pmma substrate etc..

As an example, the thickness of the glass substrate 10 can be set according to actual needs, herein without limitation.

In step 2), S2 step and Fig. 3 in Fig. 1 are please referred to, forms the first electrical connection in Yu Suoshu glass substrate 10 Structure 13, and first antenna layer 11 is formed in the first surface of the glass substrate 10, and in the second of the glass substrate 10 Surface forms the second antenna stack 12；The first surface of first electric connection structure 13 from the glass substrate 10 extends to described The second surface of glass substrate 10；The first antenna layer 11 and second antenna stack 12 and first electric connection structure 13 Electrical connection.

As an example, step 2) may include steps of:

2-1) form through-hole (not shown) in Yu Suoshu glass substrate 10, the through-hole from the glass substrate 10 first Surface extends to the second surface of the glass substrate 10；In forming the first electric connection structure 13 in the through-hole；The through-hole And the quantity of first electric connection structure 13 can be set according to actual needs, it is preferable that described logical in the present embodiment The quantity and second antenna of the quantity of hole and first electric connection structure 13 and the first antenna 111 being subsequently formed 121 quantity is identical, only includes four first antennas 111 using in the first antenna layer 11 in Fig. 3 as example；

2-2) first surface of Yu Suoshu glass substrate 10 forms first antenna material layer (not indicating)；Specifically, can To form the first antenna using sputtering technology, electroplating technology, physical gas-phase deposition or chemical vapor deposition process etc. Material layer；

2-3) perform etching to the first antenna material layer includes multiple first antennas 111 being intervally arranged to obtain The first antenna layer 11；Specifically, lithographic etch process can be used to perform etching to obtain the first antenna material layer To the first antenna layer 11；The quantity of first antenna 111 described in the first antenna layer 11 can according to actual needs into Row setting only includes four first antennas 111 using in the first antenna layer 11 herein without limitation, in Fig. 3 as showing Example；The shape of the first antenna 111 can be blocky, helical form or ring-type etc.；The first antenna 111 and described first Electric connection structure 13 corresponds electrical connection；

2-4) second surface of Yu Suoshu glass substrate 10 forms the second antenna material layer (not indicating)；Specifically, can To form second antenna using sputtering technology, electroplating technology, physical gas-phase deposition or chemical vapor deposition process etc. Material layer；

2-5) performing etching to the second antenna material layer includes multiple the second antennas 121 being intervally arranged to obtain Second antenna stack 12；Specifically, lithographic etch process can be used to perform etching to obtain the second antenna material layer To second antenna stack 12；The quantity of second antenna 121 described in second antenna stack 12 can according to actual needs into Row setting only includes four second antennas 121 using in second antenna stack 12 herein without limitation, in Fig. 3 as showing Example；The shape of second antenna 121 can be blocky, helical form or ring-type etc.；Second antenna 121 and described first Electric connection structure 13 corresponds electrical connection.

In other examples, it can also be initially formed the first antenna layer 11, then in the glass substrate 10 Form first connection structure 13；Finally re-form second antenna stack 12.

In other examples, the method for forming the first antenna layer 11 and second antenna stack 12 may be: first First, while in the first surface of the glass substrate 10 and second surface the first antenna material layer and described the are respectively formed Then two antenna material layers again respectively perform etching to obtain the first antenna material layer and the second antenna material layer The first antenna layer 11 and second antenna stack 12.

As an example, the material of the first antenna 111 may include but be not limited only in copper, aluminium, silver, nickel, gold and titanium At least one；The material of second antenna 121 may include but be not limited only in copper, aluminium, silver, nickel, gold and titanium at least It is a kind of.

As an example, in the first antenna layer 11 in the quantity of the first antenna 111 and second antenna stack 12 The quantity of second antenna 121 is identical, and the first antenna 111 is correspondingly arranged up and down one by one with second antenna 121.

As an example, the first antenna 111 and second antenna 121 may each comprise but be not limited only to oscillator day Line.

As an example, first electric connection structure 13 may include metal wire or metallic conduction post.

In step 3), S3 step and Fig. 4 in Fig. 1 are please referred to, the second antenna stack of Yu Suoshu 12 is far from the glass base The surface of plate 10 forms the second electric connection structure 14.

As an example, can use routing technique or column bonding technology in second antenna stack 12 far from the glass base The surface of plate 10 forms second electric connection structure 14；Second electric connection structure 14 may include metal wire or metal Conductive column.

As an example, the quantity of second electric connection structure 14 can be set according to actual needs, it is preferable that this In embodiment, the quantity of the second antenna 121 described in the quantity of second electric connection structure 14 and second antenna stack 12 It is identical, and second electric connection structure 14 is arranged in a one-to-one correspondence with second antenna 121, i.e. second antenna Second electric connection structure 14 is arranged in 121 surfaces far from the glass substrate 10, to ensure second electrical connection Structure 14 is electrically connected with second antenna 121 one-to-one correspondence.

In step 4), the S4 step and Fig. 5 to Fig. 6 in Fig. 1, the second surface shape of Yu Suoshu glass substrate 10 are please referred to At plastic packaging layer 15, the plastic packaging layer 15 is by second antenna stack 12 and 14 plastic packaging of the second electric connection structure.

As an example, as an example, can use but be not limited only to molded underfill technique, coining moulding technology, pass Pass the second table that moulding technology, hydraulic seal plastic package process, vacuum lamination process or spin coating proceeding are equal to the glass substrate 10 Face forms the plastic packaging layer 15；Preferably, in the present embodiment, using molded underfill technique in the of the glass substrate 10 Two surfaces form the plastic packaging layer 15.The plastic packaging layer 15 is formed using molded underfill technique, the plastic packaging layer 15 can be with It is smooth and promptly fill up the gap between i.e. described second electric connection structure 14 in the gap between second antenna 121, it can Effectively to avoid the occurrence of interface debonding；And molded underfill technique will not as capillary underfill technique in the prior art that Sample is restricted, and greatly reduces technology difficulty, be can be used for smaller joint gap, is more suitable for stacked structure.

As an example, the material of the plastic packaging layer 15 may include but be not limited only to polymer-based material, resin-based materials, Polyimides, silica gel or epoxy resin etc..

As an example, surface of the plastic packaging layer 15 being initially formed far from the glass substrate 10 (is moulded described in Fig. 5 The upper surface of sealing 15) surface (i.e. in Fig. 5 institute of second electric connection structure 14 far from the glass substrate 10 can be higher than State the top of the second electric connection structure 14), as shown in figure 5, at this point, also needing to execute institute after forming the plastic packaging layer 15 It states plastic packaging layer 15 and carries out thinned technique, specifically, can use but be not limited only to chemical mechanical milling tech to the plastic packaging Layer 15 carry out it is thinned so that retain the plastic packaging layer 15 upper surface it is equal with the top of second electric connection structure 14 Together, as shown in Figure 6.Certainly, in other examples, the upper surface for the plastic packaging layer 15 being initially formed is electrically connected with described second The top flush of binding structure 14, as shown in fig. 6, carrying out thinned technique to the plastic packaging layer 15 at this point, can then save.

In step 5), S5 step and Fig. 7 in Fig. 1 are please referred to, Yu Suoshu plastic packaging layer 15 is far from the glass substrate 10 Surface form re-wiring layer 16, the re-wiring layer 16 is electrically connected with second electric connection structure 14.

As an example, the re-wiring layer 16 may include being routed dielectric layer 161 and metallic stacked structure 162, it is described Wiring dielectric layer 161 is located at surface of the plastic packaging layer 15 far from the glass substrate 10；The metallic stacked structure 162 is located at In the wiring dielectric layer 161, the metallic stacked structure 162 include Spaced arrangement metal line layer (not shown) and Metal plug (does not indicate), and the metal plug is between the adjacent metal line layer, by the adjacent metal line layer Electrical connection.

As an example, the material of the wiring dielectric layer 161 may include low k dielectric.As an example, the wiring Dielectric layer 161 can using epoxy resin, silica gel, PI (polyimides), PBO (polybenzoxazoles), BCB (benzocyclobutene), One of silica, phosphorosilicate glass and fluorine-containing glass material, and can be using spin coating, CVD, plasma enhanced CVD etc. Technique forms the wiring dielectric layer 161.

As an example, the metal line layer may include single metal layer, it also may include two or more layers metal layer.Make For example, the material of the material of the metal line layer and the metal plug may include copper, aluminium, nickel, gold, silver, one in titanium Kind material or two or more combined materials.

As an example, the metal line layer is electrically connected with second electric connection structure 14.

In step 6), please refer to S6 step and Fig. 8 in Fig. 1, chip 17 be provided, by 17 back bonding of chip in Surface of the re-wiring layer 16 far from the plastic packaging layer 15, and the chip 17 is electrically connected with the re-wiring layer 14.

As an example, the chip 17 can be any one functional chip, device could be formed in the chip 17 Structure (not shown), the front of the chip 17 could be formed with connection weld pad (not indicating), the connection weld pad with it is described Device architecture electrical connection.

As an example, can using any one existing bonding technology by 17 back bonding of chip in it is described again Surface of the wiring layer 16 far from the re-wiring layer 14；The connection weld pad and the re-wiring layer 14 of the chip 17 In the metal line layer electrical connection.

As an example, further including forming bottom between the chip 17 and the re-wiring layer 16 to fill out after step 6) The step of filling layer 19；Specifically, ink-jetting process, gluing process, compressing and forming process, transfer modling can be used but be not limited only to At least one of moulding process, fluid-tight moulding process, vacuum lamination process or spin coating proceeding form the Underfill layer 19； The material of the Underfill layer 19 at least one of may include but be not limited only to polyimides, silica gel and epoxy resin. The bond strength of the chip 17 and the re-wiring layer 16 can be enhanced in the Underfill layer 19, and protection is described again Wiring layer 16.

In step 7), S7 step and Fig. 9 in Fig. 1 are please referred to, Yu Suoshu re-wiring layer 16 is far from the plastic packaging layer 15 surface forms soldered ball convex block 18, and the soldered ball convex block 18 is electrically connected with the re-wiring layer 16.

As an example, the material of the soldered ball convex block 18 may include at least one of copper and tin.

As an example, the soldered ball convex block 18 is electrically connected with the metal line layer.

As an example, in step 6) that several described 17 back bondings of chip are separate described in the re-wiring layer 16 The surface of plastic packaging layer 15, each 17 two sides of chip are each formed with the soldered ball convex block 18；It further include by step after step 7) 7) resulting structures carry out the step of slicing treatment, include one single chip 17 and several described soldered ball convex blocks 18 to obtain several Semiconductor package.

The preparation method of the semiconductor package of the utility model is by by the first antenna layer 11 and described second Antenna stack 12 is respectively formed in the opposite first surface and second surface of the glass substrate 10, can be reduced significantly semiconductor package The size and volume of assembling structure improve device integration；The glass substrate 10 is directly as the first antenna layer 11 and institute The bearing substrate for stating the second antenna stack 12 does not need additional carrier and is packaged transfer, is also not necessarily to carrier stripping technology, significantly Preparation process is simplified, is saved the preparation cost.

Embodiment two

Incorporated by reference to Fig. 2 to Fig. 8 refering to Fig. 9, the utility model also provides a kind of semiconductor package, the semiconductor package Assembling structure includes: glass substrate 10, and the glass substrate 10 includes first surface and second table opposite with the first surface Face；First antenna layer 11, the first antenna layer 11 are located at the first surface of the glass substrate 10；Second antenna stack 12, institute State the second surface that the second antenna stack 12 is located at the glass substrate 10；First electric connection structure 13, described first is electrically connected binding The first surface of structure 13 from the glass substrate 10 extends to the second surface of the glass substrate 10, and first electrical connection Structure 13 is electrically connected with the first antenna 11 and second antenna 12；Second electric connection structure 14, second electrical connection Structure 14 is located at surface of second antenna stack 12 far from the glass substrate 10；Plastic packaging layer 15, the plastic packaging layer 15 are located at The second surface of the glass substrate 10, and the plastic packaging layer 15 is by second antenna stack 12 and second electric connection structure 14 plastic packagings；Re-wiring layer 16, the re-wiring layer 16 are located at surface of the plastic packaging layer 15 far from the glass substrate 10, The re-wiring layer 16 is electrically connected with second electric connection structure 14；Chip 17,17 back bonding of chip is in described Surface of the re-wiring layer 16 far from the plastic packaging layer 15, and the chip 17 is electrically connected with the re-wiring layer 16；Soldered ball Convex block 18, the soldered ball convex block 18 is located at surface of the re-wiring layer 16 far from the plastic packaging layer 15, and the soldered ball is convex Block 18 is electrically connected with the re-wiring layer 16.

As an example, the first antenna layer 11 may include multiple first antennas 111 being intervally arranged, described second day Line layer 12 may include multiple the second antennas 121 being intervally arranged, and the quantity of first electric connection structure 13 is multiple；It is described The quantity of first antenna 111, second antenna 121 and first electric connection structure 13 is identical；The first antenna 111 with Second antenna 121 is correspondingly arranged up and down one by one, and first electric connection structure 13 is by the first antenna 111 and described the Two antennas 121 correspond electrical connection.

As an example, the quantity of first antenna 111 described in the first antenna layer 11 can carry out according to actual needs Setting only includes four first antennas 111 using in the first antenna layer 11 herein without limitation, in Fig. 9 as example； The shape of the first antenna 111 can be blocky, helical form or ring-type etc.；Second day described in second antenna stack 12 The quantity of line 121 can be set according to actual needs, herein without limitation, in Fig. 9 only in second antenna stack 12 Example is used as including four second antennas 121；The shape of second antenna 121 can be blocky, helical form or ring-type Etc..

As an example, second electric connection structure 14 may include metal wire or metallic conduction post.

As an example, surface of the plastic packaging layer 15 far from the glass substrate 10 and second electric connection structure 14 are remote Surface flush from the glass substrate 10.

As an example, the chip 17 can be any one functional chip, device could be formed in the chip 17 Structure (not shown), the front of the chip 17 could be formed with connection weld pad (not indicating), the connection weld pad with it is described Device architecture electrical connection；The connection weld pad of the chip 17 is electrically connected with the metal line layer in the re-wiring layer 14 It connects.

As an example, the semiconductor package further includes Underfill layer 19, the Underfill layer 19 is filled in Between the chip 17 and the re-wiring layer 16.Specifically, can use but be not limited only to ink-jetting process, gluing process, At least one of compressing and forming process, Transfer molding technique, fluid-tight moulding process, vacuum lamination process or spin coating proceeding Form the Underfill layer 19；The material of the Underfill layer 19 may include but be not limited only to polyimides, silica gel and At least one of epoxy resin.The knot of the chip 17 and the re-wiring layer 16 can be enhanced in the Underfill layer 19 Intensity is closed, and protects the re-wiring layer 16.

The semiconductor package of the utility model is by dividing the first antenna layer 11 and second antenna stack 12 It is not formed in the glass substrate 10 opposite first surface and second surface, the ruler of semiconductor package can be reduced significantly Very little and volume improves device integration；The glass substrate 10 is directly as the first antenna layer 11 and second antenna The bearing substrate of layer 12, does not need additional carrier and is packaged transfer, is also not necessarily to carrier stripping technology, significantly simplifies preparation Technique saves the preparation cost.

In conclusion the utility model provides a kind of semiconductor package, the semiconductor package includes glass Substrate, the glass substrate include first surface and the second surface opposite with the first surface；First antenna layer is located at institute State the first surface of glass substrate；Second antenna stack, positioned at the second surface of the glass substrate；First electric connection structure, from The first surface of the glass substrate extends to the second surface of the glass substrate, and with the first antenna layer and described The electrical connection of two antenna stacks；Second electric connection structure, positioned at the surface of second antenna stack far from the glass substrate；Plastic packaging Layer, positioned at the second surface of the glass substrate, and by second antenna stack and the second electric connection structure plastic packaging；Again Wiring layer, positioned at the surface of the plastic packaging layer far from the glass substrate, the re-wiring layer is electrically connected binding with described second Structure electrical connection；Chip, back bonding in surface of the re-wiring layer far from the plastic packaging layer, and with the re-wiring layer Electrical connection；Soldered ball convex block, the surface positioned at the re-wiring layer far from the plastic packaging layer, and be electrically connected with the re-wiring layer It connects.The semiconductor package of the utility model is by being respectively arranged at glass substrate phase for first antenna layer and the second antenna stack Pair first surface and second surface, can be reduced significantly the size and volume of semiconductor package, improve device integration； Glass substrate does not need additional carrier and is packaged to turn directly as first antenna layer and the bearing substrate of the second antenna stack It moves, is also not necessarily to carrier stripping technology, significantly simplifies preparation process, save the preparation cost.

The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.

Claims

1. a kind of semiconductor package characterized by comprising

First antenna layer, positioned at the first surface of the glass substrate；

First electric connection structure, extends to the second surface of the glass substrate from the first surface of the glass substrate, and with The first antenna layer and second antenna stack electrical connection；

Plastic packaging layer, positioned at the second surface of the glass substrate, and by second antenna stack and second electric connection structure Plastic packaging；

Re-wiring layer, positioned at the surface of the plastic packaging layer far from the glass substrate, the re-wiring layer and described second Electric connection structure electrical connection；

Chip, back bonding are electrically connected in surface of the re-wiring layer far from the plastic packaging layer, and with the re-wiring layer It connects；

Soldered ball convex block, the surface positioned at the re-wiring layer far from the plastic packaging layer, and be electrically connected with the re-wiring layer.

2. semiconductor package according to claim 1, it is characterised in that: the first antenna layer includes multiple intervals The first antenna of arrangement, second antenna stack include multiple the second antennas being intervally arranged, first electric connection structure Quantity is multiple；The quantity of the first antenna, second antenna and first electric connection structure is identical, and described first day Line and second antenna are correspondingly arranged up and down one by one, and first electric connection structure was by the first antenna and described second day Line corresponds electrical connection.

3. semiconductor package according to claim 1, it is characterised in that: first electric connection structure includes metal Bonding wire or metallic conduction post, second electric connection structure include metal wire or metallic conduction post.

4. semiconductor package according to claim 1, it is characterised in that: the re-wiring layer includes:

Metallic stacked structure is located in the wiring dielectric layer, and the metallic stacked structure includes the metal of Spaced arrangement The adjacent metal line layer is electrically connected by line layer and metal plug, the metal plug between the adjacent metal line layer It connects.

5. semiconductor package according to any one of claim 1 to 4, it is characterised in that: the semiconductor packages Structure further includes Underfill layer, and the Underfill layer is filled between the chip and the re-wiring layer.