CN113764359A - Electronic package and manufacturing method thereof - Google Patents

Electronic package and manufacturing method thereof Download PDF

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Publication number
CN113764359A
CN113764359A CN202010534710.8A CN202010534710A CN113764359A CN 113764359 A CN113764359 A CN 113764359A CN 202010534710 A CN202010534710 A CN 202010534710A CN 113764359 A CN113764359 A CN 113764359A
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CN
China
Prior art keywords
electronic
layer
package
encapsulation layer
bearing structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010534710.8A
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Chinese (zh)
Inventor
苏品境
王隆源
王愉博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN113764359A publication Critical patent/CN113764359A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

An electronic package and its manufacturing method, through laying the clad on the electronic element first, adhere this clad on bearing the weight of the structure, make this clad can not creep to the side of this electronic element because of capillary action, therefore when grinding a encapsulated layer used for cladding this electronic element and this clad subsequently, the inside of this electronic element can disperse the stress that receives, avoid this electronic element to take place the cracked problem because of stress concentration.

Description

Electronic package and manufacturing method thereof
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a flip chip type electronic package and a method for fabricating the same.
Background
With the rapid development of the electronic industry, electronic products are also gradually moving toward multi-function and high-performance. At present, there are many technologies applied in the field of Chip packaging, such as flip Chip Package modules, such as Chip Scale Package (CSP), Direct Chip Attached Package (DCA), or Multi-Chip Module Package (MCM), or three-dimensional stacking and integrating chips into a three-dimensional integrated circuit (3D IC) Chip stacking Module.
Fig. 1 is a cross-sectional view of a conventional 3D IC type semiconductor package 1. First, a Silicon interposer (TSI) 10 having a Through-Silicon via (TSV) 10 and a die side 10b opposite to the TSI 10 is provided, the TSI 10 has a plurality of TSV (Through-Silicon vias) 100 connecting the die side 10b and the TSI 10a, a circuit structure 101 is formed on the TSI 10b for mounting a plurality of semiconductor devices 11 having a plurality of solder bumps 12, the plurality of solder bumps 12 are covered with an underfill 13, an encapsulation layer 14 is formed to cover the semiconductor devices 11, and the encapsulation layer 14 is polished to expose the top surface of the semiconductor devices 11 outside the encapsulation layer 14. Next, the interposer 10 is mounted on a package substrate 16 through a plurality of conductive elements 15 at the connection side 10a thereof, and the package substrate 16 is electrically connected to the conductive through-silicon vias 100, and then the conductive elements 15 are covered by an underfill 17. Next, an encapsulant 18 is formed on the package substrate 16, such that the encapsulant 18 encapsulates the package layer 14 and the silicon interposer 10. Finally, a plurality of solder balls 160 are formed on the lower side of the package substrate 16 for being mounted on a circuit board 19.
However, in the semiconductor package 1, the semiconductor element 11 is flip-chip bonded to the circuit structure 101, and then the underfill 13 is filled into the semiconductor package 1, so that the outer side 130 of the underfill 13 is sloped, as shown in fig. 1', the outer side 130 of the underfill 13 flows over the side surface 11c of each semiconductor element 11 due to the capillary action generated by the gap S between the semiconductor elements 11, so that the internal stress of the semiconductor element 11 is increased, and when the package layer 14 is polished, the external polishing force is transmitted to the semiconductor element 11, which causes the stress concentration of the semiconductor element 11 to crack, and the reliability of the semiconductor package 1 is poor.
Therefore, how to overcome the above problems of the prior art has become an issue to be solved.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides an electronic package and a method for manufacturing the same, which can avoid the problem of cracking of the electronic component due to stress concentration.
The electronic package of the present invention includes: a load bearing structure; a plurality of electronic elements which are arranged on the bearing structure at intervals so as to form a gap between any two adjacent electronic elements, wherein a plurality of conductive bumps and a coating layer which coats the conductive bumps are formed on each electronic element, so that each electronic element is adhered to the bearing structure by the coating layer and is electrically connected with the bearing structure by the conductive bumps; and the packaging layer is formed on the bearing structure so as to coat the electronic elements and the coating layer.
The invention also provides a manufacturing method of the electronic packaging piece, which comprises the following steps: providing a plurality of electronic elements, wherein a plurality of conductive bumps and a coating layer coating the conductive bumps are formed on each electronic element; arranging a plurality of electronic elements on a bearing structure at intervals so as to form a gap between any two adjacent electronic elements, wherein each electronic element is adhered to the bearing structure by the coating layer and is electrically connected with the bearing structure by the conductive bump; and forming a packaging layer on the bearing structure to coat the electronic elements and the coating layer.
In the electronic package and the method for manufacturing the same, the structures of the electronic components are different from each other.
In the electronic package and the method for fabricating the same, the gap has a pitch of at most 300 μm.
The electronic package and the method for manufacturing the same further include polishing the package layer to expose a surface of the electronic component on a surface of the package layer.
In an embodiment, the side surface of the encapsulating layer is flush with the side surface of the electronic element.
In the electronic package and the method for manufacturing the same, the encapsulating layer protrudes out of the side surface of the electronic element, and the encapsulating layer does not contact the side surface of the electronic element. For example, the end of the cladding layer protrudes out of the side surface of the electronic element, and the cross section of the edge of the cladding layer is a sphere.
In the electronic package and the manufacturing method thereof, the encapsulating layer is a non-conductive film.
In the electronic package and the method for manufacturing the same, the young's modulus of the package layer is at least 20 GPa.
In the electronic package and the fabrication method thereof, the young's modulus of the package layer is greater than the young's modulus of the encapsulation layer.
In view of the above, in the electronic package and the method for manufacturing the same of the present invention, the encapsulating layer is mainly disposed on the electronic component to adhere to the supporting structure, so that the encapsulating layer does not creep to the side surface of the electronic component due to capillary action.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional semiconductor package.
Fig. 1' is a partially enlarged cross-sectional view of fig. 1.
Fig. 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing an electronic package according to the present invention.
FIG. 2B' is an enlarged partial cross-sectional view of the alternative embodiment of FIG. 2B.
FIG. 2C' is a schematic cross-sectional view of another embodiment of FIG. 2C.
Fig. 3 is a schematic cross-sectional view of another embodiment of fig. 2C.
Description of the reference numerals
1: semiconductor package
10: silicon intermediate plate
10 a: switching side
10 b: side of crystal
100: conductive through-silicon vias
101: circuit structure
11: semiconductor device with a plurality of semiconductor chips
11c,21c,23c,31 c: side surface
12: solder bump
13: primer
130: outside side
14,24: encapsulation layer
15: conductive element
16: package substrate
160: solder ball
17: primer
18: packaging colloid
19: circuit board
2,2',3: electronic package
2 a: whole page base material structure
20: bearing structure
200: line layer
21,31: electronic component
21 a: acting surface
21 b: non-functional surface
210: electrode pad
22: conductive bump
23: coating layer
230: edge of a container
24 b: upper surface of
310: packaging material
311: control chip
312: high bandwidth memory type chip
X: in the horizontal direction
L: cutting path
S: gap
t: and (4) spacing.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, proportions, and dimensions shown in the drawings and described herein are for illustrative purposes only and are not intended to limit the scope of the present invention, which is defined by the claims, but rather by the claims. In addition, the terms such as "above" and the like used in the present specification are for clarity of description only, and are not intended to limit the scope of the present invention, and changes or adjustments of the relative relationship thereof may be considered as the scope of the present invention without substantially changing the technical content.
Fig. 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the electronic package 2 according to the present invention.
As shown in fig. 2A, an entire substrate structure 2A is provided, which includes a plurality of electronic components 21 arranged in an array, and a plurality of conductive bumps 22 and a covering layer 23 covering the conductive bumps 22 are disposed on each of the electronic components 21.
The electronic component 21 can be an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, or an inductor, a package structure, or a combination thereof. In the present embodiment, the electronic component 21 is a semiconductor chip and has an active surface 21a and an inactive surface 21b opposite to each other, the active surface 21a has a plurality of electrode pads 210 thereon, conductive bumps 22 are formed on the electrode pads 210, the cover layer 23 is formed on the active surface 21a to cover the conductive bumps 22, and the conductive bumps 22 are exposed from the cover layer 23.
In addition, the Conductive bump 22 is a metal pillar (such as a copper pillar), a solder material or a combination thereof, and the cladding layer 23 is a Non-Conductive Film (NCF).
As shown in fig. 2B, the full-page substrate structure 2A is singulated along the cutting path L shown in fig. 2A to separate the electronic components 21, at least two electronic components 21 are disposed on a supporting structure 20 at intervals along the horizontal direction X, and a space (gap) S is formed between any two adjacent electronic components 21, wherein the distance t between the spaces (gaps) S is at most 300 micrometers (μm).
The carrier structure 20 may be a package substrate (substrate) having a core layer and a circuit structure or a coreless (core) circuit structure, and a plurality of circuit layers 200, such as a redistribution layer (RDL), are formed on a dielectric material. In the present embodiment, the supporting structure 20 is a coreless (core) wire structure. However, in other embodiments, the supporting structure 20 may also be a semiconductor substrate having a plurality of Through-Silicon vias (TSIs), which are used as a Silicon interposer (TSI). It should be understood that the supporting structure 20 may also be other supporting units for supporting electronic devices such as chips, such as lead frame (lead frame), but is not limited thereto.
In addition, when the electronic component 21 is pressed and adhered on the carrier structure 20 through the encapsulating layer 23, the conductive bumps 22 are electrically connected to the circuit layer 200 of the carrier structure 20 in a flip-chip manner.
In addition, the side surface 21c of the electronic component 21 is flush with the side surface 23c of the cladding layer 23 through the singulation process. However, in another embodiment, the side 23c of the covering layer 23 may be formed to protrude beyond the edge 230 of the side 21c of the electronic component 21 based on the force of pressing the electronic component 21 onto the carrying structure 20, as shown in fig. 2B'. Specifically, the edge 230 of the covering layer 23 has a convex cross-section (e.g., a hemispherical sphere).
In addition, in the embodiment, although the electronic devices 21 are all of the same type (i.e., active devices), their internal structures may be the same or different.
As shown in fig. 2C, an encapsulation layer 24 is formed on the carrier structure 20 to encapsulate the encapsulation layer 23 and the electronic elements 21.
The encapsulation layer 24 may be an insulating material, such as Polyimide (PI), dry film (dry film), epoxy (epoxy), molding compound (molding compound), or other suitable materials. In the present embodiment, the encapsulation layer 24 is formed on the carrier structure 20 by a pressing (laminating) or molding (molding) method, so that the encapsulation layer 24 fills the gap S.
In addition, the encapsulation layer 24 has a Young's modulus (Young's modulus) greater than that of the clad layer 23. In the present embodiment, the young's modulus of the encapsulation layer 24 is 20GPa or more.
In addition, the inactive surface 21b of the electronic component 21 and the upper surface 24b of the encapsulation layer 24 can be coplanar through a leveling process or a thinning process, as shown in fig. 2C', so that the inactive surface 21b of the electronic component 21 is exposed out of the encapsulation layer 24. For example, when the encapsulating layer 24 is formed on the carrying structure 20, the encapsulating layer 24 covers the non-active surface 21b of the electronic element 21, and then a part of the material of the encapsulating layer 24 is removed by grinding or cutting (or a part of the material of the non-active surface 21b of the electronic element 21 can be removed simultaneously as required), so that the non-active surface 21b of the electronic element 21 is flush with the upper surface 24b of the encapsulating layer 24.
In addition, after the package layer 24 is formed, a plurality of solder balls (not shown) may be formed on the lower side (or ball-implanting side) of the carrying structure 20 for the electronic package 2 to be mounted on an electronic device (not shown) such as a circuit board.
It should be understood that the electronic components 21 may be different types of electronic components. As shown in fig. 3, the two electronic components 21,31, the electronic component 21 (active component) is an Application-specific integrated circuit (ASIC) type semiconductor chip, and the other electronic component 31 is a package structure, which includes a package material 310, a control chip 311 and a package module of at least one High Bandwidth Memory (HBM) type chip 312, and the electrode pads 210 of the control chip 311 are combined with the conductive bumps 22.
Therefore, the manufacturing method of the present invention mainly forms the coating layer 23 on the electronic components 21,31, and then adheres to the carrying structure 20 through the coating layer 23, so that the cladding layer 23 does not creep up to the side surfaces 21c,31c of the electronic components 21,31 by capillary action, and thus regardless of the size of the gap t of the gap S (e.g., less than or equal to 150 μm), the cladding layer 23 does not have capillary phenomenon in the gap S, so that the stress increase inside the electronic components 21,31 can be avoided, and compared with the prior art, when the package layer 24 is polished by the method of the present invention, even if an external polishing force is transmitted to the electronic component 21,31, the stress applied to the electronic component 21,31 can be dispersed inside the electronic component, so as to avoid the cracking problem of the electronic components 21,31 caused by stress concentration, thereby improving the reliability of the electronic package 2.
In addition, the gap S is filled with the encapsulating layer 24 with a large young' S modulus, so that the strength of the gap S can be enhanced, and the phenomenon of package cracking caused by stress concentration in the electronic components 21 and 31 can be avoided.
The present invention also provides an electronic package 2, 2', 3 comprising: a carrier structure 20, a plurality of electronic components 21,31, and an encapsulation layer 24.
The electronic components 21,31 are disposed on the supporting structure 20 at intervals, so that a gap S is formed between any two adjacent electronic components 21,31, each electronic component 21,31 has a plurality of conductive bumps 22 and a covering layer 23 covering the conductive bumps 22, so that each electronic component 21,31 is adhered to the supporting structure 20 by the covering layer 23, and the conductive bumps 22 are electrically connected to the supporting structure 20.
The encapsulating layer 24 is formed on the carrying structure 20 to encapsulate the electronic elements 21,31 and the encapsulating layer 23.
In one embodiment, the plurality of electronic components 21,31 are configured differently from each other.
In one embodiment, the pitch t of the gap S is at most 300 μm.
In one embodiment, the surface (e.g., the non-active surface) of the electronic component 21,31 is exposed on the surface 24b of the encapsulation layer 24.
In one embodiment, the side 23c of the cladding 23 is flush with the sides 21c,31c of the electronic components 21, 31.
In one embodiment, the cladding layer 23 protrudes beyond the side surfaces 21c,31c of the electronic components 21,31, and the cladding layer 23 does not contact the side surfaces 21c,31c of the electronic components 21, 31. For example, the edge 230 of the cladding 23 protrudes from the side surface 21c of the electronic element 21, and the cross section of the edge 230 of the cladding 23 is a sphere.
In one embodiment, the cladding layer 23 is a non-conductive film.
In one embodiment, the Young's modulus of the encapsulation layer 24 is at least 20 GPa.
In one embodiment, the Young's modulus of the encapsulation layer 24 is greater than the Young's modulus of the cladding layer 23.
In summary, the electronic package and the method for fabricating the same according to the present invention are provided with the encapsulating layer on the electronic component to adhere to the supporting structure, so that the encapsulating layer is not pressed to the side surface of the electronic component, and therefore, the problem of cracking caused by stress concentration can be avoided inside the electronic component, and the reliability of the electronic package can be improved. In addition, the encapsulating layer 24 fills the gap S, so that the strength of the gap S can be enhanced, and the package will not crack due to stress concentration inside the electronic component.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. The scope of the invention is therefore indicated by the appended claims.

Claims (20)

1. An electronic package, comprising:
a load bearing structure;
a plurality of electronic elements which are arranged on the bearing structure at intervals so as to form a gap between any two adjacent electronic elements, wherein a plurality of conductive bumps and a coating layer which coats the conductive bumps are formed on each electronic element, so that each electronic element is electrically connected with the bearing structure by the conductive bumps after being adhered to the bearing structure by the coating layer; and
and the packaging layer is formed on the bearing structure so as to coat the electronic elements and the coating layer.
2. The electronic package according to claim 1, wherein the plurality of electronic components are configured differently from one another.
3. The electronic package of claim 1, wherein the gap has a pitch of at most 300 microns.
4. The electronic package according to claim 1, wherein a surface of the electronic component is exposed to a surface of the encapsulation layer.
5. The electronic package according to claim 1, wherein a side of the encapsulation layer is flush with a side of the electronic component.
6. The electronic package according to claim 1, wherein the cover layer protrudes beyond the side of the electronic device, and the cover layer does not contact the side of the electronic device.
7. The electronic package according to claim 6, wherein the end of the cover layer protrudes beyond the side of the electronic device, and the edge of the cover layer has a spherical shape in cross section.
8. The electronic package of claim 1, wherein the encapsulating layer is a non-conductive film.
9. The electronic package of claim 1, wherein the encapsulation layer has a young's modulus of at least 20 GPa.
10. The electronic package of claim 1, wherein the encapsulation layer has a young's modulus greater than a young's modulus of the encapsulation layer.
11. A method of fabricating an electronic package, comprising:
providing a plurality of electronic elements, wherein a plurality of conductive bumps and a coating layer coating the conductive bumps are formed on each electronic element;
arranging a plurality of electronic elements on a bearing structure at intervals so as to form a gap between any two adjacent electronic elements, wherein each electronic element is adhered to the bearing structure by the coating layer and is electrically connected with the bearing structure by the conductive bump; and
forming a packaging layer on the bearing structure to coat the electronic elements and the coating layer.
12. The method of manufacturing an electronic package according to claim 11, wherein the plurality of electronic components are configured differently from each other.
13. The method of claim 11, wherein the gap has a pitch of at most 300 μm.
14. The method of claim 11, further comprising grinding the encapsulation layer to expose a surface of the electronic component to a surface of the encapsulation layer.
15. The method of claim 11, wherein the side of the encapsulation layer is flush with the side of the electronic component.
16. The method of claim 11, wherein the cover layer protrudes beyond the side of the electronic device, and the cover layer does not contact the side of the electronic device.
17. The method of claim 16, wherein the end of the cladding layer protrudes beyond the side of the electronic device, and the edge of the cladding layer has a spherical shape in cross section.
18. The method of claim 11, wherein the encapsulation layer is a non-conductive film.
19. The method of claim 11, wherein the encapsulation layer has a young's modulus of at least 20 GPa.
20. The method of claim 11, wherein the encapsulation layer has a young's modulus greater than that of the encapsulation layer.
CN202010534710.8A 2020-06-04 2020-06-12 Electronic package and manufacturing method thereof Pending CN113764359A (en)

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TW109118804A TWI772816B (en) 2020-06-04 2020-06-04 Electronic package and manufacturing method thereof
TW109118804 2020-06-04

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CN109841605A (en) * 2017-11-29 2019-06-04 矽品精密工业股份有限公司 Electronic packing piece and its preparation method
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TWI772816B (en) 2022-08-01

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