TW202303900A - Semiconductor package and its manufacturing method - Google Patents

Abstract

A semiconductor package is provided with a supporting board, and at least one circuit structure with a first circuit layer is provided thereon, and then the supporting board is combined with a support structure using the circuit structure, and the support structure is there is at least one second circuit layer electrically connected to the first circuit layer, wherein the line width and line spacing of the first circuit layer are both smaller than the line width and line spacing of the second circuit layer. After that, the bracing plate is removed to install at least one semiconductor element on the circuit structure, so that the semiconductor element is electrically connected to the first circuit layer, and the semiconductor element is covered with a coating layer, so that the support Ultra-fine circuits and high-density circuit structures are manufactured on the parts to replace conventional silicon interposers.

Description

Semiconductor package and its manufacturing method

The present invention relates to a semiconductor package and its manufacturing process, especially to a semiconductor package without conductive through-silicon vias (TSV) and its manufacturing method.

With the evolution of semiconductor packaging technology, semiconductor devices (Semiconductor device) have developed different packaging types, and in order to improve electrical functions and save packaging space, different three-dimensional packaging technologies have been developed, such as fan-out package stacking (Fan Out Package on package, FO PoP for short), Chip Scale Package (CSP for short), Multi-Chip Module packaging (Multi-Chip Module, MCM for short) or 3D IC, etc., In order to cooperate with the greatly increased number of input/output ports on various chips, integrated circuits with different functions can be integrated into a single package structure. However, as the electrical functions of terminal products are more developed today, more and more semiconductor chips are connected to the interposer, so that the bonding area of the interposer will become larger and larger, and the layout of conductive through-silicon vias The quantity will also increase, resulting in a decrease in the yield rate of the packaging structure in the manufacturing process, thereby increasing the difficulty of the manufacturing process and the production cost.

Therefore, how to overcome the above-mentioned various problems has become an urgent problem to be solved at present.

In view of the various deficiencies of the above-mentioned conventional technologies, the present invention provides a semiconductor package, which includes: a circuit structure having a first circuit layer; a carrying structure having a second circuit layer on which the circuit structure is disposed, And the first circuit layer is electrically connected to the second circuit layer; the semiconductor element is arranged on the circuit structure and electrically connected to the first circuit layer; the cladding layer is formed on the carrying structure to cover The semiconductor element; the wiring structure is formed on the cladding layer; a plurality of conductive pillars are formed on the carrying structure and embedded in the cladding layer, so as to electrically connect the second wiring layer and the cladding layer The wiring structure; and the electronic components are arranged on the wiring structure.

In the aforementioned semiconductor package, the wiring structure includes at least one first insulating layer and at least one first wiring layer combined with the first insulating layer, and the first wiring layer is a fan-out (fan out) redistribution wiring layer (redistribution layer).

The present invention also provides a method for manufacturing a semiconductor package, which includes: arranging at least one circuit structure with a first circuit layer on a support plate; combining the circuit structure provided on the support plate to a carrying structure, wherein , the carrying structure has at least one second circuit layer electrically connected to the first circuit layer; removing the support plate; placing at least one semiconductor element on the circuit structure, and making the semiconductor element electrically connected to the first circuit layer A circuit layer; forming a cladding layer on the carrying structure, so that the cladding layer covers the semiconductor element; forming a plurality of conductive columns on the carrying structure, so that the second circuit layer is electrically connected by the plurality of conductive columns , wherein the plurality of conductive columns are embedded in the coating layer; a wiring structure electrically connecting the plurality of conductive columns is formed on the coating layer; and electronic components are arranged on the wiring structure.

In the aforementioned manufacturing method, the supporting plate is a glass plate, a steel plate or a silicon wafer.

In the aforementioned semiconductor package and its manufacturing method, the circuit structure is provided on the carrying structure through a plurality of conductive bumps, and the first circuit layer and the second circuit layer are electrically connected by the conductive bumps.

In the aforementioned semiconductor package and its manufacturing method, the plurality of conductive pillars are formed on the carrying structure through through formed vias (TMV).

It can be seen from the above that in the semiconductor package and its manufacturing method of the present invention, the conventional silicon interposer is replaced by making an ultra-fine line and a high-density line structure on the support, so that there is no need to make conductive through-silicon vias (TSVs). ), so compared with the prior art, the present invention can greatly reduce the difficulty of the manufacturing process and the manufacturing cost.

Furthermore, the electrical function of the semiconductor element can be connected to the carrying structure only through the first circuit layer, so the transmission speed of the signal electrical function of the semiconductor element can meet the high-speed specification, so compared with the conventional technology , The semiconductor package of the present invention can effectively improve the performance of end products.

1: Semiconductor package

10,10a: Circuit structure

100: first insulating layer

101: The first line layer

102,111,121: Conductive bumps

11: Semiconductor components

11a: Action surface

11b: Non-active surface

110: electrode pad

112: Packaging material

12: Electronic components

13: Bearing structure

130: second insulating layer

131: Second line layer

14: Conductive column

15: cladding layer

16: Wiring structure

160: insulating layer

161: line layer

17: Encapsulation layer

18: Conductive element

9,9a: support plate

90: bonding layer

L: cutting path

1A to 1H are schematic cross-sectional views of the manufacturing method of the semiconductor package of the present invention.

The implementation of the present invention is described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification, for the understanding and reading of those familiar with this technology, and are not used to limit the implementation of the present invention Therefore, it has no technical substantive meaning. Any modification of structure, change of proportional relationship or adjustment of size shall still fall within the scope of this invention without affecting the effect and purpose of the present invention. The technical content disclosed by the invention must be within the scope covered. At the same time, terms such as "above", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the present invention. The change or adjustment of the relative relationship shall also be regarded as the applicable scope of the present invention if there is no substantial change in the technical content.

1A to 1H are schematic cross-sectional views of the manufacturing method of the semiconductor package 1 of the present invention. As shown in FIG. 1A , at least one circuit structure 10 having a plurality of conductive bumps 102 is provided on a supporting board 9 .

In this embodiment, the wiring structure 10 is a coreless full-scale substrate, which includes at least one first insulating layer 100 and at least one first wiring layer 101 combined with the first insulating layer 100, and The conductive bumps 102 are formed on the outermost first circuit layer 101 , so that the conductive bumps 102 are electrically connected to the first circuit layer 101 . For example, the first insulating layer 100 is a dielectric material, such as ABF (Ajinomoto Build-up Film), photosensitive resin, polyimide (Polyimide, referred to as PI), bismaleimide triazine (Bismaleimide Triazine, referred to as BT), FR5 prepreg (Prepreg, referred to as PP), molding resin (Molding Compound), molded epoxy resin (Epoxy Molding Compound, referred to as EMC) or other appropriate materials, and the first circuit layer 101 is fan-out (fan out) type redistribution layer (redistribution layer, RDL for short). Moreover, the support plate 9 can be a glass plate, a steel plate, a silicon wafer, etc., and it is combined with the circuit structure 10 through a bonding layer 90 . For example, the bonding layer 90 can be a release film (separation layer) such as titanium silicon oxide or other suitable adhesive materials.

In addition, in this embodiment, since a plurality of circuit structures that meet the requirements of the packaging specification can be formed on the support plate 9 at the same time, after the conductive bumps 102 are formed on the outermost first circuit layer 101, it can be further along the following lines: The cutting path L shown in FIG. 1A performs singulation (cutting the support plate 9 together) to obtain a plurality of separated circuit structures 10 a and a plurality of separated support plates 9 a as shown in FIG. 1B .

As shown in FIG. 1C , the support plate 9 a is combined with the circuit structure 10 on a carrying structure 13 , and the circuit structure 10 is connected to the carrying structure 13 through the conductive bump 102 .

In this embodiment, the carrying structure 13 is, for example, a packaging substrate with a core layer and a wiring structure, a packaging substrate without a coreless wiring structure, or a silicon substrate with a conductive through-silicon via (TSV). Interposer (Through Silicon interposer, referred to as TSI) or other board type, which includes at least one second insulating layer 130 and at least one second wiring layer 131 combined with the second insulating layer 130, so that the second wiring layer 131 is combined And electrically connect the conductive bump 102 . For example, the second The circuit layer 131 is a build-up circuit specification, such as a PCB type, and the second insulating layer 130 is a dielectric material, such as ABF, photosensitive resin, polyimide (PI), bismaleimide three Zinc (BT), FR5 prepreg (PP), molded resin, molded epoxy resin (EMC) or other suitable materials. It should be understood that the carrying structure 13 can also be other chip-carrying substrates, such as a lead frame, a wafer, or other boards with metal wiring (routing), and is not limited to the above-mentioned . Moreover, the material of the second insulating layer 130 and the material of the first insulating layer 100 can be the same or different.

As shown in FIG. 1D , the support plate 9 a and the bonding layer 90 thereon are removed, and the first circuit layer 101 of the circuit structure 10 is exposed. In this embodiment, if the first circuit layer 101 is bonded to the bonding layer 90 , the first circuit layer 101 can be exposed after removing the bonding layer 90 . If the first insulating layer 100 is combined on the bonding layer 90, after removing the bonding layer 90, part of the material of the first insulating layer 100 can be removed by laser drilling or other hole forming methods, Part of the surface of the first wiring layer 101 is exposed outside. It should be understood that there are many ways to expose the first circuit layer 101 , such as grinding and leveling the insulating layer, which are not limited to the above.

As shown in FIG. 1E , at least one semiconductor element 11 is disposed on the wiring structure 10 , and the semiconductor element 11 is electrically connected to the first wiring layer 101 . The semiconductor device 11 can be an active device, a passive device or a combination thereof. The active element is, for example, a semiconductor chip, and the passive element is, for example, resistors, capacitors and inductors. In this embodiment, the semiconductor element 11 is a semiconductor chip, which has an opposite active surface 11a and a non-active surface 11b. The active surface 11a has a plurality of electrode pads 110, so as to be connected by a plurality of solder materials, metal pillars (pillar) Or other conductive bumps 111 are provided on the first circuit layer 101 of the circuit structure 10 by flip-chip and electrically connected to the first circuit layer 101, and are filled with a primer or a non-conductive underfill film (NCF) The packaging material 112 covers the conductive bumps 111; or, the semiconductor element 11 can be electrically connected to the first circuit layer 101 by a plurality of bonding wires (not shown); or, the semiconductor element 11 The first circuit layer 101 can be directly contacted. Therefore, the desired type and quantity can be placed on the line structure 10 To improve the electrical function of the semiconductor element, there are many ways to electrically connect the semiconductor element 11 to the circuit layer, which are not limited to the above.

As shown in FIG. 1F, a plurality of conductive pillars 14 are formed on the carrying structure 13, and a cladding layer 15 is formed on the carrying structure 13, so that the cladding layer 15 covers the circuit structure 10, the semiconductor element 11 and The conductive pillars 14 . In this embodiment, the conductive column 14 is a metal column such as a copper column, which is electrically connected to the second circuit layer 131 . Furthermore, the cladding layer 15 can be formed first, and then a through hole is formed on the cladding layer 15 to fill the conductive material into the through hole for serving as the conductive column 14 . For example, after forming the cladding layer 15 , the surface of the carrying structure 13 can be opened through a through molding via (TMV) to expose the second metal layer 131 , and then filled with solder material to form the conductive pillar 14 . Alternatively, the conductive pillar 14 can be formed first, and then the cladding layer 15 can be formed. It should be understood that the process sequence of the conductive pillar 14 and the cladding layer 15 can be designed according to requirements, as long as the conductive pillar 14 is embedded in the cladding layer 15 , there is no special limitation.

Also, if the cladding layer 15 is formed after the conductive pillar 14 is formed, a leveling process can be carried out as required, so that the upper surface of the cladding layer 15 is flush with the end surface of the conductive pillar 14, so that the conductive pillar The end surface of 14 exposes the cladding layer 15, and even the upper surface of the cladding layer 15 can be flush with the non-active surface 11b of the semiconductor element 11, so that the non-active surface 11b exposes the cladding layer 15. For example, the leveling process can be performed by grinding to remove part of the material of the conductive pillar 14 and part of the material of the cladding layer 15 .

In addition, the material forming the cladding layer 15 is, for example, polyimide (PI for short), dry film (dry film), epoxy resin (epoxy) or packaging material (molding compound) and other insulating materials, but not limited to the above. For example, lamination or molding can be used to form the cladding layer 15 on the carrying structure 10 .

As shown in FIG. 1G, a wiring structure 16 is formed on the cladding layer 15, and the wiring structure 16 is electrically connected to the conductive pillars 14, so that the semiconductor element 11 passes through the wiring structure 10 and passes through the carrier. The structure 13 and the conductive column 14 are electrically connected to the wiring structure 16 . In this embodiment, the wiring structure 16 includes at least one insulating layer 160 and a plurality of wiring layers 161 (such as RDL) disposed on the insulating layer 160 . For example, The material forming the circuit layer 161 is copper, and the material forming the insulating layer 160 is a dielectric material such as polyparabenazole (PBO), polyimide (PI), and prepreg (PP). It is PI material.

As shown in FIG. 1H , at least one electronic component 12 is connected on the wiring structure 16 , and the electronic component 12 is electrically connected to the circuit layer 161 . The electronic component 12 can be an active component, a passive component or a combination thereof. The active components are, for example, semiconductor chips, and the passive components are, for example, resistors, capacitors and inductors. In this embodiment, the electronic component 12 is provided on the circuit layer 161 by means of flip-chip with a plurality of conductive bumps 121 and electrically connected to the circuit layer 161; (not shown in the figure) is electrically connected to the circuit layer 161 by wire bonding. It should be understood that there are various ways for the electronic components 12 to be electrically connected to the circuit layer 161 , and are not limited to the above.

Furthermore, an encapsulation layer 17 can be formed on the wiring structure 16 so that the encapsulation layer 17 covers the electronic component 12 . For example, the material forming the packaging layer 17 is polyimide (polyimide, PI for short), dry film (dry film), epoxy resin (epoxy) or packaging material (molding compound) and other insulating materials, but not limited to the above-mentioned . It should be understood that the material of the encapsulation layer 17 and the material of the cladding layer 15 may be the same or different, and there is no special limitation.

In addition, a plurality of conductive elements 18 such as solder balls can be formed on the lower side of the carrying structure 10, so that the semiconductor package 1 can be connected to an electronic device such as a circuit board (not shown) through the conductive elements 18, wherein , the conductive elements 18 are electrically connected to the second circuit layer 131 .

To sum up, the manufacturing method of the present invention mainly replaces the conventional silicon interposer by using coreless technology to manufacture ultra-fine lines and high-density line structures 10 on the support member 9, so that there is no need to make conductive through-silicon vias (TSVs) ), so compared with the conventional technology, the manufacturing method of the present invention can greatly reduce the difficulty of manufacturing process and manufacturing cost, and the circuit structure 10 can match the fine pitch and fine line specifications of the semiconductor element 11, so that the semiconductor package 1 can It meets the multi-contact (I/O) requirement of the semiconductor device 11 .

Furthermore, the electrical function of the semiconductor element 11 can be connected to the carrying structure 13 only through the first circuit layer 101, so that the transmission of the signal (signal) electrical function of the semiconductor element 11 The speed can meet the high-speed specification, so compared with the conventional technology, the semiconductor package 1 of the present invention can effectively improve the performance of end products.

Moreover, the manufacturing method of the present invention utilizes the carrier structure 13 as a carrier plate for the packaging process, so there is no need to use an additional carrier, so the process time can be greatly shortened, and the yield rate of the semiconductor package 1 can be controlled to greatly improve production efficiency. .

In addition, since the circuit structure 10 can produce ultra-fine lines and high-density first circuit layer 101, the second circuit layer 131 of the carrying structure 13 can be combined with the conductive pillars 14 only by adopting general circuit specifications. , so the manufacturing method of the present invention can maintain the traditional design of the carrying structure 13 and the encapsulation process on it, so as to greatly save the manufacturing cost and effectively improve the yield.

The above-mentioned embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of the patent application described later.

1: Semiconductor package

10: Line structure

101: The first line layer

11: Semiconductor components

12: Electronic components

121: Conductive bump

13: Bearing structure

131: Second line layer

14: Conductive column

15: cladding layer

16: Wiring structure

161: line layer

17: Encapsulation layer

18: Conductive element

Claims (8)

A semiconductor package, comprising: The circuit structure has a first circuit layer; The carrying structure has a second circuit layer on which the circuit structure is disposed, and the first circuit layer is electrically connected to the second circuit layer; A semiconductor element is arranged on the circuit structure and electrically connected to the first circuit layer; A cladding layer is formed on the carrying structure to cover the semiconductor element; a wiring structure formed on the cladding layer; A plurality of conductive pillars are formed on the carrying structure and embedded in the cladding layer, so as to electrically connect the second circuit layer and the wiring structure; and Electronic components are arranged on the wiring structure. The semiconductor package as claimed in claim 1, wherein the wiring structure includes at least one first insulating layer and at least one first wiring layer combined with the first insulating layer, and the first wiring layer is fan out (fan out) ) type redistribution layer (redistribution layer). The semiconductor package according to claim 1, wherein the circuit structure is provided on the carrying structure through a plurality of conductive bumps, and the first circuit layer and the second circuit layer are electrically connected by the plurality of conductive bumps. The semiconductor package as claimed in claim 1, wherein the plurality of conductive pillars are formed on the carrier structure through through formed vias (TMV). A method for manufacturing a semiconductor package, comprising: disposing at least one wiring structure with a first wiring layer on a supporting board; combining the circuit structure on the support plate with a carrying structure, wherein the carrying structure has at least one second circuit layer electrically connected to the first circuit layer; remove the support plate; disposing at least one semiconductor element on the wiring structure, and electrically connecting the semiconductor element to the first wiring layer; forming a cladding layer on the carrying structure, so that the cladding layer covers the semiconductor element; Forming a plurality of conductive columns on the carrying structure, so as to electrically connect the second circuit layer through the plurality of conductive columns, wherein the plurality of conductive columns are embedded in the cladding layer; forming a wiring structure electrically connecting the plurality of conductive pillars on the cladding layer; and Electronic components are arranged on the wiring structure. The method for manufacturing a semiconductor package according to claim 5, wherein the support plate is a glass plate, a steel plate, or a silicon wafer. The method for manufacturing a semiconductor package as described in Claim 5, wherein the circuit structure is provided on the carrying structure through a plurality of conductive bumps, and the first circuit layer and the second circuit layer are electrically connected by the conductive bumps. The method of manufacturing a semiconductor package as claimed in claim 5, wherein the plurality of conductive pillars are formed on the carrier structure through through formed vias (TMV).

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