JP2006032625A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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JP2006032625A
JP2006032625A JP2004208835A JP2004208835A JP2006032625A JP 2006032625 A JP2006032625 A JP 2006032625A JP 2004208835 A JP2004208835 A JP 2004208835A JP 2004208835 A JP2004208835 A JP 2004208835A JP 2006032625 A JP2006032625 A JP 2006032625A
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semiconductor element
adhesive
insulating substrate
semi
semiconductor
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JP4688443B2 (en
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Kinichi Kumagai
欣一 熊谷
Takao Nishimura
隆雄 西村
Akira Takashima
晃 高島
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device to which a semiconductor element and an insulating substrate are fixed by using adhesive for controlling the leakage/widening of the adhesive, and for improving the adhesiveness of the semiconductor and the insulating substrate. <P>SOLUTION: This semiconductor device is provided with a semiconductor element 11, an insulating substrate 18 to which the semiconductor element is fixed by using thermosetting adhesive 16, a plurality of electrode pads arranged on the circuit formation face of the semiconductor element 11, a wire for electrically connecting the electrodes with an external terminal on the insulating substrate and sealing resin for sealing the semiconductor element and wire fixed on the insulating substrate. Adhesive 14 in a semi-cured status formed in the whole periphery of the external peripheral end face of the semiconductor element is thermoset with the thermosetting adhesive 16, and integrally formed with the thermosetting adhesive in the external periphery of the semiconductor element fixed on an insulating substrate 18. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は半導体装置及びその製造方法に係り、特に半導体素子と絶縁基板とを固定するために接着剤を用いる半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device using an adhesive to fix a semiconductor element and an insulating substrate and a manufacturing method thereof.

近年、電子情報機器の小型化及び高性能化に伴い、電子情報機器に搭載する半導体装置をより小型化、薄型化するための技術開発が要求されている。この要求に対処すべく、半導体装置のパッケージ構造の小型化、薄型化に向け急速に複雑化する一方で、その信頼性を維持していくことが重要になっている。   2. Description of the Related Art In recent years, with the miniaturization and high performance of electronic information equipment, there has been a demand for technological development for further downsizing and thinning semiconductor devices mounted on the electronic information equipment. In order to cope with this requirement, it is important to maintain the reliability of the package structure of the semiconductor device while rapidly complicating it toward a reduction in size and thickness.

樹脂封止型の半導体装置は、通常、半導体素子と絶縁基板とを固定するために接着剤を用いている。樹脂封止型半導体装置は、簡易な構造で小型化／軽量化を比較的容易に実現でき、組立コストも安いことから多くの半導体パッケージに採用されている。例えば、特許文献１に、樹脂封止型の半導体装置の一例が示されている。   A resin-encapsulated semiconductor device usually uses an adhesive to fix the semiconductor element and the insulating substrate. Resin-encapsulated semiconductor devices are employed in many semiconductor packages because they can be relatively easily reduced in size and weight with a simple structure, and the assembly cost is low. For example, Patent Document 1 shows an example of a resin-sealed semiconductor device.

特許文献１が示す樹脂封止型半導体装置では、半導体素子周囲に所定の角度傾斜した端面を形成することにより半導体素子端面のフィレットを最小限にすることで、より一層の小型化を可能にし、設計時の制約を少なくすることが提案されている。
特開２００３−１６３３１３号公報 In the resin-encapsulated semiconductor device shown in Patent Document 1, by further reducing the fillet of the semiconductor element end face by forming an end face inclined at a predetermined angle around the semiconductor element, further miniaturization is possible. It has been proposed to reduce design constraints.
JP 2003-163313 A

従来の樹脂封止型半導体装置の半導体素子と絶縁基板とを固定するために用いられる接着剤は、通常液状であり、半導体素子が押し当てられることによって絶縁基板上に濡れ広がる。このため、半導体素子周囲に濡れ広がった接着剤を制御することは困難であり、濡れ広がった領域には半導体素子の電極パッドとの接続端子を形成することができなくなる。また、半導体素子を薄型化すると、素子の周端面から回路形成面にも這い上がりが発生し、場合によっては絶縁基板の端子との接続のための電極パッドに影響を及ぼし、小型化、薄型化を阻害する可能性がある。   An adhesive used for fixing a semiconductor element and an insulating substrate of a conventional resin-encapsulated semiconductor device is usually a liquid and wets and spreads on the insulating substrate when the semiconductor element is pressed. For this reason, it is difficult to control the adhesive spread around the semiconductor element, and a connection terminal with the electrode pad of the semiconductor element cannot be formed in the wet spread area. In addition, when the semiconductor element is made thinner, the circuit forming surface also crawls up from the peripheral edge surface of the element, affecting the electrode pads for connection with the terminals of the insulating substrate in some cases, making it smaller and thinner. May be disturbed.

逆に、接着剤の濡れが十分でなく内部に気泡などが残った場合には、耐熱性を低下させる原因になる。   On the contrary, when the adhesive is not sufficiently wetted and air bubbles remain inside, it causes a decrease in heat resistance.

また、接着剤は半導体素子の外周端面にも濡れ広がり、フィレットと呼ばれる樹脂溜まりを形成する。このフィレットは半導体素子と絶縁基板の密着性を向上させるために有効な構造であるが、十分なはみ出しが無い場合には、半導体素子と絶縁基板間の毛細管現象によって引けが生じてしまい、耐熱性を低下させる原因になる。   The adhesive also spreads on the outer peripheral end surface of the semiconductor element and forms a resin pool called a fillet. This fillet is an effective structure for improving the adhesion between the semiconductor element and the insulating substrate. However, if there is not enough protrusion, the capillary will be damaged by the capillary phenomenon between the semiconductor element and the insulating substrate, resulting in heat resistance. It will cause the decrease.

従って、従来の樹脂封止型の半導体装置の課題として、接着剤によって半導体素子を絶縁基板に固定する際に、接着剤の濡れ性が良好となるように制御する必要がある。   Therefore, as a problem of the conventional resin-encapsulated semiconductor device, it is necessary to control so that the wettability of the adhesive is good when the semiconductor element is fixed to the insulating substrate with the adhesive.

上記の問題を解決する方法としてフィルム状の接着剤も開発されているが、半導体素子と絶縁基板間の密着性を重視する場合、流動性を上げる必要が生じ、液状接着剤と同じ問題が生じる。逆に、濡れ広がりを抑制した場合、流動性を下げる必要が生じ、半導体素子と絶縁基板間の十分な密着性を確保することが困難になる。また、半導体素子の外周端面への濡れ性も期待できないことから、耐熱性を低下させる原因になってしまう。   A film-like adhesive has also been developed as a method for solving the above problem. However, when importance is attached to the adhesion between the semiconductor element and the insulating substrate, it is necessary to increase the fluidity, and the same problem as the liquid adhesive occurs. . Conversely, when wetting and spreading are suppressed, it is necessary to lower the fluidity, and it becomes difficult to ensure sufficient adhesion between the semiconductor element and the insulating substrate. Moreover, since the wettability to the outer peripheral end surface of the semiconductor element cannot be expected, it causes a decrease in heat resistance.

特許文献１の半導体装置の場合には、半導体素子の外周端面に特殊な加工を行う必要があるため、ヒビなどのチッピングが発生する可能性が高くなる。半導体素子が異型になるため取り扱いが困難であり、半導体装置の薄型化への対応が困難である。   In the case of the semiconductor device of Patent Document 1, since it is necessary to perform special processing on the outer peripheral end face of the semiconductor element, there is a high possibility that chipping such as cracks will occur. Since the semiconductor element is atypical, it is difficult to handle, and it is difficult to cope with the thinning of the semiconductor device.

本発明は、上記の点に鑑みてなされたものであり、半導体素子と絶縁基板とを接着剤を用いて固定する半導体装置において、接着剤の濡れ広がりを制御して、半導体素子と絶縁基板との密着性を向上させることを目的とする。   The present invention has been made in view of the above points, and in a semiconductor device that fixes a semiconductor element and an insulating substrate using an adhesive, the wetting and spreading of the adhesive is controlled, and the semiconductor element and the insulating substrate It aims at improving the adhesiveness of.

上記の課題を解決するために、本発明の半導体装置は、外周端面全周に接着剤が配設された半導体素子と、熱硬化性接着剤を介して前記半導体素子が固定される絶縁基板と、前記絶縁基板と前記半導体素子とを封止する封止樹脂とを備え、前記半導体素子の外周及び前記絶縁基板との間において、前記半導体素子の外周端面全周に配設された前記接着剤と前記熱硬化性接着剤とが一体的に形成されていることを特徴とする。   In order to solve the above-described problems, a semiconductor device of the present invention includes a semiconductor element in which an adhesive is disposed all around the outer peripheral end surface, and an insulating substrate to which the semiconductor element is fixed via a thermosetting adhesive. The adhesive comprising: a sealing resin that seals the insulating substrate and the semiconductor element, and the adhesive disposed around the outer peripheral end surface of the semiconductor element between the outer periphery of the semiconductor element and the insulating substrate And the thermosetting adhesive are integrally formed.

本発明の半導体装置において、前記半導体素子の外周端面全周に配設された前記接着剤は半硬化接着剤を用いて構成することができる。   In the semiconductor device of the present invention, the adhesive disposed on the entire outer peripheral end surface of the semiconductor element can be configured using a semi-cured adhesive.

上記の課題を解決するために、本発明の半導体装置の製造方法は、半導体素子の外周端面全周に半硬化状態の接着剤を配設する工程と、熱硬化性接着剤を絶縁基板に塗布する工程と、前記半導体素子を前記熱硬化性接着剤を介して前記絶縁基板に押圧する工程と、前記熱硬化性接着剤を加熱して硬化させることにより前記半導体素子を前記絶縁基板に固定する工程と、前記半硬化状態の接着剤を熱硬化し、前記半導体素子の外周及び前記半導体素子と前記絶縁基板との接合部を前記熱硬化性接着剤と共に封止する工程とを含むことを特徴とする。   In order to solve the above-described problems, a method for manufacturing a semiconductor device according to the present invention includes a step of disposing a semi-cured adhesive around the entire outer peripheral end surface of a semiconductor element, and applying a thermosetting adhesive to an insulating substrate. A step of pressing the semiconductor element against the insulating substrate via the thermosetting adhesive, and fixing the semiconductor element to the insulating substrate by heating and curing the thermosetting adhesive. And a step of thermosetting the semi-cured adhesive and sealing the outer periphery of the semiconductor element and a joint between the semiconductor element and the insulating substrate together with the thermosetting adhesive. And

上記の課題を解決するために、本発明の半導体装置の製造方法は、半導体素子の外周端面全周に半硬化状態の接着剤を配設する工程と、熱硬化性接着剤を絶縁基板に塗布する工程と、前記半導体素子の外部電極形成面を前記絶縁基板に対向させて、前記半導体素子を前記熱硬化性接着剤を介して前記絶縁基板に押圧する工程と、前記熱硬化性接着剤を加熱して硬化させると共に、前記外部電極を前記絶縁基板上の電極に接合して、前記半導体素子を前記絶縁基板に固定する工程と、前記半硬化状態の接着剤を熱硬化し、前記半導体素子の外周及び前記半導体素子と前記絶縁基板との接合部を前記熱硬化性接着剤と共に封止する工程とを含むことを特徴とする。   In order to solve the above-described problems, a method for manufacturing a semiconductor device according to the present invention includes a step of disposing a semi-cured adhesive around the entire outer peripheral end surface of a semiconductor element, and applying a thermosetting adhesive to an insulating substrate. A step of pressing the semiconductor element against the insulating substrate with the thermosetting adhesive facing the external electrode forming surface of the semiconductor element to the insulating substrate, and the thermosetting adhesive. Heating and curing, bonding the external electrode to the electrode on the insulating substrate, and fixing the semiconductor element to the insulating substrate; and thermosetting the semi-cured adhesive; and the semiconductor element And a step of sealing a joint portion between the semiconductor element and the insulating substrate together with the thermosetting adhesive.

上記の課題を解決するために、本発明の半導体装置の製造方法は、半導体素子の外周端面全周に第１の半硬化接着剤を配設する工程と、前記半導体素子の回路形成面と反対側の裏面に第２の半硬化接着剤を配設する工程と、前記半導体素子を前記第２の半硬化接着剤を介して絶縁基板に押圧する工程と、前記第１の半硬化接着剤と前記第２の半硬化接着剤を同時に加熱して硬化させることにより前記半導体素子を前記絶縁基板に固定し、前記半導体素子の外周及び前記半導体素子と前記絶縁基板との接合部を封止する工程とを含むことを特徴とする。   In order to solve the above-described problems, a method of manufacturing a semiconductor device according to the present invention includes a step of disposing a first semi-cured adhesive all around an outer peripheral end surface of a semiconductor element, and a circuit forming surface opposite to the semiconductor element. A step of disposing a second semi-cured adhesive on the rear surface of the side, a step of pressing the semiconductor element against the insulating substrate through the second semi-cured adhesive, and the first semi-cured adhesive The step of fixing the semiconductor element to the insulating substrate by simultaneously heating and curing the second semi-cured adhesive, and sealing the outer periphery of the semiconductor element and the junction between the semiconductor element and the insulating substrate. It is characterized by including.

上述のごとく本発明によれば、半導体素子の外周端面に予め接着剤を半硬化状態で形成しておくことによって、絶縁基板上における接着剤の濡れ広がりを抑えるとともに、半導体素子の外周端面の半硬化接着剤が熱によって流動性を取り戻すことによって、絶縁基板と半導体素子の隙間に空間のない、半導体素子表面にも這い上がらない良好なフィレットを形成することができる。したがって、本発明の半導体装置によれば、半導体素子と絶縁基板との密着性を向上できる。   As described above, according to the present invention, the adhesive is preliminarily formed on the outer peripheral end surface of the semiconductor element in a semi-cured state, thereby suppressing the wetting and spreading of the adhesive on the insulating substrate and the half of the outer peripheral end surface of the semiconductor element. When the cured adhesive regains fluidity by heat, it is possible to form a good fillet that has no space between the insulating substrate and the semiconductor element and does not crawl on the surface of the semiconductor element. Therefore, according to the semiconductor device of the present invention, the adhesion between the semiconductor element and the insulating substrate can be improved.

次に、本発明を実施するための最良の形態について図面と共に説明する。   Next, the best mode for carrying out the present invention will be described with reference to the drawings.

図１は、本発明の第１の実施形態に係る半導体装置に用いられる半硬化接着剤を示す図である。図２は、本発明の第１の実施形態に係る半導体装置の製造工程を説明するための図である。図３は、本発明の第１の実施形態に係る半導体装置の側断面図である。   FIG. 1 is a diagram showing a semi-cured adhesive used in the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a diagram for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a sectional side view of the semiconductor device according to the first embodiment of the present invention.

図１の（ａ）は本発明の第１の実施形態の半導体装置における半導体素子１１の上面図であり、図１の（ｂ）は半導体素子１１の側断面図である。   FIG. 1A is a top view of the semiconductor element 11 in the semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a side sectional view of the semiconductor element 11.

図１に示すように、半導体素子１１は回路形成面１１ａの周縁部に複数の電極パッド１２が配設されている。電極パッド１２は半導体素子１１内の回路を外部端子と接続するために設けられ、半導体素子１１と外部の回路との間で電気的な信号のやりとりが電極パッド１２を介して行われる。   As shown in FIG. 1, the semiconductor element 11 has a plurality of electrode pads 12 disposed on the peripheral edge of the circuit forming surface 11a. The electrode pad 12 is provided to connect a circuit in the semiconductor element 11 to an external terminal, and an electrical signal is exchanged between the semiconductor element 11 and an external circuit through the electrode pad 12.

半導体素子１１の外周端面全周に半硬化接着剤１４が予め形成される。半導体素子１１の裏面１１ｂには接着剤等を形成しない。本実施形態の半硬化接着剤１４の好適な材料として、熱硬化性エポキシ樹脂等を用いることができる。   A semi-cured adhesive 14 is formed in advance on the entire outer peripheral end surface of the semiconductor element 11. No adhesive or the like is formed on the back surface 11 b of the semiconductor element 11. As a suitable material for the semi-cured adhesive 14 of the present embodiment, a thermosetting epoxy resin or the like can be used.

この半硬化接着剤１４は、所謂Ｂ−状態（Ｂ−ステージ）と呼ばれる半硬化状態の接着剤を用いる。一般に熱硬化性接着剤として用いられる熱硬化性樹脂の加工硬化過程において、初期縮合物・初期反応物であって低分子量の可溶可融状のプレポリマーの段階（Ａ−状態）の樹脂をある程度加熱し反応を進めて、分子量・溶融粘度を上昇させた段階がＢ−状態、即ち半硬化状態である。半硬化状態の樹脂をさらに加熱し反応を進めることにより、最終的に硬化させた段階をＣ−状態（Ｃ−ステージ）という。   The semi-cured adhesive 14 uses a semi-cured adhesive called a so-called B-state (B-stage). In the process and curing process of a thermosetting resin generally used as a thermosetting adhesive, an initial condensate / initial reaction product of a low molecular weight soluble fusible prepolymer stage (A-state) The stage in which the reaction is advanced by heating to some extent to increase the molecular weight and melt viscosity is the B-state, that is, the semi-cured state. The stage which was finally cured by further heating the semi-cured resin to advance the reaction is called C-state (C-stage).

図３を用いて、本発明の第１の実施形態に係る半導体装置１０の構成について説明する。   The configuration of the semiconductor device 10 according to the first embodiment of the present invention will be described with reference to FIG.

図３に示すように、半導体装置１０は、半導体素子１１と、熱硬化性接着剤１６を用いて半導体素子１１が固定される絶縁基板１８と、半導体素子１１の回路形成面１１ａに配設した複数の電極パッド１２と、電極パッド１２と絶縁基板１８上の外部電極パッド１７とを電気的に接続するワイヤ１３と、絶縁基板１８上に固定された半導体素子１１及びワイヤ１３を封止する封止樹脂１５と、絶縁基板１８の裏面に配設された複数の半田ボール１９とから構成される。半導体素子１１の外周端面全周に設けた半硬化状態の接着剤１４が熱硬化性接着剤１６とともに加熱により硬化され、絶縁基板１８上に固定された半導体素子１１の外周において熱硬化性接着剤１６と一体的に形成される。   As shown in FIG. 3, the semiconductor device 10 is disposed on the semiconductor element 11, the insulating substrate 18 to which the semiconductor element 11 is fixed using a thermosetting adhesive 16, and the circuit formation surface 11 a of the semiconductor element 11. A plurality of electrode pads 12, a wire 13 that electrically connects the electrode pad 12 and the external electrode pad 17 on the insulating substrate 18, a semiconductor element 11 fixed on the insulating substrate 18, and a seal that seals the wire 13 It is composed of a stop resin 15 and a plurality of solder balls 19 disposed on the back surface of the insulating substrate 18. The semi-cured adhesive 14 provided on the entire outer peripheral end surface of the semiconductor element 11 is cured by heating together with the thermosetting adhesive 16, and the thermosetting adhesive is disposed on the outer periphery of the semiconductor element 11 fixed on the insulating substrate 18. 16 is formed integrally.

本実施形態の封止樹脂１５及び熱硬化性接着剤１６の好適な材料として、熱硬化性エポキシ樹脂等を用いることができる。   As a suitable material for the sealing resin 15 and the thermosetting adhesive 16 of the present embodiment, a thermosetting epoxy resin or the like can be used.

参照符号１４ａは半硬化接着剤１４の熱硬化後の状態を示し、参照符号１６ａは熱硬化性接着剤１６の、半導体素子１１を絶縁基板１８上に搭載した後の状態を示す。   Reference numeral 14 a indicates a state after the thermosetting of the semi-cured adhesive 14, and reference numeral 16 a indicates a state of the thermosetting adhesive 16 after the semiconductor element 11 is mounted on the insulating substrate 18.

図２を用いて、本発明の第１の実施形態に係る半導体装置１０の製造工程について説明する。   A manufacturing process of the semiconductor device 10 according to the first embodiment of the present invention will be described with reference to FIG.

図２（ａ）に示すように、半導体素子１１には、回路形成面１１ａにＬＳＩ等の内部回路（図示なし）が形成され、回路形成面１１ａの周縁部に複数の電極パッド１２（図１）が予め配設されている。また、半導体素子１１の外周端面全周には半硬化状態の接着剤１４が予め形成されている。まず、絶縁基板１８に熱硬化性接着剤１６を塗布する。そして、回路形成面１１ａを上向き、裏面１１ｂを下向き（絶縁基板１８に対向する向き）にした状態で半導体素子１１を、絶縁基板１８の上方に配置する。   As shown in FIG. 2A, in the semiconductor element 11, an internal circuit (not shown) such as LSI is formed on the circuit formation surface 11a, and a plurality of electrode pads 12 (FIG. 1) are formed on the peripheral portion of the circuit formation surface 11a. ) Are arranged in advance. A semi-cured adhesive 14 is formed in advance on the entire outer peripheral end surface of the semiconductor element 11. First, the thermosetting adhesive 16 is applied to the insulating substrate 18. Then, the semiconductor element 11 is disposed above the insulating substrate 18 with the circuit forming surface 11a facing upward and the back surface 11b facing downward (direction facing the insulating substrate 18).

図２（ａ）の工程において、熱硬化性接着剤１６の塗布量は、絶縁基板１８上に半導体素子１１を搭載した後の熱硬化性接着剤１６の濡れ広がりが半導体素子１１の裏面１１ｂからはみ出ない程度に調製される。また、半硬化状態の接着剤１４は、熱硬化後の接着剤１４ａの濡れ広がりが良好となるように、所定の幅で半導体素子１１の外周端面全周に形成される。   In the process of FIG. 2A, the amount of the thermosetting adhesive 16 applied is such that the wetting and spreading of the thermosetting adhesive 16 after mounting the semiconductor element 11 on the insulating substrate 18 starts from the back surface 11 b of the semiconductor element 11. Prepared to the extent that it does not protrude. Further, the semi-cured adhesive 14 is formed on the entire circumference of the outer peripheral end surface of the semiconductor element 11 with a predetermined width so that the wet spread of the adhesive 14a after thermosetting is good.

次に、図２（ｂ）に示すように、半導体素子１１が絶縁基板１８に押圧される圧力により、熱硬化性接着剤１６は濡れ広がる。このとき、熱硬化性接着剤１６ａは半導体素子１１の領域よりも狭い領域で濡れ広がる。そして、この状態の熱硬化性接着剤１６ａを硬化させるために加熱する。熱硬化性接着剤１６ａの硬化により、半導体素子１１が絶縁基板１８に固定される。   Next, as shown in FIG. 2B, the thermosetting adhesive 16 spreads wet by the pressure with which the semiconductor element 11 is pressed against the insulating substrate 18. At this time, the thermosetting adhesive 16 a spreads in a region narrower than the region of the semiconductor element 11. And it heats in order to harden the thermosetting adhesive agent 16a of this state. The semiconductor element 11 is fixed to the insulating substrate 18 by the curing of the thermosetting adhesive 16a.

図２（ｃ）に示すように、半導体素子１１の外周端面全周に形成した半硬化状態の接着剤１４が熱硬化性接着剤１６ａと共に熱硬化されて接着剤１４ａとなり、絶縁基板１８上に固定された半導体素子１１の外周において熱硬化性接着剤１６ａと一体的に形成される。半硬化状態の接着剤１４は加熱により流動性を取り戻して半導体素子１１裏面と熱硬化性接着剤１６ａの隙間を埋めている。   As shown in FIG. 2C, the semi-cured adhesive 14 formed on the entire outer peripheral end surface of the semiconductor element 11 is thermally cured together with the thermosetting adhesive 16 a to become the adhesive 14 a, and is formed on the insulating substrate 18. The outer periphery of the fixed semiconductor element 11 is formed integrally with the thermosetting adhesive 16a. The semi-cured adhesive 14 regains fluidity by heating and fills the gap between the back surface of the semiconductor element 11 and the thermosetting adhesive 16a.

さらに、図３に示すように、ワイヤボンディング工程を行うことにより、電極パッド１２と絶縁基板１８上の外部電極パッド１７をワイヤ１３により電気的に接続する。次に、所定の樹脂封止工程を行うことにより、封止樹脂１５にて、絶縁基板１８に固定した半導体素子１１及びワイヤ１３を封止する。さらに、他の配線基板（マザーボード等）への接続のため、絶縁基板１８の底面に複数の半田ボール１９を配置することによって半導体装置１０が完成される。   Further, as shown in FIG. 3, the electrode pad 12 and the external electrode pad 17 on the insulating substrate 18 are electrically connected by the wire 13 by performing a wire bonding process. Next, the semiconductor element 11 and the wire 13 fixed to the insulating substrate 18 are sealed with the sealing resin 15 by performing a predetermined resin sealing process. Furthermore, the semiconductor device 10 is completed by disposing a plurality of solder balls 19 on the bottom surface of the insulating substrate 18 for connection to another wiring board (such as a mother board).

図３の半導体装置１０によれば、半導体素子１１の外周端面に予め接着剤を半硬化状態で形成しておくことによって、絶縁基板上における接着剤の濡れ広がりを抑えるとともに、半導体素子１１の外周端面の接着剤が熱によって流動性を取り戻すことによって、絶縁基板と半導体素子の隙間に空間のない、半導体素子表面に這い上がらない良好なフィレットを形成することができる。   According to the semiconductor device 10 of FIG. 3, the adhesive is preliminarily formed on the outer peripheral end face of the semiconductor element 11 in a semi-cured state, thereby suppressing the wetting and spreading of the adhesive on the insulating substrate and the outer periphery of the semiconductor element 11. When the adhesive on the end surface regains fluidity by heat, a good fillet that does not crawl on the surface of the semiconductor element without a space between the insulating substrate and the semiconductor element can be formed.

また、半硬化状態の接着剤１４の幅を調整することによって、フィレットの濡れ広がりを制御することができるので、半導体装置１０の小型化を実現できる。半硬化状態の接着剤１４は、半硬化時は比較的高い硬度を持たせることによって、半導体素子１１のキャリアとして使用され、チップクラックなどを防止することができ、半導体装置の薄型化を実現できる。   In addition, by adjusting the width of the semi-cured adhesive 14, the wetting and spreading of the fillet can be controlled, so that the semiconductor device 10 can be downsized. The semi-cured adhesive 14 is used as a carrier for the semiconductor element 11 by imparting a relatively high hardness during semi-curing, thereby preventing chip cracks and the like and realizing a thin semiconductor device. .

図３の半導体装置１０では、一個の半導体素子１１のみを絶縁基板１８上に搭載している例を説明したが、本発明はこの実施態様に限定されるものではなく、配線基板上に複数個の半導体素子を搭載してもよい。その場合、複数個の半導体素子と配線基板との接続は、フリップチップボンディング、ＴＡＢ（tape automated bonding）テープ、ワイヤボンディング等により行う。また、その場合、全ての半導体素子の外周端面に半硬化状態の接着剤を形成する必要はなく、小型化、薄型化を実現したい半導体素子のみに形成すればよい。   In the semiconductor device 10 of FIG. 3, the example in which only one semiconductor element 11 is mounted on the insulating substrate 18 has been described. However, the present invention is not limited to this embodiment, and a plurality of elements are formed on the wiring substrate. The semiconductor element may be mounted. In this case, the connection between the plurality of semiconductor elements and the wiring board is performed by flip chip bonding, TAB (tape automated bonding) tape, wire bonding, or the like. In that case, it is not necessary to form a semi-cured adhesive on the outer peripheral end faces of all the semiconductor elements, and they may be formed only on the semiconductor elements to be reduced in size and thickness.

次に、図４は、本発明の第２の実施形態に係る半導体装置に用いられる半硬化接着剤を示す図である。図５は、本発明の第２の実施形態に係る半導体装置の製造工程を説明するための図である。図６は、本発明の第２の実施形態に係る半導体装置の側断面図である。   Next, FIG. 4 is a figure which shows the semi-hardened adhesive used for the semiconductor device based on the 2nd Embodiment of this invention. FIG. 5 is a diagram for explaining a manufacturing process of the semiconductor device according to the second embodiment of the present invention. FIG. 6 is a sectional side view of a semiconductor device according to the second embodiment of the present invention.

図４の（ａ）は本発明の第２の実施形態の半導体装置における半導体素子２１の上面図であり、図４の（ｂ）は半導体素子２１の側断面図である。   4A is a top view of the semiconductor element 21 in the semiconductor device according to the second embodiment of the present invention, and FIG. 4B is a side sectional view of the semiconductor element 21.

図４に示すように、半導体素子２１は回路形成面２１ａの周縁部に複数の電極パッド２２が配設されている。電極パッド２２は半導体素子２１内の回路を外部端子と接続するために設けられ、半導体素子２１と外部の回路との間で電気的な信号のやりとりが電極パッド２２を介して行われる。さらに、図４の（ｂ）に示すように、半導体素子２１には、回路形成面２１ａの複数の電極パッド２２上にそれぞれ複数のバンプ２３が予め形成されている。   As shown in FIG. 4, the semiconductor element 21 is provided with a plurality of electrode pads 22 on the peripheral edge of the circuit forming surface 21a. The electrode pad 22 is provided to connect a circuit in the semiconductor element 21 to an external terminal, and an electrical signal is exchanged between the semiconductor element 21 and an external circuit through the electrode pad 22. Further, as shown in FIG. 4B, a plurality of bumps 23 are previously formed on the semiconductor element 21 on the plurality of electrode pads 22 on the circuit forming surface 21a.

このバンプ２３は、図３の半導体装置１０においてワイヤ１３の形成に用いられるワイヤボンディングと同様の工程を行うことにより、電極パッド２２上に形成することができる。後述するように、半導体素子２１は回路形成面２１ａを絶縁基板に対向させた状態で熱硬化性接着剤により絶縁基板に固定され、バンプ２３により電極パッド２２が絶縁基板上の外部端子と電気的に接続される。   The bumps 23 can be formed on the electrode pads 22 by performing the same process as the wire bonding used for forming the wires 13 in the semiconductor device 10 of FIG. As will be described later, the semiconductor element 21 is fixed to the insulating substrate by a thermosetting adhesive with the circuit forming surface 21a facing the insulating substrate, and the electrode pads 22 are electrically connected to the external terminals on the insulating substrate by the bumps 23. Connected to.

図４に示すように、半導体素子２１の外周端面全周に半硬化接着剤２４が予め形成される。半導体素子２１の裏面２１ｂには接着剤等を形成しない。本実施形態の半硬化接着剤２４の好適な材料として、熱硬化性エポキシ樹脂等を用いることができる。この半硬化接着剤２４は、図１を用いて説明した半硬化接着剤１４と同様の接着剤を用いることができる。   As shown in FIG. 4, a semi-cured adhesive 24 is formed in advance on the entire outer peripheral end surface of the semiconductor element 21. No adhesive or the like is formed on the back surface 21 b of the semiconductor element 21. As a suitable material for the semi-cured adhesive 24 of the present embodiment, a thermosetting epoxy resin or the like can be used. As the semi-cured adhesive 24, the same adhesive as the semi-cured adhesive 14 described with reference to FIG. 1 can be used.

図６を用いて、本発明の第２の実施形態に係る半導体装置２０の構成について説明する。   The configuration of the semiconductor device 20 according to the second embodiment of the present invention will be described with reference to FIG.

図６に示すように、半導体装置２０は、半導体素子２１と、熱硬化性接着剤２６を用いて半導体素子２１が固定される絶縁基板２８と、半導体素子２１の回路形成面２１ａに配設した複数の電極パッド２２と、電極パッド２２と絶縁基板２８上の外部電極パッド２７とを電気的に接続するバンプ２３と、絶縁基板１８上に固定された半導体素子２１を封止する封止樹脂２５と、絶縁基板２８の裏面に配設された複数の半田ボール２９とから構成される。半導体素子２１の外周端面全周に設けた半硬化状態の接着剤２４が熱硬化性接着剤２６と共に加熱により硬化され、絶縁基板２８上に固定された半導体素子２１の外周において熱硬化性接着剤２６と一体的に形成される。   As shown in FIG. 6, the semiconductor device 20 is disposed on a semiconductor element 21, an insulating substrate 28 to which the semiconductor element 21 is fixed using a thermosetting adhesive 26, and a circuit formation surface 21 a of the semiconductor element 21. A plurality of electrode pads 22, bumps 23 that electrically connect the electrode pads 22 and external electrode pads 27 on the insulating substrate 28, and a sealing resin 25 that seals the semiconductor element 21 fixed on the insulating substrate 18. And a plurality of solder balls 29 disposed on the back surface of the insulating substrate 28. The semi-cured adhesive 24 provided on the entire outer peripheral end surface of the semiconductor element 21 is cured by heating together with the thermosetting adhesive 26, and the thermosetting adhesive is disposed on the outer periphery of the semiconductor element 21 fixed on the insulating substrate 28. 26 is formed integrally.

本実施形態の封止樹脂２５及び熱硬化性接着剤２６の好適な材料として、熱硬化性エポキシ樹脂等を用いることができる。   As a suitable material for the sealing resin 25 and the thermosetting adhesive 26 of the present embodiment, a thermosetting epoxy resin or the like can be used.

図６において、参照符号２３ａはバンプ２３の、フリップチップボンディングにより電極パッド２２と外部電極パッド２７とを電気的に接続した後の状態を示し、参照符号２４ａは接着剤２４の熱硬化後の状態を示し、参照符号２６ａは熱硬化性接着剤２６の、半導体素子２１を絶縁基板２８上に搭載した後の状態を示す。   In FIG. 6, reference numeral 23 a indicates a state of the bump 23 after the electrode pad 22 and the external electrode pad 27 are electrically connected by flip chip bonding, and reference numeral 24 a indicates a state after the adhesive 24 is thermally cured. Reference numeral 26 a indicates a state of the thermosetting adhesive 26 after the semiconductor element 21 is mounted on the insulating substrate 28.

図５を用いて、本発明の第２の実施形態に係る半導体装置２０の製造工程について説明する。   A manufacturing process of the semiconductor device 20 according to the second embodiment of the present invention will be described with reference to FIG.

図５（ａ）に示すように、半導体素子２１には、回路形成面２１ａにＬＳＩ等の内部回路（図示なし）が形成され、回路形成面２１ａの周縁部に電極パッド２２（図４）が配設され、さらに、電極パッド２２上にバンプ２３が予め形成されている。また、半導体素子２１の外周端面全周に半硬化状態の接着剤２４が予め形成されている。まず、絶縁基板２８に熱硬化性接着剤２６を塗布する。そして、回路形成面２１ａを絶縁基板２８に対向する向きにした状態で半導体素子２１を、絶縁基板２８の上方に配置する。   As shown in FIG. 5A, in the semiconductor element 21, an internal circuit (not shown) such as LSI is formed on the circuit forming surface 21a, and an electrode pad 22 (FIG. 4) is formed on the peripheral portion of the circuit forming surface 21a. Further, bumps 23 are formed in advance on the electrode pads 22. A semi-cured adhesive 24 is formed in advance on the entire outer peripheral end surface of the semiconductor element 21. First, the thermosetting adhesive 26 is applied to the insulating substrate 28. Then, the semiconductor element 21 is disposed above the insulating substrate 28 with the circuit forming surface 21 a facing the insulating substrate 28.

図５（ａ）の工程において、熱硬化性接着剤２６の塗布量は、絶縁基板２８上に半導体素子２１を搭載した後の熱硬化性接着剤２６の濡れ広がりが半導体素子２１の回路形成面２１ａからはみ出ない程度に調製される。また、半硬化状態の接着剤２４は、熱硬化後の接着剤２４ａの濡れ広がりが良好となるように、所定の幅で半導体素子２１の外周端面全周に形成される。   In the process of FIG. 5A, the application amount of the thermosetting adhesive 26 is such that the wetting and spreading of the thermosetting adhesive 26 after mounting the semiconductor element 21 on the insulating substrate 28 is the circuit formation surface of the semiconductor element 21. It is prepared so as not to protrude from 21a. The semi-cured adhesive 24 is formed on the entire outer peripheral end surface of the semiconductor element 21 with a predetermined width so that the wet spread of the adhesive 24a after thermosetting is good.

次に、図５（ｂ）に示すように、回路形成面２１ａを絶縁基板２８に対向させた状態で半導体素子２１が絶縁基板２８に押圧される圧力により、熱硬化性接着剤２６は濡れ広がる。このとき、熱硬化性接着剤２６ａは半導体素子２１の領域よりも狭い領域で濡れ広がっている。そして、この状態の熱硬化性接着剤２６ａを硬化させるために加熱する。熱硬化性接着剤２６ａの硬化により、半導体素子２１が絶縁基板２８に固定される。   Next, as shown in FIG. 5B, the thermosetting adhesive 26 is spread by the pressure by which the semiconductor element 21 is pressed against the insulating substrate 28 with the circuit forming surface 21a facing the insulating substrate 28. . At this time, the thermosetting adhesive 26 a spreads in a region narrower than the region of the semiconductor element 21. And it heats in order to harden the thermosetting adhesive agent 26a of this state. The semiconductor element 21 is fixed to the insulating substrate 28 by the curing of the thermosetting adhesive 26a.

さらに、図５（ｂ）の工程では、フリップチップボンディングにより、電極パッド２２と絶縁基板２８上の外部電極パッド２７とがバンプ２３ａにより電気的に接続される。   Further, in the step of FIG. 5B, the electrode pad 22 and the external electrode pad 27 on the insulating substrate 28 are electrically connected by the bump 23a by flip chip bonding.

図５（ｃ）に示すように、半導体素子２１の外周端面全周に形成した半硬化状態の接着剤２４が熱硬化性接着剤２６ａと共に熱硬化されて接着剤２４ａとなり、絶縁基板２８上に固定された半導体素子２１の外周において熱硬化性接着剤２６ａと一体的に形成される。半硬化状態の接着剤２４は加熱により流動性を取り戻して半導体素子２１裏面と熱硬化性接着剤２６ａの隙間を埋めている。   As shown in FIG. 5C, the semi-cured adhesive 24 formed on the entire outer periphery of the semiconductor element 21 is thermally cured together with the thermosetting adhesive 26a to form the adhesive 24a. The outer periphery of the fixed semiconductor element 21 is formed integrally with the thermosetting adhesive 26a. The semi-cured adhesive 24 regains fluidity by heating and fills the gap between the back surface of the semiconductor element 21 and the thermosetting adhesive 26a.

さらに、図６に示すように、所定の樹脂封止工程を行うことにより、封止樹脂２５にて、絶縁基板２８に固定した半導体素子２１を封止する。さらに、他の配線基板（マザーボード等）への接続のため、絶縁基板２８の底面に複数の半田ボール２９を配置することによって半導体装置２０が完成される。   Furthermore, as shown in FIG. 6, the semiconductor element 21 fixed to the insulating substrate 28 is sealed with a sealing resin 25 by performing a predetermined resin sealing step. Further, the semiconductor device 20 is completed by disposing a plurality of solder balls 29 on the bottom surface of the insulating substrate 28 for connection to another wiring board (such as a mother board).

図６の半導体装置２０によれば、半導体素子２１の外周端面に予め接着剤を半硬化状態で形成しておくことによって、絶縁基板上における接着剤の濡れ広がりを抑えるとともに、半導体素子２１の外周端面の接着剤が熱によって流動性を取り戻すことによって、絶縁基板と半導体素子の隙間に空間のない、半導体素子表面に這い上がらない良好なフィレットを形成することができる。   According to the semiconductor device 20 of FIG. 6, the adhesive is preliminarily formed on the outer peripheral end face of the semiconductor element 21 in a semi-cured state, thereby suppressing the wetting and spreading of the adhesive on the insulating substrate and the outer periphery of the semiconductor element 21. When the adhesive on the end surface regains fluidity by heat, a good fillet that does not crawl on the surface of the semiconductor element without a space between the insulating substrate and the semiconductor element can be formed.

また、半硬化状態の接着剤２４の幅を調整することによって、フィレットの濡れ広がりを制御することができるので、半導体装置２０の小型化を実現できる。半硬化状態の接着剤２４は、半硬化時は比較的高い硬度を持たせることによって、半導体素子２１のキャリアとして使用され、チップクラックなどを防止することができ、半導体装置２０の薄型化を実現できる。   In addition, by adjusting the width of the semi-cured adhesive 24, the wetting and spreading of the fillet can be controlled, so that the semiconductor device 20 can be downsized. The semi-cured adhesive 24 is used as a carrier of the semiconductor element 21 by having a relatively high hardness when semi-cured, and can prevent chip cracks and the like, and realize a thin semiconductor device 20. it can.

図６の半導体装置２０では、一個の半導体素子２１のみを絶縁基板２８上に搭載している例を説明したが、本発明はこの実施態様に限定されるものではなく、配線基板上に複数個の半導体素子を搭載してもよい。その場合、複数個の半導体素子と配線基板との接続は、フリップチップボンディング、ＴＡＢ（tape automated bonding）テープ、ワイヤボンディング等により行う。また、その場合、全ての半導体素子の外周端面に半硬化状態の接着剤を形成する必要はなく、小型化、薄型化を実現したい半導体素子のみに形成すればよい。   In the semiconductor device 20 of FIG. 6, the example in which only one semiconductor element 21 is mounted on the insulating substrate 28 has been described. However, the present invention is not limited to this embodiment, and a plurality of elements are formed on the wiring substrate. The semiconductor element may be mounted. In this case, the connection between the plurality of semiconductor elements and the wiring board is performed by flip chip bonding, TAB (tape automated bonding) tape, wire bonding, or the like. In that case, it is not necessary to form a semi-cured adhesive on the outer peripheral end faces of all the semiconductor elements, and they may be formed only on the semiconductor elements to be reduced in size and thickness.

次に、図７は、本発明の第３の実施形態に係る半導体装置に用いられる半硬化接着剤を示す図である。図８は、本発明の第３の実施形態に係る半導体装置の製造工程を説明するための図である。   Next, FIG. 7 is a diagram showing a semi-cured adhesive used in the semiconductor device according to the third embodiment of the present invention. FIG. 8 is a diagram for explaining a manufacturing process of the semiconductor device according to the third embodiment of the present invention.

図７の（ａ）は本発明の第３の実施形態の半導体装置における半導体素子３１の上面図であり、図７の（ｂ）は半導体素子３１の側断面図である。   FIG. 7A is a top view of the semiconductor element 31 in the semiconductor device according to the third embodiment of the present invention, and FIG. 7B is a side sectional view of the semiconductor element 31.

図７に示すように、半導体素子３１は回路形成面３１ａの周縁部に複数の電極パッド３２が配設されている。電極パッド３２は半導体素子３１内の回路を外部端子と接続するために設けられ、半導体素子３１と外部の回路との間で電気的な信号のやりとりが電極パッド３２を介して行われる。   As shown in FIG. 7, the semiconductor element 31 is provided with a plurality of electrode pads 32 on the periphery of the circuit formation surface 31a. The electrode pad 32 is provided to connect a circuit in the semiconductor element 31 to an external terminal, and electrical signals are exchanged between the semiconductor element 31 and an external circuit via the electrode pad 32.

半導体素子３１の外周端面全周に半硬化接着剤３４が予め形成される。さらに、半導体素子３１の裏面３１ｂに半硬化接着剤３６が予め形成される。本実施形態の半硬化接着剤３４及び３６の好適な材料として、熱硬化性エポキシ樹脂等を用いることができる。これらの半硬化接着剤３４及び３６は、図１を用いて説明した半硬化接着剤１４と同様の接着剤を用いることができる。   A semi-cured adhesive 34 is formed in advance on the entire outer peripheral end surface of the semiconductor element 31. Further, a semi-cured adhesive 36 is formed in advance on the back surface 31 b of the semiconductor element 31. As a suitable material for the semi-cured adhesives 34 and 36 of the present embodiment, a thermosetting epoxy resin or the like can be used. As these semi-cured adhesives 34 and 36, the same adhesive as the semi-cured adhesive 14 described with reference to FIG. 1 can be used.

本実施形態の半導体装置３０の構成は、図３を用いて説明した半導体装置１０の構成と基本的に同一であるので図示を省略する。但し、熱硬化性接着剤１６を絶縁基板１８に塗布する代りに、半硬化接着剤３６を半導体素子３１の裏面に予め形成しておく。   The configuration of the semiconductor device 30 of this embodiment is basically the same as the configuration of the semiconductor device 10 described with reference to FIG. However, instead of applying the thermosetting adhesive 16 to the insulating substrate 18, a semi-curing adhesive 36 is formed in advance on the back surface of the semiconductor element 31.

半導体装置３０は、回路形成面３１ａに複数の電極パッド３２を配設した半導体素子３１と、半導体素子３１の外周端面全周に設けた半硬化接着剤３４と、半導体素子３１の裏面３１ｂに設けた半硬化接着剤３６と、半硬化接着剤３６を用いて半導体素子３１が固定される絶縁基板３８と、電極パッド３２と絶縁基板３８上の外部電極パッドとを電気的に接続するワイヤと、絶縁基板３８上に固定された半導体素子３１を封止する封止樹脂と、絶縁基板３８の裏面に配設された複数の半田ボールとから構成される。半硬化接着剤３４が半硬化接着剤３６とともに加熱により硬化され、絶縁基板３８上に固定された半導体素子３１の外周において半硬化接着剤３６と一体的に形成される。   The semiconductor device 30 includes a semiconductor element 31 having a plurality of electrode pads 32 disposed on a circuit forming surface 31 a, a semi-cured adhesive 34 provided on the entire outer peripheral end surface of the semiconductor element 31, and a back surface 31 b of the semiconductor element 31. A semi-cured adhesive 36, an insulating substrate 38 to which the semiconductor element 31 is fixed using the semi-cured adhesive 36, a wire for electrically connecting the electrode pad 32 and an external electrode pad on the insulating substrate 38, It is composed of a sealing resin for sealing the semiconductor element 31 fixed on the insulating substrate 38 and a plurality of solder balls disposed on the back surface of the insulating substrate 38. The semi-cured adhesive 34 is cured by heating together with the semi-cured adhesive 36 and is integrally formed with the semi-cured adhesive 36 on the outer periphery of the semiconductor element 31 fixed on the insulating substrate 38.

本実施形態の封止樹脂の好適な材料として、熱硬化性エポキシ樹脂等を用いることができる。   As a suitable material for the sealing resin of this embodiment, a thermosetting epoxy resin or the like can be used.

図８を用いて、本発明の第３の実施形態に係る半導体装置３０の製造工程について説明する。   A manufacturing process of the semiconductor device 30 according to the third embodiment of the present invention will be described with reference to FIG.

図８（ａ）に示すように、半導体素子３１には、回路形成面３１ａにＬＳＩ等の内部回路（図示なし）が形成され、回路形成面３１ａの周縁部に複数の電極パッド３２（図７）が予め配設されている。また、半導体素子３１の外周端面全周には半硬化接着剤３４が、裏面３１ｂには半硬化接着剤３６が予め形成されている。まず、回路形成面３１ａを上向き、裏面３１ｂを下向き（絶縁基板３８に対向する向き）にした状態で半導体素子３１を、絶縁基板３８の上方に配置する。   As shown in FIG. 8A, in the semiconductor element 31, an internal circuit (not shown) such as an LSI is formed on the circuit forming surface 31a, and a plurality of electrode pads 32 (FIG. 7) are formed on the peripheral portion of the circuit forming surface 31a. ) Are arranged in advance. A semi-cured adhesive 34 is formed in advance on the entire outer peripheral end surface of the semiconductor element 31, and a semi-cured adhesive 36 is formed on the back surface 31b. First, the semiconductor element 31 is disposed above the insulating substrate 38 with the circuit forming surface 31a facing upward and the back surface 31b facing downward (facing the insulating substrate 38).

図８（ａ）の工程において、半硬化接着剤３６の塗布量は、絶縁基板３８上に半導体素子３１を搭載した後の半硬化接着剤３６の濡れ広がりが半導体素子３１の裏面３１ｂからはみ出ない程度に調製される。また、半硬化接着剤３４は、熱硬化後の接着剤３４ａの濡れ広がりが良好となるように、所定の幅で半導体素子３１の外周端面全周に形成される。   In the process of FIG. 8A, the amount of the semi-cured adhesive 36 applied is such that the wet spread of the semi-cured adhesive 36 after mounting the semiconductor element 31 on the insulating substrate 38 does not protrude from the back surface 31 b of the semiconductor element 31. Prepared to the extent. Further, the semi-cured adhesive 34 is formed on the entire outer peripheral end surface of the semiconductor element 31 with a predetermined width so that the wet spread of the adhesive 34a after heat curing is good.

次に、図８（ｂ）に示すように、半導体素子３１が絶縁基板３８に押圧され、半硬化接着剤３６は僅かに濡れ広がる。そして、この状態の半硬化接着剤３６ａと半硬化接着剤３４を硬化させるために加熱する。半硬化接着剤３６ａの硬化により、半導体素子３１が絶縁基板３８に固定される。   Next, as shown in FIG. 8B, the semiconductor element 31 is pressed against the insulating substrate 38, and the semi-cured adhesive 36 is slightly spread. And in order to harden the semi-hardened adhesive 36a and the semi-hardened adhesive 34 in this state, it heats. The semiconductor element 31 is fixed to the insulating substrate 38 by the curing of the semi-cured adhesive 36a.

図８（ｃ）に示すように、半導体素子３１の外周端面全周に形成した半硬化接着剤３４が半硬化接着剤３６ａと共に熱硬化されて接着剤３４ａとなり、絶縁基板３８上に固定された半導体素子３１の外周において接着剤３６ａと一体的に形成される。半硬化接着剤３４は加熱により流動性を取り戻して半導体素子３１裏面と半硬化接着剤３６ａの隙間を埋めている。   As shown in FIG. 8C, the semi-cured adhesive 34 formed on the entire outer peripheral end surface of the semiconductor element 31 is thermally cured together with the semi-cured adhesive 36a to become the adhesive 34a, and is fixed on the insulating substrate 38. It is integrally formed with the adhesive 36 a on the outer periphery of the semiconductor element 31. The semi-cured adhesive 34 regains fluidity by heating and fills the gap between the back surface of the semiconductor element 31 and the semi-cured adhesive 36a.

さらに、図３の実施形態と同様に、ワイヤボンディング工程を行うことにより、電極パッド３２と絶縁基板３８上の外部電極パッドをワイヤにより電気的に接続する。次に、所定の樹脂封止工程を行うことにより、封止樹脂にて、絶縁基板３８に固定した半導体素子３１及びワイヤを封止する。さらに、他の配線基板（マザーボード等）への接続のため、絶縁基板３８の底面に複数の半田ボールを配置することによって半導体装置３０が完成される。   Further, as in the embodiment of FIG. 3, by performing a wire bonding process, the electrode pads 32 and the external electrode pads on the insulating substrate 38 are electrically connected by wires. Next, by performing a predetermined resin sealing step, the semiconductor element 31 and the wires fixed to the insulating substrate 38 are sealed with a sealing resin. Furthermore, the semiconductor device 30 is completed by disposing a plurality of solder balls on the bottom surface of the insulating substrate 38 for connection to another wiring board (such as a mother board).

この半導体装置３０によれば、半導体素子３１の外周端面に予め接着剤を半硬化状態で形成しておくことによって、絶縁基板上における接着剤の濡れ広がりを抑えるとともに、半導体素子３１の外周端面の接着剤が熱によって流動性を取り戻すことによって、絶縁基板と半導体素子の隙間に空間のない、半導体素子表面に這い上がらない良好なフィレットを形成することができる。   According to this semiconductor device 30, the adhesive is preliminarily formed on the outer peripheral end surface of the semiconductor element 31 in a semi-cured state, thereby suppressing the wetting and spreading of the adhesive on the insulating substrate and the outer peripheral end surface of the semiconductor element 31. When the adhesive regains fluidity by heat, a good fillet can be formed in which there is no space in the gap between the insulating substrate and the semiconductor element and the surface of the semiconductor element does not crawl up.

また、半硬化状態の接着剤３４の幅を調整することによって、フィレットの濡れ広がりを制御することができるので、半導体装置３０の小型化を実現できる。半硬化状態の接着剤３４は、半硬化時は比較的高い硬度を持たせることによって、半導体素子３１のキャリアとして使用され、チップクラックなどを防止することができ、半導体装置の薄型化を実現できる。   Moreover, since the wetting and spreading of the fillet can be controlled by adjusting the width of the semi-cured adhesive 34, the semiconductor device 30 can be downsized. The semi-cured adhesive 34 is used as a carrier for the semiconductor element 31 by imparting a relatively high hardness during semi-curing, thereby preventing chip cracks and the like and realizing a thin semiconductor device. .

この半導体装置３０では、一個の半導体素子３１のみを絶縁基板３８上に搭載している例を説明したが、本発明はこの実施態様に限定されるものではなく、配線基板上に複数個の半導体素子を搭載してもよい。その場合、複数個の半導体素子と配線基板との接続は、フリップチップボンディング、ＴＡＢ（tape automated bonding）テープ、ワイヤボンディング等により行う。また、その場合、全ての半導体素子の外周端面に半硬化状態の接着剤を形成する必要はなく、小型化、薄型化を実現したい半導体素子のみに形成すればよい。   In this semiconductor device 30, the example in which only one semiconductor element 31 is mounted on the insulating substrate 38 has been described. However, the present invention is not limited to this embodiment, and a plurality of semiconductor elements are formed on the wiring substrate. An element may be mounted. In this case, the connection between the plurality of semiconductor elements and the wiring board is performed by flip chip bonding, TAB (tape automated bonding) tape, wire bonding, or the like. In that case, it is not necessary to form a semi-cured adhesive on the outer peripheral end faces of all the semiconductor elements, and they may be formed only on the semiconductor elements to be reduced in size and thickness.

本発明の第１の実施形態に係る半導体装置に用いられる半硬化接着剤を示す図である。It is a figure which shows the semi-hardened adhesive agent used for the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の製造工程を説明するための図である。It is a figure for demonstrating the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の側断面図である。1 is a side sectional view of a semiconductor device according to a first embodiment of the present invention. 本発明の第２の実施形態に係る半導体装置に用いられる半硬化接着剤を示す図である。It is a figure which shows the semi-hardened adhesive agent used for the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施形態に係る半導体装置の製造工程を説明するための図である。It is a figure for demonstrating the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施形態に係る半導体装置の側断面図である。It is a sectional side view of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置に用いられる半硬化接着剤を示す図である。It is a figure which shows the semi-hardened adhesive agent used for the semiconductor device which concerns on the 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の製造工程を説明するための図である。It is a figure for demonstrating the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention.

符号の説明Explanation of symbols

１０、２０、３０ 半導体装置
１１、２１、３１ 半導体素子
１２、２２、３２ 電極パッド
１３ ワイヤ
１４、２４、３４、３６ 半硬化接着剤
１５、２５ 封止樹脂
１６、２６ 熱硬化性接着剤
１７、２７ 外部電極パッド
１８、２８、３８ 絶縁基板
１９、２９ 半田ボール
２３ バンプ 10, 20, 30 Semiconductor device 11, 21, 31 Semiconductor element 12, 22, 32 Electrode pad 13 Wire 14, 24, 34, 36 Semi-curing adhesive 15, 25 Sealing resin 16, 26 Thermosetting adhesive 17, 27 External electrode pad 18, 28, 38 Insulating substrate 19, 29 Solder ball 23 Bump

Claims (5)

外周端面全周に接着剤が配設された半導体素子と、
熱硬化性接着剤を介して前記半導体素子が固定される絶縁基板と、
前記絶縁基板と前記半導体素子とを封止する封止樹脂と
を備え、前記半導体素子の外周及び前記絶縁基板との間において、前記半導体素子の外周端面全周に配設された前記接着剤と前記熱硬化性接着剤とが一体的に形成されていることを特徴とする半導体装置。 A semiconductor element in which an adhesive is disposed all around the outer peripheral end surface;
An insulating substrate to which the semiconductor element is fixed via a thermosetting adhesive;
A sealing resin for sealing the insulating substrate and the semiconductor element; and the adhesive disposed on the entire outer peripheral end surface of the semiconductor element between the outer periphery of the semiconductor element and the insulating substrate. A semiconductor device, wherein the thermosetting adhesive is integrally formed. 前記半導体素子の外周端面全周に配設された前記接着剤は半硬化接着剤であることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the adhesive disposed on the entire outer peripheral end surface of the semiconductor element is a semi-cured adhesive. 半導体素子の外周端面全周に半硬化状態の接着剤を配設する工程と、
熱硬化性接着剤を絶縁基板に塗布する工程と、
前記半導体素子を前記熱硬化性接着剤を介して前記絶縁基板に押圧する工程と、
前記熱硬化性接着剤を加熱して硬化させることにより前記半導体素子を前記絶縁基板に固定する工程と、
前記半硬化状態の接着剤を熱硬化し、前記半導体素子の外周及び前記半導体素子と前記絶縁基板との接合部を前記熱硬化性接着剤と共に封止する工程と
を含むことを特徴とする半導体装置の製造方法。 A step of disposing a semi-cured adhesive around the outer peripheral end surface of the semiconductor element;
Applying a thermosetting adhesive to the insulating substrate;
Pressing the semiconductor element against the insulating substrate via the thermosetting adhesive;
Fixing the semiconductor element to the insulating substrate by heating and curing the thermosetting adhesive; and
Heat curing the semi-cured adhesive, and sealing the outer periphery of the semiconductor element and the joint between the semiconductor element and the insulating substrate together with the thermosetting adhesive. Device manufacturing method. 半導体素子の外周端面全周に半硬化状態の接着剤を配設する工程と、
熱硬化性接着剤を絶縁基板に塗布する工程と、
前記半導体素子の外部電極形成面を前記絶縁基板に対向させて、前記半導体素子を前記熱硬化性接着剤を介して前記絶縁基板に押圧する工程と、
前記熱硬化性接着剤を加熱して硬化させると共に、前記外部電極を前記絶縁基板上の電極に接合して、前記半導体素子を前記絶縁基板に固定する工程と、
前記半硬化状態の接着剤を熱硬化し、前記半導体素子の外周及び前記半導体素子と前記絶縁基板との接合部を前記熱硬化性接着剤と共に封止する工程と
を含むことを特徴とする半導体装置の製造方法。 A step of disposing a semi-cured adhesive around the outer peripheral end surface of the semiconductor element;
Applying a thermosetting adhesive to the insulating substrate;
The external electrode forming surface of the semiconductor element is opposed to the insulating substrate, and the semiconductor element is pressed against the insulating substrate via the thermosetting adhesive;
Heating and curing the thermosetting adhesive, bonding the external electrode to an electrode on the insulating substrate, and fixing the semiconductor element to the insulating substrate;
Heat curing the semi-cured adhesive, and sealing the outer periphery of the semiconductor element and the joint between the semiconductor element and the insulating substrate together with the thermosetting adhesive. Device manufacturing method. 半導体素子の外周端面全周に第１の半硬化接着剤を配設する工程と、
前記半導体素子の回路形成面と反対側の裏面に第２の半硬化接着剤を配設する工程と、
前記半導体素子を前記第２の半硬化接着剤を介して絶縁基板に押圧する工程と、
前記第１の半硬化接着剤と前記第２の半硬化接着剤を同時に加熱して硬化させることにより前記半導体素子を前記絶縁基板に固定し、前記半導体素子の外周及び前記半導体素子と前記絶縁基板との接合部を封止する工程と
を含むことを特徴とする半導体装置の製造方法。
Disposing a first semi-cured adhesive all around the outer peripheral end surface of the semiconductor element;
Disposing a second semi-cured adhesive on the back surface opposite to the circuit forming surface of the semiconductor element;
Pressing the semiconductor element against the insulating substrate via the second semi-cured adhesive;
The semiconductor element is fixed to the insulating substrate by simultaneously heating and curing the first semi-curing adhesive and the second semi-curing adhesive, and the outer periphery of the semiconductor element and the semiconductor element and the insulating substrate And a step of sealing the joint with the semiconductor device.
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