JP2013048171A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

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JP2013048171A
JP2013048171A JP2011186160A JP2011186160A JP2013048171A JP 2013048171 A JP2013048171 A JP 2013048171A JP 2011186160 A JP2011186160 A JP 2011186160A JP 2011186160 A JP2011186160 A JP 2011186160A JP 2013048171 A JP2013048171 A JP 2013048171A
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chip
adhesive member
mounting substrate
semiconductor device
chip mounting
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Kinichi Kumagai
欣一 熊谷
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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    • HELECTRICITY
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    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/732Location after the connecting process
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    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909Post-treatment of the layer connector or bonding area
    • H01L2224/83951Forming additional members, e.g. for reinforcing, fillet sealant
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    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
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    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which inhibits warp of a chip.SOLUTION: A semiconductor device manufacturing method comprises: a lateral face adhesive member formation process of forming a lateral face adhesive member on a lateral face of a chip on which an integrated circuit is provided on a surface; a first adhesion process of pressing the lateral face adhesive member to a chip mounting substrate while pressing the chip to the chip mounting substrate via a rear face adhesive member arranged on a rear face of the chip to adhere the lateral face adhesive member to the chip mounting substrate; and a second adhesion process of heating the rear face adhesive member after the first adhesion process to adhere the chip to the chip mounting substrate.

Description

本発明は、半導体装置の製造方法および半導体装置に関する。   The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

半導体装置は、半導体チップと、半導体チップが搭載されたチップ搭載基板とを有している。半導体チップは、接着部材によりチップ搭載基板に接着される。   The semiconductor device has a semiconductor chip and a chip mounting substrate on which the semiconductor chip is mounted. The semiconductor chip is bonded to the chip mounting substrate by an adhesive member.

特開2006−32625号公報JP 2006-32625 A

近年、半導体装置の小型化や半導体チップのスタック化に伴い、半導体チップは薄層化している。半導体チップは、薄層化されると反りやすくなる。このようなチップをチップ搭載基板に密着させることは困難であり、ボンディングワイヤのショートやチップクラック等の問題が生じている。   In recent years, semiconductor chips have become thinner with the miniaturization of semiconductor devices and the stacking of semiconductor chips. A semiconductor chip tends to warp when it is thinned. It is difficult to bring such a chip into close contact with the chip mounting substrate, causing problems such as shorting of bonding wires and chip cracks.

上記の問題を解決するために、本製造方法の一観点によれば、集積回路が表面に設けられたチップの側面に側面接着部材を形成する側面接着部材の形成工程と、前記チップの裏面に配置された裏面接着部材を介して前記チップをチップ搭載基板に押圧しながら前記側面接着部材を前記チップ搭載基板に押圧して前記側面接着部材を前記チップ搭載基板に接着する第1の接着工程と、前記第1の接着工程の後に前記裏面接着部材を加熱して前記チップ搭載基板に前記チップを接着する第2の接着工程とを有する半導体装置の製造方法が提供される。   In order to solve the above problem, according to one aspect of the present manufacturing method, a side surface adhesive member forming step for forming a side surface adhesive member on a side surface of a chip on which an integrated circuit is provided on the surface, and a back surface of the chip A first bonding step of pressing the side surface adhesive member against the chip mounting substrate while pressing the chip against the chip mounting substrate via the disposed back surface bonding member to bond the side surface bonding member to the chip mounting substrate; There is provided a method for manufacturing a semiconductor device, comprising: a second bonding step of bonding the chip to the chip mounting substrate by heating the back surface bonding member after the first bonding step.

実施の形態によれば、薄層化されたチップの反りを抑制する半導体装置の製造方法が提供される。   According to the embodiment, a method of manufacturing a semiconductor device that suppresses warpage of a thinned chip is provided.

実施の形態1の半導体装置の製造方法を説明する工程断面図である。FIG. 10 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device of the first embodiment. 実施の形態1の半導体装置の製造方法を説明する工程断面図である。FIG. 10 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device of the first embodiment. 実施の形態1の半導体装置の製造方法を説明する工程断面図である。FIG. 10 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device of the first embodiment. 実施の形態1の半導体装置の製造方法を説明する工程断面図である。FIG. 10 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device of the first embodiment. 側面接着部材が形成されたチップの構成図である。It is a block diagram of the chip | tip in which the side surface adhesion member was formed. コレットの構成図である。It is a block diagram of a collet. 図2に示す工程を説明する平面図である。It is a top view explaining the process shown in FIG. 側面接着部材を用いない半導体装置の製造方法を説明する工程断面図である。It is process sectional drawing explaining the manufacturing method of the semiconductor device which does not use a side surface adhesion member. 側面接着部材を用いない半導体装置の製造方法を説明する工程断面図である。It is process sectional drawing explaining the manufacturing method of the semiconductor device which does not use a side surface adhesion member. 側面接着部材の変形例を説明する図である。It is a figure explaining the modification of a side surface adhesion member. 側面接着部材の変形例を説明する図である。It is a figure explaining the modification of a side surface adhesion member. 図1を参照して説明した側面接着部材の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the side surface adhesion member demonstrated with reference to FIG. コレットの変形例の下面図である。It is a bottom view of the modification of a collet. 実施の形態2の半導体装置の製造方法を説明する工程断面図である。FIG. 10 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device of the second embodiment. 実施の形態2の半導体装置の製造方法を説明する工程断面図である。FIG. 10 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device of the second embodiment. チップの部分断面図の一例である。It is an example of the fragmentary sectional view of a chip.

以下、図面にしたがって本発明の実施の形態について説明する。但し、本発明の技術的範囲はこれらの実施の形態に限定されず、特許請求の範囲に記載された事項とその均等物まで及ぶものである。尚、図面が異なっても対応する部分には同一の符号を付し、その説明を省略する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof. Note that, even if the drawings are different, corresponding parts are denoted by the same reference numerals, and description thereof is omitted.

(実施の形態1)
図1乃至4は、本実施の形態の半導体装置の製造方法を説明する工程断面図である。
(Embodiment 1)
1 to 4 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to the present embodiment.

(1)側面接着部材の形成工程(図1(a)〜(d))
集積回路(図示せず)が表面に形成されたウエハー状の半導体基板(例えば、シリコン基板)2の裏面にダイシングフィルム4を貼り付けた後、この半導体基板2をブレード6で切断する(図1(a)参照)。これにより、集積回路が表面に形成された複数のチップ8が形成される。チップ8の厚さは、例えば10μm以上100μm以下である。尚、図1(a)乃至(d)には、ウエハー状の半導体基板2の一部が示されている。
(1) Step of forming side surface adhesive member (FIGS. 1A to 1D)
A dicing film 4 is attached to the back surface of a wafer-like semiconductor substrate (for example, a silicon substrate) 2 on which an integrated circuit (not shown) is formed, and then the semiconductor substrate 2 is cut with a blade 6 (FIG. 1). (See (a)). Thereby, a plurality of chips 8 having integrated circuits formed on the surface are formed. The thickness of the chip 8 is, for example, 10 μm or more and 100 μm or less. 1A to 1D show a part of the wafer-like semiconductor substrate 2.

半導体基板2の切断により、各チップ8の間には、ブレード6と略同じ幅の溝10が形成される(図1(b)参照)。この溝10に、例えばスピンコートまたは真空印刷によりペースト状の熱硬化性接着部材12(例えば、エポキシ樹脂等の熱硬化性樹脂)を充填する。   By cutting the semiconductor substrate 2, a groove 10 having a width substantially the same as that of the blade 6 is formed between the chips 8 (see FIG. 1B). The groove 10 is filled with a paste-like thermosetting adhesive member 12 (for example, a thermosetting resin such as an epoxy resin) by spin coating or vacuum printing, for example.

この熱硬化性接着部材12を加熱して、半硬化接着部材14を形成する。半硬化接着部材14は、ペースト状の熱硬化性接着部材に含まれる低分子量の化合物が加熱処理により高分子に変化する途中の中間物である。半硬化接着部材は、熱硬化性接着部材を短時間加熱して形成される所謂B−ステージの熱硬化性樹脂である。   The thermosetting adhesive member 12 is heated to form a semi-cured adhesive member 14. The semi-cured adhesive member 14 is an intermediate in the middle of changing a low molecular weight compound contained in the paste-like thermosetting adhesive member into a polymer by heat treatment. The semi-curing adhesive member is a so-called B-stage thermosetting resin formed by heating a thermosetting adhesive member for a short time.

この半硬化接着部材14の中央部を、図1(c)に示すように、半導体基板2の切断に用いたブレード6より幅の狭いブレード16で切断する。これにより、図1(d)に示すように、チップ8の側面に固形接着部材18(以下、側面接着部材と呼ぶ)が形成される。以上の説明から明らかなように、側面接着部材18は、チップ8の側面に接着されている。   The central portion of the semi-cured adhesive member 14 is cut with a blade 16 that is narrower than the blade 6 used for cutting the semiconductor substrate 2 as shown in FIG. Thereby, as shown in FIG. 1D, a solid adhesive member 18 (hereinafter referred to as a side adhesive member) is formed on the side surface of the chip 8. As is clear from the above description, the side surface adhesive member 18 is bonded to the side surface of the chip 8.

図5(a)は、側面接着部材18が形成されたチップ8の平面図である。図5(b)は、図5(a)のVB-VB線に沿った断面図である。   FIG. 5A is a plan view of the chip 8 on which the side surface adhesive member 18 is formed. FIG. 5B is a cross-sectional view taken along the line VB-VB in FIG.

チップ8の表面20(図5(b)参照)には、集積回路が形成されている。更に、このチップ8の表面20には、図5(a)に示すように、チップ8の外周に沿って複数の電極パッド22が設けられている。表面20の下側の領域は、分割された半導体基板2aである。   An integrated circuit is formed on the surface 20 of the chip 8 (see FIG. 5B). Further, as shown in FIG. 5A, a plurality of electrode pads 22 are provided on the surface 20 of the chip 8 along the outer periphery of the chip 8. The lower region of the surface 20 is a divided semiconductor substrate 2a.

更に、集積回路の表面20には、ポリイミド等の保護膜(図示せず)が設けられている。電極パッド22上のポリイミド膜は除去され、ボンディングワイヤが接続されるようになっている。尚、図5(b)以外の図面では、集積回路の表面20は省略されている。   Further, a protective film (not shown) such as polyimide is provided on the surface 20 of the integrated circuit. The polyimide film on the electrode pad 22 is removed, and a bonding wire is connected. In the drawings other than FIG. 5B, the surface 20 of the integrated circuit is omitted.

(2)第1の接着工程(図2(a)〜(c))
次に、図2(a)に示すように、チップ搭載基板(例えば、ガラスエポキシ基板やセラミック基板)24をダイボンダー(図示せず)にセットする。このチップ搭載基板24のチップ搭載領域に、接着部材26(以下、裏面接着部材と呼ぶ)を塗布する。裏面接着部材26は、例えばペースト状のエポキシ樹脂(または、アクリル樹脂、ポリイミド樹脂など)である。
(2) First bonding step (FIGS. 2A to 2C)
Next, as shown in FIG. 2A, a chip mounting substrate (for example, a glass epoxy substrate or a ceramic substrate) 24 is set on a die bonder (not shown). An adhesive member 26 (hereinafter referred to as a back surface adhesive member) is applied to the chip mounting area of the chip mounting substrate 24. The back surface adhesive member 26 is, for example, a paste-like epoxy resin (or acrylic resin, polyimide resin, or the like).

次に、チップ8をダイシングフィルム4から取り外し、図2(a)に示すように、ダイボンダーのコレット28に吸着する。図6(a)は、コレット28の下面図である。図6(b)は、図6(a)のVIB-VIB線に沿った断面図である。   Next, the chip 8 is removed from the dicing film 4 and adsorbed on the collet 28 of the die bonder as shown in FIG. FIG. 6A is a bottom view of the collet 28. FIG. 6B is a cross-sectional view taken along the line VIB-VIB in FIG.

図6(a)に示すように、コレット28は、枠状突出部30と、枠状突出部30の外周に接する複数の突起部32とを有している。枠状突出部30の内側には、排気口34が設けられている。この排気口34から、枠状突出部30内の空気が排気される。これにより、チップ8がコレット28に吸着される。枠状突出部30の外縁は、チップ8の外縁に略一致するように設定されている。   As shown in FIG. 6A, the collet 28 has a frame-shaped protrusion 30 and a plurality of protrusions 32 that are in contact with the outer periphery of the frame-shaped protrusion 30. An exhaust port 34 is provided inside the frame-shaped protrusion 30. The air in the frame-shaped protrusion 30 is exhausted from the exhaust port 34. Thereby, the chip 8 is adsorbed to the collet 28. The outer edge of the frame-shaped protrusion 30 is set so as to substantially coincide with the outer edge of the chip 8.

図6(b)に示すように、突起部32は、枠状突出部30より更に突出している。図2(a)に示すように、この突起部32に側面接着部材18が接触した状態で、チップ8はコレット28に吸着される。   As shown in FIG. 6B, the protrusion 32 protrudes further than the frame-shaped protrusion 30. As shown in FIG. 2A, the chip 8 is adsorbed to the collet 28 in a state where the side surface adhesive member 18 is in contact with the protrusion 32.

図7は、図2に示す工程を説明する平面図である。図7(a)は、コレット28によってチップ搭載基板24の上方に配置されたチップ8を見た図である。図7(a)は、図2(a)に対応している。   FIG. 7 is a plan view for explaining the process shown in FIG. FIG. 7A is a view of the chip 8 disposed above the chip mounting substrate 24 by the collet 28. FIG. 7A corresponds to FIG.

図2(a)および図7(a)に示すように、チップ8はコレット28に吸着され、裏面接着部材26の真上に配置される。   As shown in FIG. 2A and FIG. 7A, the chip 8 is adsorbed by the collet 28 and disposed immediately above the back surface adhesive member 26.

次に、図2(b)に示すように、ダイボンダーに内蔵されたヒータ36でコレット28を加熱しながら、チップ8をチップ搭載基板24に押圧する。これにより、チップ8は、その裏面に配置された裏面接着部材26を介して押圧される。この時、裏面接着部材26が、チップ8とチップ搭載基板24の間を満たすように押し広げられる。尚、コレット28の加熱温度は、例えば100〜150℃である。   Next, as shown in FIG. 2B, the chip 8 is pressed against the chip mounting substrate 24 while the collet 28 is heated by the heater 36 incorporated in the die bonder. Thereby, the chip 8 is pressed through the back surface adhesive member 26 disposed on the back surface thereof. At this time, the back surface adhesive member 26 is spread so as to fill between the chip 8 and the chip mounting substrate 24. In addition, the heating temperature of the collet 28 is 100-150 degreeC, for example.

図7(b)は、チップ8が、チップ搭載基板24に接触した直後の状態を示している。図7(b)は、図2(b)に対応している。   FIG. 7B shows a state immediately after the chip 8 contacts the chip mounting substrate 24. FIG. 7B corresponds to FIG.

チップ8がコレット28に吸着されると、側面接着部材18と突起部32の接触部38の温度が上昇する(図7(b)参照)。すると、接触部38の側面接着部材18が軟化し、そのタック性(粘着性)が高くなる。このタック性が高くなった側面接着部材18がチップ搭載基板24に押圧され、接触部38の側面接着部材18がチップ搭載基板24に接着される。   When the chip 8 is adsorbed by the collet 28, the temperature of the contact portion 38 between the side surface adhesive member 18 and the protrusion 32 increases (see FIG. 7B). Then, the side surface adhesive member 18 of the contact portion 38 is softened, and the tackiness (adhesiveness) is increased. The side adhesive member 18 having improved tackiness is pressed against the chip mounting substrate 24, and the side adhesive member 18 of the contact portion 38 is bonded to the chip mounting substrate 24.

これによりチップ8は、側面接着部材18を介して、チップ搭載基板24に仮接着される。この接着は一時的なものであり、側面接着部材18は、後述する樹脂封止工程の前に除去される。尚、以上の説明から明らかなように、チップ8の押圧と側面接着部材18の押圧は、略同時に進行する。   As a result, the chip 8 is temporarily bonded to the chip mounting substrate 24 via the side surface adhesive member 18. This adhesion is temporary, and the side surface adhesive member 18 is removed before the resin sealing step described later. As is clear from the above description, the pressing of the chip 8 and the pressing of the side surface adhesive member 18 proceed almost simultaneously.

図2(c)に示すように、チップ8は所定の荷重まで押圧された後、コレット28から分離される。押圧時間は、例えば0.5〜1.0秒である。   As shown in FIG. 2 (c), the chip 8 is pressed to a predetermined load and then separated from the collet 28. The pressing time is, for example, 0.5 to 1.0 seconds.

図7(c)は、コレット28から分離されたチップ8および側面接着部材18を示している。図7(c)は、図2(c)に対応している。側面接着部材18は、半硬化性樹脂である。したがって、側面接着部材18は、コレット28の突起部32で押圧されると、例えば図7(c)に示すように変形する。   FIG. 7C shows the chip 8 and the side adhesive member 18 separated from the collet 28. FIG. 7C corresponds to FIG. The side adhesive member 18 is a semi-curable resin. Therefore, when the side surface adhesive member 18 is pressed by the protrusion 32 of the collet 28, it is deformed as shown in FIG.

図16は、チップ8の部分断面図の一例である。図16に示すように、チップ8は、例えばSTI(Shallow Trench Isolation)絶縁膜60によって周囲を囲われた半導体素子62と、複数の層間絶縁膜64と、層間絶縁膜64に埋め込まれた配線66およびプラグ68を有している。   FIG. 16 is an example of a partial cross-sectional view of the chip 8. As shown in FIG. 16, the chip 8 includes, for example, a semiconductor element 62 surrounded by an STI (Shallow Trench Isolation) insulating film 60, a plurality of interlayer insulating films 64, and a wiring 66 embedded in the interlayer insulating film 64. And a plug 68.

この層間絶縁膜64等の部材は、高温で形成される。このためチップ8には、表面20と半導体基板2の熱膨張係数の違いにより内部応力(以下、チップ内応力と呼ぶ)が発生する。一方、チップ8の厚さは、上述したように極めて薄い(10〜100μm)。このためチップ8は、チップ内応力によって容易に反り返る。   The members such as the interlayer insulating film 64 are formed at a high temperature. For this reason, internal stress (hereinafter referred to as in-chip stress) is generated in the chip 8 due to the difference in thermal expansion coefficient between the surface 20 and the semiconductor substrate 2. On the other hand, the thickness of the chip 8 is extremely thin (10 to 100 μm) as described above. For this reason, the chip 8 easily warps due to the stress in the chip.

本実施の形態では、図2(c)に示すように、側面接着部材18によりチップ8がチップ搭載基板24に仮接着される。このためチップ8がコレット28から分離された後も、チップ8の形状は平坦に保たれる。   In the present embodiment, as shown in FIG. 2C, the chip 8 is temporarily bonded to the chip mounting substrate 24 by the side surface adhesive member 18. For this reason, even after the chip 8 is separated from the collet 28, the shape of the chip 8 is kept flat.

(3)第2の接着工程(図3(a))
次に、チップ8が接着されたチップ搭載基板24を、ヒータ36を有する恒温槽40にセットする。この恒温槽40を用いて、裏面接着部材26を加熱する。加熱温度および加熱時間は、例えば100〜150℃および2時間程度である。
(3) Second bonding step (FIG. 3 (a))
Next, the chip mounting substrate 24 to which the chip 8 is bonded is set in a thermostatic chamber 40 having a heater 36. The back surface adhesive member 26 is heated using the thermostat 40. The heating temperature and the heating time are, for example, about 100 to 150 ° C. and about 2 hours.

この加熱処理によって、裏面接着部材26が硬化する。硬化した裏面接着部材26aにより、チップ8はチップ搭載基板24に強く接着される。   By this heat treatment, the back surface adhesive member 26 is cured. The chip 8 is strongly bonded to the chip mounting substrate 24 by the cured back surface adhesive member 26a.

加熱処理の間、チップ8の側面は、側面接着部材18によりチップ搭載基板24に仮接着されている。このためチップ8は平坦な形状を保ったまま、チップ搭載基板24に接着される。   During the heat treatment, the side surface of the chip 8 is temporarily bonded to the chip mounting substrate 24 by the side surface adhesive member 18. Therefore, the chip 8 is bonded to the chip mounting substrate 24 while maintaining a flat shape.

(4)側面接着部材の剥離工程(図3(b))
次に、図3(b)に示すように、側面接着部材18をチップ搭載基板24およびチップ8から剥離する。
(4) Side surface adhesive member peeling step (FIG. 3B)
Next, as shown in FIG. 3B, the side surface adhesive member 18 is peeled from the chip mounting substrate 24 and the chip 8.

(5)ボンディング工程(図3(c))
次に、チップ搭載基板24の表面に設けられた電極パッド(図示せず)とチップ8の電極パッド22を、ボンディングワイヤ42で接続する。チップ8が平坦なので、ボンディングワイヤ42とチップ8の外周部が接触して、ショートすることはない。
(5) Bonding process (FIG. 3C)
Next, an electrode pad (not shown) provided on the surface of the chip mounting substrate 24 and the electrode pad 22 of the chip 8 are connected by a bonding wire 42. Since the chip 8 is flat, the bonding wire 42 and the outer peripheral portion of the chip 8 are not in contact with each other and short-circuiting occurs.

(6)封止工程および半田ボール形成工程(図4(a)〜(b))
その後、チップ8およびボンディングワイヤ42をモールド樹脂44で封止する。この際図4(a)に示すように、金型(図示せず)に充填されたモールド樹脂44を恒温槽40で加熱して硬化させる。
(6) Sealing step and solder ball forming step (FIGS. 4A to 4B)
Thereafter, the chip 8 and the bonding wire 42 are sealed with a mold resin 44. At this time, as shown in FIG. 4A, the mold resin 44 filled in a mold (not shown) is heated in a constant temperature bath 40 to be cured.

最後に、図4(b)に示すように、チップ搭載基板24の裏面側の電極パッド(図示せず)に、半田ボール46を形成する。裏面側の電極パッドは、ビアによりチップ搭載基板24の表面側の電極パッドに接続されている。以上により、薄層化されたチップ8が反らずに格納された半導体装置37が形成される。   Finally, as shown in FIG. 4B, solder balls 46 are formed on electrode pads (not shown) on the back surface side of the chip mounting substrate 24. The electrode pad on the back surface side is connected to the electrode pad on the front surface side of the chip mounting substrate 24 by a via. Thus, the semiconductor device 37 in which the thinned chip 8 is stored without warping is formed.

(7)側面接着部材を用いない半導体装置の製造方法
図8及び9は、側面接着部材18を用いない半導体装置の製造方法を説明する工程断面図である。
(7) Manufacturing Method of Semiconductor Device Without Using Side Adhesive Member FIGS. 8 and 9 are process cross-sectional views illustrating a manufacturing method of a semiconductor device without using the side adhesive member 18.

まず、図8(a)に示すように、ペースト状の裏面接着部材26をチップ搭載基板24に塗布する。その後、コレット28aにチップ8を吸着し、裏面接着部材26の上方に配置する。ここでは、突起部32を有さないコレット28aを用いる。   First, as shown in FIG. 8A, a paste-like back surface adhesive member 26 is applied to the chip mounting substrate 24. Thereafter, the chip 8 is adsorbed to the collet 28 a and disposed above the back surface adhesive member 26. Here, a collet 28a having no protrusion 32 is used.

次に、図8(b)に示すように、裏面接着部材26を介して、チップ8をチップ搭載基板24に押圧する。すると、反っていたチップ8が略平坦になり、チップ8とチップ搭載基板24の間が裏面接着部材26で満たされる。   Next, as shown in FIG. 8B, the chip 8 is pressed against the chip mounting substrate 24 through the back surface adhesive member 26. Then, the warped chip 8 becomes substantially flat, and the space between the chip 8 and the chip mounting substrate 24 is filled with the back surface adhesive member 26.

しかし、チップ8をコレット28aから分離すると、図8(c)に示すようにチップ8は再び反り返る。この時、裏面接着部材26に、ひけ48(空間)が発生する。   However, when the chip 8 is separated from the collet 28a, the chip 8 warps again as shown in FIG. At this time, sink marks 48 (spaces) are generated in the back surface adhesive member 26.

このため次の接着工程(裏面接着部材の加熱工程)では、裏面接着部材26は、図8(d)に示すように、反り返ったまま恒温槽40で加熱され硬化する。その結果、チップ8は、反ったままチップ搭載基板24に接着される。   For this reason, in the next bonding step (heating step of the back surface adhesive member), the back surface adhesive member 26 is heated and cured in the constant temperature bath 40 while being warped, as shown in FIG. As a result, the chip 8 is bonded to the chip mounting substrate 24 while being warped.

この反り返ったチップ8に対して、図9(a)に示すように、チップ8の電極パッド22とチップ搭載基板24の電極パッドがボンディングワイヤ42で接続される。すると、領域Aに示すように、反り返ったチップ8の端とボンディングワイヤ42が接触または接近する。その結果、ボンディングワイヤ42と集積回路がショートしやすくなる。或いは、領域Bに示すように、ボンディングワイヤ42が電極パッド22から剥れ易くなる。   As shown in FIG. 9A, the electrode pad 22 of the chip 8 and the electrode pad of the chip mounting substrate 24 are connected to the warped chip 8 by bonding wires 42 as shown in FIG. Then, as shown in the region A, the end of the warped chip 8 and the bonding wire 42 contact or approach each other. As a result, the bonding wire 42 and the integrated circuit are easily short-circuited. Alternatively, as shown in the region B, the bonding wire 42 is easily peeled off from the electrode pad 22.

次に、図9(b)に示すように、チップ8およびボンディングワイヤ42をモールド樹脂44で封止する。この際、まずチップ8が搭載されたチップ搭載基板24が金型(図示せず)内に装着され、この金型にモールド樹脂44が充填される。その後、モールド樹脂44は加熱され、硬化させる。   Next, as shown in FIG. 9B, the chip 8 and the bonding wire 42 are sealed with a mold resin 44. At this time, the chip mounting substrate 24 on which the chip 8 is mounted is first mounted in a mold (not shown), and the mold resin 44 is filled in the mold. Thereafter, the mold resin 44 is heated and cured.

金型にモールド樹脂44が充填されると、ひけ48の上側でチップ8が破壊され易くなる。例えば、ひけ48が裏面接着部材26の内部に閉じ込められると、ボイド52になる。このボイド52の上側では、チップ8がモールド樹脂44から受ける圧力に対抗する力が働かない。このためチップ8が破壊され、チップクラック50が発生する。   When the mold is filled with the mold resin 44, the chip 8 is easily broken above the sink marks 48. For example, when sink mark 48 is confined inside back adhesive member 26, void 52 is formed. On the upper side of the void 52, a force that opposes the pressure that the chip 8 receives from the mold resin 44 does not work. For this reason, the chip 8 is destroyed and a chip crack 50 is generated.

最後に、図9(c)に示すように、チップ搭載基板24の裏面側の電極パッドに半田ボール46を形成して、半導体装置37aが完成する。   Finally, as shown in FIG. 9C, solder balls 46 are formed on the electrode pads on the back surface side of the chip mounting substrate 24 to complete the semiconductor device 37a.

このように、側面接着部材18を用いないで半導体装置37aを製造すると、ボンディングワイヤ42のショート、ボンディングワイヤ42の電極パッドからの剥れ、およびチップクラック50の発生等の問題が生じ易くなる。   Thus, when the semiconductor device 37a is manufactured without using the side surface adhesive member 18, problems such as shorting of the bonding wire 42, peeling of the bonding wire 42 from the electrode pad, and generation of the chip crack 50 are likely to occur.

更に、半導体装置37aをプリント基板等に半田付けすると、ボイド52内の水分が高温に曝されて膨張し、半導体装置37aを破壊する(所謂、ポップコーン現象)。   Further, when the semiconductor device 37a is soldered to a printed circuit board or the like, the moisture in the void 52 is exposed to a high temperature and expands to destroy the semiconductor device 37a (so-called popcorn phenomenon).

これらの問題は、すべてチップ8の反りに起因している。本実施の形態によれば、図2を参照して説明したようにチップ8の反りが抑制されるので、これらの問題の一部または全部が解決される。   These problems are all caused by the warp of the chip 8. According to the present embodiment, as described with reference to FIG. 2, the warpage of the chip 8 is suppressed, so that some or all of these problems are solved.

(8)変形例
図10及び11は、側面接着部材の変形例18aを説明する図である。
(8) Modification FIGS. 10 and 11 are diagrams illustrating a modification 18a of the side surface adhesive member.

図1を参照して説明したように、図5に示す側面接着部材18は、チップ8の側面に接する樹脂配置領域(溝10)に熱硬化性樹脂12を配置し、この熱硬化性樹脂12を半硬化させて形成する。   As described with reference to FIG. 1, the side adhesive member 18 shown in FIG. 5 arranges the thermosetting resin 12 in the resin arrangement region (groove 10) in contact with the side surface of the chip 8, and this thermosetting resin 12. Is semi-cured to form.

図12は、図1を参照して説明した側面接着部材18の製造方法を説明する平面図である。図12に示す例では、チップ8を囲う領域(樹脂配置領域)に、熱硬化性樹脂12が配置される。一方、変形例18aの製造方法では、図10に示すように、チップ8の四隅をそれぞれ囲う複数の孤立領域(樹脂配置領域)に、熱硬化性樹脂12が配置される。したがって、図11に示すように、チップ8の四隅に側面接着部材(変形例18a)が形成される。   FIG. 12 is a plan view illustrating a method for manufacturing the side surface adhesive member 18 described with reference to FIG. In the example shown in FIG. 12, the thermosetting resin 12 is arranged in an area (resin arrangement area) surrounding the chip 8. On the other hand, in the manufacturing method of the modified example 18a, as shown in FIG. 10, the thermosetting resin 12 is arranged in a plurality of isolated regions (resin arrangement regions) that respectively surround the four corners of the chip 8. Therefore, as shown in FIG. 11, side surface adhesive members (modified example 18a) are formed at the four corners of the chip 8.

図13は、コレットの変形例28aの下面図である。図6を参照して説明したコレット28は、図6(a)に示すように、枠状突出部30の四隅にそれぞれ2つの突起部32を有している。一方、変形例28aは、図13に示すように、枠状突出部30の四隅に突起部32を一つずつ有している。   FIG. 13 is a bottom view of a modified collet 28a. The collet 28 described with reference to FIG. 6 has two protrusions 32 at the four corners of the frame-shaped protrusion 30 as shown in FIG. On the other hand, as shown in FIG. 13, the modified example 28 a has one protrusion 32 at each of the four corners of the frame-shaped protrusion 30.

いずれのコレットでも、突起部32は側面接着部材18の一部を押圧するだけなので、過剰な裏面接着部材26や空気の排出経路が確保される。また、チップ8の対角線に沿って側面接着部材18が押圧されるので、チップ8の反りが効率良くに抑制される。   In any collet, since the protrusion 32 only presses a part of the side surface adhesive member 18, an excessive back surface adhesive member 26 and an air discharge path are secured. Moreover, since the side surface adhesive member 18 is pressed along the diagonal line of the chip 8, warping of the chip 8 is efficiently suppressed.

(実施の形態2)
図14及び15は、本実施の形態の半導体装置の製造方法を説明する工程断面図である。実施の形態1と共通する部分については、説明を省略する。
(Embodiment 2)
14 and 15 are process cross-sectional views illustrating the method for manufacturing the semiconductor device of the present embodiment. Description of portions common to the first embodiment is omitted.

(1)側面接着部材および裏面接着部材の形成工程
まず、図1と略同じ工程により、チップ8の側面に側面接着部材18を形成する。その後、裏面接着部材26bとして、チップ8の裏面にフィルム状の接着部材54(例えば、Die Attach Film)を接着する。
(1) Forming Step of Side Adhesive Member and Back Adhesive Member First, the side adhesive member 18 is formed on the side surface of the chip 8 by substantially the same process as FIG. Thereafter, a film-like adhesive member 54 (for example, Die Attach Film) is adhered to the back surface of the chip 8 as the back surface adhesive member 26b.

(2)第1の接着工程(図14(a)〜(c))
まず、ダイボンダーに、チップ搭載基板24を装着する。その後、図14(a)に示すように、チップ8をコレット28で吸着し、チップ搭載基板24の上方に配置する。
(2) First bonding step (FIGS. 14A to 14C)
First, the chip mounting substrate 24 is mounted on the die bonder. After that, as shown in FIG. 14A, the chip 8 is adsorbed by the collet 28 and disposed above the chip mounting substrate 24.

次に、図14(b)に示すように、ダイボンダーに内蔵されたヒータ36でチップ搭載基板24を加熱しながら、フィルム状の接着部材(以下、接着フィルムと呼ぶ)54を介してチップ8をチップ搭載基板24に押圧する。押圧時間は、0.5〜1.0秒程度である。この時、側面接着部材18も突起部32によりチップ搭載基板24に押圧され、側面接着部材18がチップ搭載基板24に接着される。この側面接着部材18によって、チップ8はチップ搭載基板24に仮接着される。   Next, as shown in FIG. 14B, the chip 8 is attached via a film-like adhesive member (hereinafter referred to as an adhesive film) 54 while heating the chip mounting substrate 24 with the heater 36 incorporated in the die bonder. The chip mounting substrate 24 is pressed. The pressing time is about 0.5 to 1.0 seconds. At this time, the side surface adhesive member 18 is also pressed against the chip mounting substrate 24 by the protrusion 32, and the side surface adhesive member 18 is bonded to the chip mounting substrate 24. The chip 8 is temporarily bonded to the chip mounting substrate 24 by the side surface adhesive member 18.

ところで、側面接着部材18だけでなく接着フィルム(裏面接着部材)54も、チップ搭載基板24を介して加熱される。接着フィルム(裏面接着部材)54が加熱されると、そのタック性が高くなる。このためチップ8は、側面接着部材18だけでなく接着フィルム54によっても、チップ搭載基板24に接着される。しかし、加熱時間が短いので、接着フィルム54だけで、チップ8の反りを防ぐことは困難である。このため、側面接着部材18が用いられる。   By the way, not only the side surface adhesive member 18 but also the adhesive film (back surface adhesive member) 54 is heated via the chip mounting substrate 24. When the adhesive film (back surface adhesive member) 54 is heated, its tackiness is enhanced. Therefore, the chip 8 is bonded to the chip mounting substrate 24 not only by the side surface adhesive member 18 but also by the adhesive film 54. However, since the heating time is short, it is difficult to prevent the chip 8 from warping only with the adhesive film 54. For this reason, the side surface adhesive member 18 is used.

尚、本実施の形態では、コレット28は加熱されない。これは、チップ8の吸着時に接着フィルム54は加熱されて、チップ8のピックアップが困難になることを回避するためである。   In the present embodiment, the collet 28 is not heated. This is to prevent the adhesive film 54 from being heated when the chip 8 is adsorbed to make it difficult to pick up the chip 8.

チップ8の搭載が終了すると、チップ搭載基板24は、ダイボンダーから取り外される。これにより、チップ8に対するコレット28の押さえが無くなる。しかし、チップ8は、側面接着部材18によりチップ搭載基板24に仮接着されているので、平坦な形状を保ち続ける(図14(c)参照)。   When the mounting of the chip 8 is completed, the chip mounting substrate 24 is removed from the die bonder. As a result, the collet 28 is not pressed against the chip 8. However, since the chip 8 is temporarily bonded to the chip mounting substrate 24 by the side surface adhesive member 18, it keeps a flat shape (see FIG. 14C).

(3)ボンディング工程(図15(a))
次に、図15(a)に示すように、側面接着部材18を残したまま、チップ8の電極パッド22とチップ搭載基板の電極パッドをボンディングワイヤ42で接続する(図15(a)参照)。
(3) Bonding process (FIG. 15A)
Next, as shown in FIG. 15A, the electrode pad 22 of the chip 8 and the electrode pad of the chip mounting substrate are connected by the bonding wire 42 while leaving the side surface adhesive member 18 (see FIG. 15A). .

(4)封止工程および第2の接着工程(図15(b))
次に、チップ8およびボンディングワイヤ42をモールド樹脂44で封止する(封止工程)。この際、恒温槽40を用いてモールド樹脂44を加熱し硬化させる。
(4) Sealing step and second bonding step (FIG. 15B)
Next, the chip 8 and the bonding wire 42 are sealed with a mold resin 44 (sealing process). At this time, the mold resin 44 is heated and cured using the thermostat 40.

この時、接着フィルム54も加熱され、チップ8がチップ搭載基板24に強く接着される(第2の接着工程)。   At this time, the adhesive film 54 is also heated, and the chip 8 is strongly bonded to the chip mounting substrate 24 (second bonding step).

接着フィルム54によるチップ8の接着は、接着フィルム54の押圧(図14(b))により、第1の接着工程(図14(a)〜(c))で始まる。その後、接着フィルム54によるチップ8の接着は、チップ搭載基板24のダイボンダーからの取り出しにより一旦停止するが、モールド樹脂の封止工程で再開し完了する。   The adhesion of the chip 8 by the adhesive film 54 starts with the first adhesion process (FIGS. 14A to 14C) by pressing the adhesive film 54 (FIG. 14B). Thereafter, the bonding of the chip 8 by the adhesive film 54 is temporarily stopped by taking out the chip mounting substrate 24 from the die bonder, but is restarted and completed in the molding resin sealing process.

(5)半田ボール形成工程(図15(c))
最後に、図15(c)に示すように、チップ搭載基板24の裏面側に半田ボール46を形成する。
(5) Solder ball forming step (FIG. 15C)
Finally, as shown in FIG. 15C, solder balls 46 are formed on the back surface side of the chip mounting substrate 24.

以上の工程により、集積回路が表面に設けられたチップ8、チップ8が搭載されたチップ搭載基板24、裏面接着部材26b、および側面接着部材18を有する半導体装置37cが形成される。   Through the above steps, the semiconductor device 37c including the chip 8 with the integrated circuit provided on the surface, the chip mounting substrate 24 on which the chip 8 is mounted, the back surface adhesive member 26b, and the side surface adhesive member 18 is formed.

ここで、裏面接着部材26は、チップ8の裏面に設けられ、チップ8をチップ搭載基板24に接着する接着部材である。側面接着部材18は、半導体チップ8の側面に設けられ、チップ8をチップ搭載基板24に接着する接着部材である。   Here, the back surface adhesive member 26 is an adhesive member that is provided on the back surface of the chip 8 and adheres the chip 8 to the chip mounting substrate 24. The side adhesive member 18 is an adhesive member that is provided on the side surface of the semiconductor chip 8 and adheres the chip 8 to the chip mounting substrate 24.

上述したように、封止工程までは接着フィルム54の接着力は、チップ8の反りを防ぐには不十分である。このため側面接着部材18を用いないと、チップ8のコレット28からの取り外す時に、チップ搭載基板24から接着フィルム54の一部が剥離して、チップ8が反り返る。このため実施の形態1と同様、ボンディングワイヤのショートなど種々の問題が発生する。   As described above, the adhesive force of the adhesive film 54 is insufficient to prevent the chip 8 from warping until the sealing step. Therefore, if the side surface adhesive member 18 is not used, when the chip 8 is removed from the collet 28, a part of the adhesive film 54 is peeled off from the chip mounting substrate 24, and the chip 8 is warped. For this reason, as in the first embodiment, various problems such as a short of a bonding wire occur.

しかし、本実施の形態によれば、側面接着部材18によりチップ8の反りが抑制されるので、これらの問題の全部または一部が解決される。   However, according to the present embodiment, since the warpage of the chip 8 is suppressed by the side surface adhesive member 18, all or part of these problems are solved.

本実施の形態では、側面接着部材18は除去されないが、実施の形態1と同様に、側面接着部材18は除去されてもよい。   In the present embodiment, the side adhesive member 18 is not removed, but the side adhesive member 18 may be removed as in the first embodiment.

また、本実施の形態では、裏面接着部材26bの加熱処理は、モールド樹脂の加熱処理と同時に行われる。しかし、実施の形態1と同様に、モールド樹脂を加熱する前に裏面接着部材26bを加熱してもよい。   Moreover, in this Embodiment, the heat processing of the back surface adhesive member 26b is performed simultaneously with the heat processing of mold resin. However, as in the first embodiment, the back surface adhesive member 26b may be heated before the mold resin is heated.

以上の例では、側面接着部材18は、エポキシ樹脂を半硬化させて形成される。しかし、側面接着部材18の原料は、エポキシ樹脂には限られない。例えば、エポキシ樹脂以外の熱硬化性樹脂から、側面接着部材18を形成してもよい。また、熱可塑性樹脂(例えば、アクリル樹脂やABS(Acrylonitrile Butadiene Styrene)樹脂)から、側面接着部材18を形成してもよい。更に、室温でタック性を有するように調合されたエポキシ樹脂から、側面接着部材18を形成してもよい。この場合、コレット28やチップ搭載基板24の加熱は不要である。   In the above example, the side surface adhesive member 18 is formed by semi-curing an epoxy resin. However, the raw material of the side surface adhesive member 18 is not limited to an epoxy resin. For example, the side surface adhesive member 18 may be formed from a thermosetting resin other than an epoxy resin. Further, the side surface adhesive member 18 may be formed from a thermoplastic resin (for example, an acrylic resin or ABS (Acrylonitrile Butadiene Styrene) resin). Furthermore, you may form the side surface adhesion member 18 from the epoxy resin prepared so that it may have tackiness at room temperature. In this case, heating of the collet 28 and the chip mounting substrate 24 is not necessary.

上の例では、裏面接着部材は、ペースト状のエポキシ樹脂または接着フィルムである。しかし、裏面接着部材は、これらの接着部材に限られない。例えば、裏面接着部材は、銀ペース等の導電性接着部材やエポキシ樹脂以外の熱硬化性樹脂であってもよい。   In the above example, the back surface adhesive member is a paste-like epoxy resin or an adhesive film. However, the back surface adhesive member is not limited to these adhesive members. For example, the back surface adhesive member may be a conductive adhesive member such as a silver paste or a thermosetting resin other than an epoxy resin.

以上の例では、チップ8が有する基板2は、シリコン基板である。しかし、基板2は、シリコン基板以外の基板であってもよい。例えば、基板2は、SOI(Silicon on Insulator)基板やGaAs基板等の化合物半導体基板であってもよい。   In the above example, the substrate 2 included in the chip 8 is a silicon substrate. However, the substrate 2 may be a substrate other than a silicon substrate. For example, the substrate 2 may be a compound semiconductor substrate such as an SOI (Silicon on Insulator) substrate or a GaAs substrate.

以上の実施の形態1及び2に関し、更に以下の付記を開示する。   Regarding the above first and second embodiments, the following additional notes are disclosed.

(付記1)
集積回路が表面に設けられたチップの側面に、側面接着部材を形成する側面接着部材の形成工程と、
前記チップの裏面に配置された裏面接着部材を介して前記チップをチップ搭載基板に押圧しながら、前記側面接着部材を前記チップ搭載基板に押圧して前記側面接着部材を前記チップ搭載基板に接着する第1の接着工程と、
前記第1の接着工程の後に、前記裏面接着部材を加熱して、前記チップ搭載基板に前記チップを接着する第2の接着工程とを
有する半導体装置の製造方法。
(Appendix 1)
A step of forming a side surface adhesive member on the side surface of the chip provided with the integrated circuit on the surface;
While pressing the chip against the chip mounting substrate via a back surface bonding member disposed on the back surface of the chip, the side surface bonding member is pressed against the chip mounting substrate to bond the side surface bonding member to the chip mounting substrate. A first bonding step;
A method for manufacturing a semiconductor device, comprising: a second bonding step of heating the back surface bonding member and bonding the chip to the chip mounting substrate after the first bonding step.

(付記2)
付記1に記載の半導体装置の製造方法において、
前記第2の接着工程の後に、前記側面接着部材を取り除くことを
特徴とする半導体装置の製造方法。
(Appendix 2)
In the method for manufacturing a semiconductor device according to attachment 1,
The method for manufacturing a semiconductor device, wherein the side surface adhesive member is removed after the second bonding step.

(付記3)
付記1または2に記載の半導体装置の製造方法において、
前記側面接着部材の形成工程は、前記チップの側面に接する樹脂配置領域に熱硬化性樹脂を配置した後、前記熱硬化性樹脂を半硬化させて前記チップの側面に前記側面接着部材を形成することを
特徴とする半導体装置の製造方法。
(Appendix 3)
In the method for manufacturing a semiconductor device according to appendix 1 or 2,
In the step of forming the side surface adhesive member, a thermosetting resin is arranged in a resin arrangement region in contact with the side surface of the chip, and then the thermosetting resin is semi-cured to form the side surface adhesive member on the side surface of the chip. A method for manufacturing a semiconductor device.

(付記4)
付記3に記載の半導体装置の製造方法において、
前記樹脂配置領域は、前記チップの四隅の孤立領域または前記チップを囲う領域であることを
特徴とする半導体装置の形成方法。
(Appendix 4)
In the method for manufacturing a semiconductor device according to attachment 3,
The method for forming a semiconductor device, wherein the resin arrangement region is an isolated region at four corners of the chip or a region surrounding the chip.

(付記5)
付記1乃至4のいずれか1項に記載の半導体装置の製造方法において、
前記裏面接着部材は、前記チップ搭載基板に塗布された接着部材であることを
特徴とする半導体装置の製造方法。
(Appendix 5)
In the method for manufacturing a semiconductor device according to any one of appendices 1 to 4,
The method of manufacturing a semiconductor device, wherein the back surface adhesive member is an adhesive member applied to the chip mounting substrate.

(付記6)
付記1乃至4のいずれか1項に記載の半導体装置の製造方法において、
前記裏面接着部材は、前記チップの裏面に接着されたフィルム状の接着部材であり、
前第1の接着工程は、前記フィルム状の接着部材を加熱しながら前記チップを前記チップ搭載基板に押圧し、
前記フィルム状の接着部材による前記チップの接着は、前記第1の工程で始まることを
特徴とする半導体装置の製造方法。
(Appendix 6)
In the method for manufacturing a semiconductor device according to any one of appendices 1 to 4,
The back surface adhesive member is a film-like adhesive member adhered to the back surface of the chip,
In the first bonding step, the chip is pressed against the chip mounting substrate while heating the film-like bonding member,
The method for manufacturing a semiconductor device, wherein the bonding of the chip by the film-like adhesive member starts in the first step.

(付記7)
付記1乃至6のいずれか1項に記載の半導体装置の製造方法において、
前記チップは、10μm以上100μm以下の厚さを有することを
特徴とする半導体装置の製造方法。
(Appendix 7)
In the method for manufacturing a semiconductor device according to any one of appendices 1 to 6,
The method of manufacturing a semiconductor device, wherein the chip has a thickness of 10 μm to 100 μm.

(付記8)
集積回路が表面に設けられたチップと、
前記チップが搭載されたチップ搭載基板と、
前記チップの裏面に設けられ、前記チップを前記チップ搭載基板に接着する裏面接着部材と、
前記半導体チップの側面に設けられ、前記チップを前記チップ搭載基板に接着する側面接着部材とを
有する半導体装置。
(Appendix 8)
A chip with an integrated circuit on its surface;
A chip mounting substrate on which the chip is mounted;
A back surface adhesive member that is provided on the back surface of the chip and adheres the chip to the chip mounting substrate;
A semiconductor device comprising: a side adhesive member that is provided on a side surface of the semiconductor chip and adheres the chip to the chip mounting substrate.

8・・・チップ
14・・・半硬化接着部材
18・・・側面接着部材
24・・・チップ搭載基板
26・・・裏面接着部材
28・・・コレット
37、37a・・・半導体装置
54・・・接着フィルム
8 ... Chip 14 ... Semi-cured adhesive member 18 ... Side side adhesive member 24 ... Chip mounting substrate 26 ... Back side adhesive member 28 ... Collet 37, 37a ... Semiconductor device 54 ...・ Adhesive film

Claims (5)

集積回路が表面に設けられたチップの側面に、側面接着部材を形成する側面接着部材の形成工程と、
前記チップの裏面に配置された裏面接着部材を介して前記チップをチップ搭載基板に押圧しながら、前記側面接着部材を前記チップ搭載基板に押圧して前記側面接着部材を前記チップ搭載基板に接着する第1の接着工程と、
前記第1の接着工程の後に、前記裏面接着部材を加熱して、前記チップ搭載基板に前記チップを接着する第2の接着工程とを
有する半導体装置の製造方法。
A step of forming a side surface adhesive member on the side surface of the chip provided with the integrated circuit on the surface;
While pressing the chip against the chip mounting substrate via a back surface bonding member disposed on the back surface of the chip, the side surface bonding member is pressed against the chip mounting substrate to bond the side surface bonding member to the chip mounting substrate. A first bonding step;
A method for manufacturing a semiconductor device, comprising: a second bonding step of heating the back surface bonding member and bonding the chip to the chip mounting substrate after the first bonding step.
請求項1に記載の半導体装置の製造方法において、
前記第2の接着工程の後に、前記側面接着部材を取り除くことを
特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the side surface adhesive member is removed after the second bonding step.
請求項1または2に記載の半導体装置の製造方法において、
前記側面接着部材の形成工程は、前記チップの側面に接する樹脂配置領域に熱硬化性樹脂を配置した後、前記熱硬化性樹脂を半硬化させて前記チップの側面に前記側面接着部材を形成することを
特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 1 or 2,
In the step of forming the side surface adhesive member, a thermosetting resin is arranged in a resin arrangement region in contact with the side surface of the chip, and then the thermosetting resin is semi-cured to form the side surface adhesive member on the side surface of the chip. A method for manufacturing a semiconductor device.
請求項1乃至3のいずれか1項に記載の半導体装置の製造方法において、
前記チップは、10μm以上100μm以下の厚さを有することを
特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to any one of claims 1 to 3,
The method of manufacturing a semiconductor device, wherein the chip has a thickness of 10 μm to 100 μm.
集積回路が表面に設けられたチップと、
前記チップが搭載されたチップ搭載基板と、
前記チップの裏面に設けられ、前記チップを前記チップ搭載基板に接着する裏面接着部材と、
前記半導体チップの側面に設けられ、前記チップを前記チップ搭載基板に接着する側面接着部材とを
有する半導体装置。
A chip with an integrated circuit on its surface;
A chip mounting substrate on which the chip is mounted;
A back surface adhesive member that is provided on the back surface of the chip and adheres the chip to the chip mounting substrate;
A semiconductor device comprising: a side adhesive member that is provided on a side surface of the semiconductor chip and adheres the chip to the chip mounting substrate.
JP2011186160A 2011-08-29 2011-08-29 Semiconductor device manufacturing method and semiconductor device Pending JP2013048171A (en)

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JPH1058873A (en) * 1996-08-26 1998-03-03 Hitachi Maxell Ltd Ic module
JP2001053033A (en) * 1999-08-12 2001-02-23 Texas Instr Japan Ltd Dicing method of semiconductor device
JP2002198384A (en) * 2000-12-27 2002-07-12 Matsushita Electric Ind Co Ltd Semiconductor device and its fabrication method
JP2005197621A (en) * 2004-01-09 2005-07-21 Nec Saitama Ltd Csp removal device and method therefor
JP2006032625A (en) * 2004-07-15 2006-02-02 Fujitsu Ltd Semiconductor device and method for manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1058873A (en) * 1996-08-26 1998-03-03 Hitachi Maxell Ltd Ic module
JP2001053033A (en) * 1999-08-12 2001-02-23 Texas Instr Japan Ltd Dicing method of semiconductor device
JP2002198384A (en) * 2000-12-27 2002-07-12 Matsushita Electric Ind Co Ltd Semiconductor device and its fabrication method
JP2005197621A (en) * 2004-01-09 2005-07-21 Nec Saitama Ltd Csp removal device and method therefor
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