CN109003907A - packaging method - Google Patents
packaging method Download PDFInfo
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- CN109003907A CN109003907A CN201810883152.9A CN201810883152A CN109003907A CN 109003907 A CN109003907 A CN 109003907A CN 201810883152 A CN201810883152 A CN 201810883152A CN 109003907 A CN109003907 A CN 109003907A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 52
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- 238000007731 hot pressing Methods 0.000 claims abstract description 81
- 230000008569 process Effects 0.000 claims description 73
- 238000012545 processing Methods 0.000 claims description 66
- 238000010438 heat treatment Methods 0.000 claims description 53
- 238000011282 treatment Methods 0.000 claims description 46
- 235000012431 wafers Nutrition 0.000 claims description 39
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- 238000013007 heat curing Methods 0.000 claims description 16
- 230000009467 reduction Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 124
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
A kind of packaging method, comprising: provide substrate, the face to be bonded of substrate is the first face to be bonded;Several chips are provided, the face to be bonded of chip is the second face to be bonded;Film-type encapsulating material is provided;Bonded layer is formed at least one face in the first face to be bonded and the second face to be bonded;After forming bonded layer at least one face in the first face to be bonded and the second face to be bonded, the first face to be bonded and the second face to be bonded is made to be oppositely arranged and chip is placed on substrate;After chip is placed on substrate, using hot pressing technique, substrate and several chips is made to realize bonding by the bonded layer, and be filled in encapsulating material between chip and substrate and cover chip, the encapsulating material after hot pressing technique is as encapsulated layer.By film-type encapsulating material, the probability that chip drifts about during reduction hot pressing technique improves the yield and reliability of encapsulating structure;And hot pressing technique synchronizes the bonding for realizing substrate and chip, improves packaging efficiency.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of packaging methods.
Background technique
With the development trend of super large-scale integration, integrated circuit feature size persistently reduces, and people are to integrated electricity
The requirement of the encapsulation technology on road is accordingly also continuously improved.Wherein, system in package (System in Package, SIP) be will be more
The other elements such as a active component with different function, passive element, MEMS (MEMS), optical element, are combined to
In one unit, the system or subsystem that can provide multiple functions is formed, allows heterogeneous IC integrated.Compared to system-level core
Piece (System on Chip, SoC), integrating for system in package is relatively easy, and design cycle and period that appears on the market are shorter, cost compared with
It is low, more complicated system may be implemented, be a kind of more universal encapsulation technology.
Currently, in order to meet the more inexpensive, more reliable, faster and more highdensity target of integrated antenna package, it is advanced
Packaging method mainly use wafer scale system encapsulation (Wafer Level System in Package, WLPSiP) and panel
Grade system encapsulation (Panel Level System in Package, PLSIP), compared with traditional system in package, wafer scale
System encapsulation and the encapsulation of face board level system are to complete encapsulation procedure on wafer (Wafer) or panel, have and substantially reduce encapsulation
The area of structure reduces the advantages such as manufacturing cost, optimization electrical property, batch manufacture, can significantly reduce workload and equipment
Demand.
But the yield of the formed encapsulating structure of packaging method and reliability are still to be improved at present.
Summary of the invention
Problems solved by the invention is to provide a kind of packaging method, improves the yield and reliability of encapsulating structure.
To solve the above problems, the present invention provides a kind of packaging method, comprising: provide substrate, the substrate it is to be bonded
Face is the first face to be bonded;Several chips are provided, the face to be bonded of the chip is the second face to be bonded;Film-type envelope is provided
Package material;Bonded layer is formed at least one face in the described first face to be bonded and second face to be bonded;Described
After forming bonded layer at least one face in first face to be bonded and second face to be bonded, make the described first face to be bonded
It is oppositely arranged with the described second face to be bonded, and the chip is placed on the substrate;The chip is placed in the substrate
After upper, using hot pressing technique, the substrate and several described chips is made to realize bonding by the bonded layer, and made described
Encapsulating material is filled between several described chips and substrate and several described chips of covering, after the hot pressing technique
Encapsulating material is used to be used as encapsulated layer.
Optionally, after the chip being placed on the substrate, before the hot pressing technique, further includes: to described
Substrate and chip carry out pre- bonding processing.
Optionally, the technique of the pre- bonding processing is thermocompression bonding or pressurization bonding.
Optionally, the step of technique of the pre- bonding processing is thermocompression bonding, and the pre- bonding is handled includes: to described
At least one of chip and substrate carry out the first pressurized treatments, and while carrying out first pressurized treatments, to described
Chip and the substrate carry out the first heat treatment.
Optionally, in first pressurized treatments the step of, to the chip backwards to the table in the described second face to be bonded
Face carries out first pressurized treatments;In the step of described first heats, to the chip backwards to described second to key
The surface in conjunction face and the substrate back carry out first heat treatment.
Optionally, the step of pre- bonding is handled further include: in first pressurized treatments and the first heat treatment
Before, the first vacuumize process is carried out, the process pressure of the pre- bonding processing is made to reach default pressure.
Optionally, the step of hot pressing technique includes: that the encapsulating material is placed on several described chips;It will
After the encapsulating material is placed on several described chips, the second vacuumize process and the second heat treatment are carried out, the heat is made
The process pressure of process for pressing reaches default pressure, and the technological temperature of the hot pressing technique is made to reach preset temperature;Described
Under default pressure and preset temperature, the second pressurized treatments are carried out to preset time to the substrate and encapsulating material, make the envelope
Package material is filled between several described chips and substrate and the covering chip, and makes the substrate and several described cores
Piece realizes bonding;After carrying out second pressurized treatments under the default pressure and preset temperature, under the preset temperature,
Heat cure processing is carried out to the encapsulating material, forms the encapsulated layer.
Optionally, in the step of forming the bonded layer, the bonded layer is formed on the described first face to be bonded.
Optionally, the hot pressing technique is hot press forming technology or hot pressing attachment process.
Optionally, in the step of carrying out pre- bonding processing to the substrate and chip, when the technique of the pre- bonding processing
Between be 1 second to 30 seconds, the pressure of first pressurized treatments is 100 newton to 400 newton, the technique of first heat treatment
Temperature is 150 degrees Celsius to 250 degrees Celsius.
Optionally, in the step of carrying out pre- bonding processing to the substrate and chip, the default pressure is 5 kPas to one
A standard atmospheric pressure.
Optionally, in the hot pressing technique the step of, the default pressure is 5 kPas to 15 kPas, described default
Temperature is 120 degrees Celsius to 180 degrees Celsius, and the pressure of second pressurized treatments is 0.1 megapascal to 10 megapascal, when described default
Between be 30 seconds to 60 seconds, the process time of heat cure processing is 300 seconds to 600 seconds.
Optionally, in the step of encapsulating material of a sheet type or film-type is provided, the encapsulating material with a thickness of 40 μ
M to 200 μm.
Optionally, the substrate is device wafers, carrier wafer or panel.
Optionally, in the step of several chips are provided, it is formed with pad in the chip, exposes the chip of the pad
Surface is chip front side, and the face opposite with the chip front side is chip back;Second face to be bonded be the chip just
Face or chip back.
Compared with prior art, technical solution of the present invention has the advantage that
After chip (Chip) is placed on the substrate by the present invention, using film-type encapsulating material, and pass through hot pressing work
Skill makes the substrate and several described chips realize bonding by the bonded layer, and the encapsulating material is made to be filled in institute
Several described chips are stated between several chips and substrate and cover, the encapsulating material after the hot pressing technique is used for conduct
Encapsulated layer;Compared to the scheme for being bonded, molding (Molding) technique being used to form encapsulated layer again for first realizing chip and substrate,
Hot pressing technique is carried out by film-type encapsulating material, the lateral impact forces that the chip is subject to can be reduced, to be conducive to
The probability that the chip drifts about during hot pressing technique is reduced, the yield and reliability of encapsulating structure are improved;And
And the hot pressing technique synchronizes the bonding for realizing the substrate and chip, ensure between the substrate and chip have compared with
While high bond strength, the process-cycle of packaging technology is accordingly also shortened, to improve packaging efficiency.
In optinal plan, after the chip is placed on the substrate, before the hot pressing technique, further includes: right
The substrate and chip carry out pre- bonding processing, are handled by the pre- bonding, can before carrying out the hot pressing technique,
Make that there is certain bond strength between the substrate and chip, therefore during the hot pressing technique, is conducive into one
Bond strength of the probability, the raising substrate and chip that the step reduction chip drifts about after the hot pressing technique,
And also help the process time for reducing the hot pressing technique, thus further increase encapsulating structure yield and reliability,
Improve packaging efficiency.
Detailed description of the invention
Fig. 1 to Fig. 8 is the corresponding structural schematic diagram of each step in one embodiment of packaging method of the present invention.
Specific embodiment
It can be seen from background technology that the yield of the formed encapsulating structure of packaging method and reliability are still to be improved at present.Point
The reason that the yield and reliability of analysis encapsulating structure are to be improved is:
In current packaging technology, compared with bonding process, bonding technology has better cohesive force and chemical stabilization
Property, therefore bonding technology is increasingly becoming the main means for realizing the encapsulation of wafer scale system and the encapsulation of face board level system.
But wafer scale system encapsulation or face board level system encapsulation be one ground of chip is bonded to wafer or other
On substrate, due to the substantial amounts of chip, in order to shorten the process-cycle of packaging technology, it is desirable that bonding time is shorter, and shorter
The corresponding bond strength that can be reduced between chip and wafer or other substrates again of bonding time;Moulding technology shape is used when subsequent
When at encapsulated layer, encapsulating material can generate lateral impact forces to chip during flowing, due to chip and wafer or other
Bond strength between substrate is lower, therefore chip is easy to happen drift, i.e. chip is easy to deviate on wafer or other substrates
Predeterminated position and then lead to the yield and reliability decrease of encapsulating structure to generate adverse effect to follow-up process.
In order to solve the technical problem, the present invention provides a kind of packaging method, comprising: substrate is provided, the substrate
Face to be bonded is the first face to be bonded;Several chips are provided, the face to be bonded of the chip is the second face to be bonded;It provides thin
Membranous type encapsulating material;Bonded layer is formed at least one face in the described first face to be bonded and second face to be bonded;
On at least one face in the described first face to be bonded and second face to be bonded formed bonded layer after, make described first to
Bonding face and second face to be bonded are oppositely arranged, and the chip is placed on the substrate;The chip is placed in institute
After stating on substrate, using hot pressing technique, the substrate and several described chips is made to realize bonding by the bonded layer, and
It is filled in the encapsulating material between several described chips and substrate and covers several described chips, the hot pressing work
Encapsulating material after skill is used to be used as encapsulated layer.
After chip is placed on the substrate by the present invention, using film-type encapsulating material, and by hot pressing technique, make institute
State substrate and several described chips and bonding realized by the bonded layer, and make the encapsulating material be filled in it is described several
Between chip and substrate and several described chips are covered, the encapsulating material after the hot pressing technique is used to be used as encapsulated layer;
Compared to the scheme for being bonded, using moulding technology to form encapsulated layer again for first realizing chip and substrate, passes through film-type package material
Material carries out hot pressing technique, can reduce the lateral impact forces that the chip is subject to, to advantageously reduce the chip in heat
The probability to drift about during process for pressing, improves the yield and reliability of encapsulating structure;And the hot pressing technique
The bonding for realizing the substrate and chip is synchronized, it is same with higher bond strength between the substrate and chip ensureing
When, the process-cycle of packaging technology is accordingly also shortened, to improve packaging efficiency.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 to Fig. 8 is the corresponding structural schematic diagram of each step in one embodiment of packaging method of the present invention.
With reference to Fig. 1, substrate 100 is provided, the face to be bonded of the substrate 100 is the first face 101 to be bonded.
The packaging method encapsulates for realizing wafer scale system or the encapsulation of face board level system.
Specifically, when the packaging method is for realizing the encapsulation of wafer scale system, the substrate 100 is device wafers
(CMOS Wafer) or carrier wafer (Carrier Wafer).Wherein, the carrier wafer can for semiconductor substrate (such as
Silicon substrate), organic glass wafer, unorganic glass wafer, resin wafer, semiconductor material wafer, oxide crystal wafer, ceramics
Wafer, metal wafer, organic plastics wafer, inorganic oxide wafer or ceramic material wafer.
When the packaging method is for realizing the encapsulation of face board level system, the substrate is panel (Panel).The panel
Shape be square, rectangle or it is other it is any needed for shape, the size of the panel is usually larger, the energy on one piece of panel
It enough realizes the encapsulation of more chips, to advantageously reduce packaging cost, there is economies of scale.Specifically, the panel
Can for printed wiring board (Printed Wire Board, PWB), printed circuit board (Printed Circuit Board,
PCB), the double-deck printed board, multilayer board, flexible circuit board or other types.
In the present embodiment, the packaging method encapsulates for realizing wafer scale system, and according to actual process demand, described
Substrate 100 is carrier wafer.
Specifically, the substrate 100 is used for and chip to be packaged realizes interim bonding, and the substrate 100 is used for subsequent
In technical process, para-linkage is played a supporting role in the chip to be packaged on the substrate 100, reduce subsequent technique described in
The probability that the problems such as rupture, warpage, fracture occurs for encapsulation chip improves subsequent work to provide technique platform for subsequent technique
The operability of skill.That is, it is subsequent by after the substrate 100 and chip to be packaged realization bonding, it also needs to remove the base
Plate 100.
In other embodiments, according to actual process demand, the substrate can be also used for realizing forever with chip to be packaged
Bonding long, i.e., it is subsequent by after the substrate and chip to be packaged realization bonding, retain the substrate.
In the present embodiment, any one side of the substrate 100 is the described first face 101 to be bonded.Correspondingly, with described
The opposite face in one face 101 to be bonded is substrate back 102.
It should be noted that in other embodiments, when the substrate is device wafers, the device wafers are to complete
The wafer of element manufacturing, such as N-type metal-oxide semiconductor (MOS) (N- is formed by techniques such as deposition, etchings on substrate
Metal-Oxide-Semiconductor, NMOS) device, P type metal oxide semiconductor (P-Metal-Oxide-
Semiconductor, PMOS) devices such as device, formed on the device dielectric layer, metal interconnection structure and with the gold
Belong to the mutually structures such as pad of connection electrical connection.Correspondingly, the substrate surface for exposing the pad is the described first face to be bonded, with
The opposite face in first face to be bonded is substrate back.Wherein, the pad is lead pad (Bond Pad), the substrate
The back side refers to the substrate floor in the substrate far from the lead pad side.
With reference to Fig. 2, several chips 200 are provided, the face to be bonded of the chip 200 is the second face 201 to be bonded.
The chip 200 is used for as the chip to be packaged in packaging technology, the function type of several chips 200
It is at least a kind of.
In the present embodiment, the quantity of the chip 200 is multiple, and be packaged for will be multiple and different for the wafer scale system
The chip 200 of function is combined in an encapsulating structure, therefore the function type of the multiple chip 200 is a variety of.Specifically,
The chip 200 can be storage chip, communication chip, processing chip, flash chip or logic chip.In other embodiments
In, the chip can also be other function chip.
In other embodiments, according to actual process demand, the function type of the multiple chip can be with identical.
The chip 200 uses made by production of integrated circuits technology, therefore the chip 200 generally also includes being formed in
The devices such as NMOS device, PMOS device on substrate further include the structures such as dielectric layer, metal interconnection structure and pad.Specifically,
The pad is lead pad.
In the present embodiment, 200 surface of chip for exposing the lead pad is chip front side (not indicating), with the chip
The opposite face in front is chip back (not indicating).Wherein, the chip back refers to drawing in the chip 200 far from described
The substrate floor of wire bonding disk side.
In the present embodiment, according to actual process demand, the subsequent chip 200 is with the side of chip front side (faceup) upward
Formula is bonded to the substrate 100 (as shown in Figure 1), therefore second face 201 to be bonded is the chip back.In other realities
It applies in example, when the chip is bonded to the substrate in a manner of chip front side downward (face down), described second to key
Conjunction face mutually should be the chip front side.
It should be noted that only illustrating a chip 200 for the ease of illustration, in Fig. 2.
In the present embodiment, in order to realize the bonding of the substrate 100 and chip 200, the packaging method further include: in institute
It states at least one face in the first face 101 (as shown in Figure 1) to be bonded and second face 201 (as shown in Figure 2) to be bonded
It is formed bonded layer (bonding film) 120 (as shown in Figure 3).
After subsequent bonding technology, the substrate 100 and several described chips 200 pass through the bonded layer 120
Realize physical connection.
Compared with adhesive layer, the bonded layer 120 has more high bond strength, has good chemical resistance, acid and alkali-resistance
Property and the characteristics such as heat-resisting quantity, and using after the bonded layer 120, requirement of the bonding technology to shearing force is reduced, shorter
Process time in, the complete bonding of the substrate 100 and the chip 200 can be realized, the chip 200 is in the substrate
The probability to drift about on 100 is relatively low.
In the present embodiment, the base materials of the bonded layer 120 are epoxy resin, the mass percentage content of epoxy resin
It is 80% to 95%.Wherein, base materials refer to the base-material of the bonded layer 120, are main groups of the bonded layer 120
Point, for determining the basic performance of the bonded layer 120.
In other embodiments, the base materials of the bonded layer can also be novolac epoxy resin.
It should be noted that emulsion can be added in the promoter material of the bonded layer 120, to make the bonded layer
120 have can photoetching characteristic.Wherein, promoter material refers to: the material in addition to the base materials is to assign
State auxiliary material added by certain characteristic of bonded layer 120.
Electric connection is another important process of packaging technology, in order to realize the electric connection of encapsulating structure, subsequent
Bonding technology after, also typically include the processing procedure of the graphical bonded layer 120, can by having the bonded layer 120
The characteristic of photoetching, it is subsequent the bonded layer 120 to be patterned by way of exposure development, it avoids using additionally
Etching technics, this not only contributes to simplify the processing step of the graphical bonded layer 120, improves packaging efficiency, and passes through
The mode of exposure development, additionally it is possible to reduce the influence to bond strength between the bonded layer 120 and chip 200, it is corresponding to reduce
The probability that the bonded layer 120 is fallen off.
In other embodiments, according to actual process demand, emulsion can not also be added in the material of the bonded layer.
The thickness T1 (as shown in Figure 3) of the bonded layer 120 is unsuitable too small, also should not be too large.If the bonded layer 120
Thickness T1 it is too small, then be easy to cause the bonded layer 120 to be not enough to realize the substrate 100 and several described chips 200
Between bonding, that is, the bond strength being easily reduced between the substrate 100 and several described chips 200;If the key
The thickness T1 for closing layer 120 is excessive, then is easy to cause the volume of formed encapsulating structure excessive, and also will cause the waste of material.
For this purpose, after forming the bonded layer 120, the thickness T1 of the bonded layer 120 is 20 μm to 100 μm in the present embodiment.
In the present embodiment, using attachment process (i.e. lamination technique), in the described first face 101 to be bonded and described
The bonded layer 120 is formed at least one face in second face 201 to be bonded.
With reference to Fig. 3, in the present embodiment, in order to reduce the technology difficulty to form the bonded layer 120, simplification forms the key
It closes the processing step of layer 120, improve packaging efficiency, form the bonded layer on the first face 101 to be bonded of the substrate 100
120。
Moreover, being also convenient for subsequent by forming the bonded layer 120 on the first face 101 to be bonded of the substrate 100
Several described chips 200 are placed on the substrate 100, are conducive to improve process operability.
In other embodiments, the bonded layer can also be formed on the second face to be bonded of several chips.
Wherein, it is obtained since several described chips are cut by multiple wafers to different function, for the ease of institute
The formation for stating bonded layer, the step on the second face to be bonded of several chips include: to be integrated with the chip
The bonded layer is formed on multiple wafers;After forming the bonded layer, the multiple wafer is cut, to be formed
There are several chips of the bonded layer.
With continued reference to Fig. 3, in the present embodiment, according to actual process demand, the bonded layer 120 and the substrate 100 are logical
It crosses adhesive layer 110 and realizes bonding.
The adhesive layer 110 is used as peeling layer, for realizing the interim bonding of the substrate 100 and bonded layer 120
(temporary bonding)。
It is subsequent after formation encapsulated layer, also to need to remove the substrate 100, by making the bonded layer on the substrate 100
120 and the substrate 100 by the adhesive layer 110 realize bonding, can be convenient for subsequent by the substrate 100 and the bonding
Layer 120 is separated.
Therefore, the adhesive layer 110 has smooth finish surface, and the adhesive layer 110 and the substrate 100 and the key
Close layer 120 have certain binding force, thus reduce the substrate 100 and bonded layer 120 occurs in the subsequent process move or
Isolated probability.
In the present embodiment, the adhesive layer 110 is chip bonding glue film (Die Attach Film, DAF).In other realities
It applies in example, the adhesive layer can also be dry film (Dry Film), UV glue or hot-setting adhesive.
For this purpose, in the present embodiment, in order to improve process operability, on the described first face 101 to be bonded described in formation
110 layers of adhesive layer;After forming 110 layers of the adhesive layer on the described first face 101 to be bonded, the shape on the adhesive layer 110
At the bonded layer 120.
In other embodiments, when the substrate is used for and several described chips realize permanent bonding, then accordingly may be used
Not use the adhesive layer, i.e., described first face to be bonded is in contact with the bonded layer.
With reference to Fig. 4, after forming the bonded layer 120, make the described first face 101 to be bonded and second face to be bonded
201 are oppositely arranged, and several described chips 200 are placed on the substrate 100.
By being oppositely arranged the described first face 101 to be bonded and second face 201 to be bonded, and will it is described several
Chip 200 is placed on the substrate 100, to mention for the subsequent bonding for realizing the substrate 100 and several chips 200
For Process ba- sis.
In the present embodiment, several described chips 200 are placed on the substrate 100 by the way of absorption.
Specifically, it is oppositely arranged the described first face 101 to be bonded and second face 201 to be bonded, and if will be described
The step that dry chip 200 is placed on the substrate 100 includes: to provide bonding apparatus (not shown), and the bonding apparatus includes
First heating plate 310 and thermal head 320, first heating plate 310 and thermal head 320 are set to the chamber of the bonding apparatus
In;The substrate 100 is placed in first heating plate 310;The substrate 100 is placed in first heating plate 310
Afterwards, the chip 200 is adsorbed backwards to the surface in the described second face 201 to be bonded using the thermal head 320;Using the hot pressing
The first 320 absorption chip 200 is behind the surface in the described second face 201 to be bonded, using the thermal head 320 by the core
Piece 200 is placed in the predetermined position on the substrate 100.
It should be noted that the quantity of the thermal head 320 of the bonding apparatus is one, therefore the thermal head 320 will
Several described chips 200 are placed in one by one on the substrate 100.
With continued reference to Fig. 4, in the present embodiment, after the chip 200 is placed on the substrate 100, further includes: to described
Substrate 100 and chip 200 are bonded (pre-bonding) processing in advance.
By carrying out pre- bonding processing to the substrate 100 and chip 200, make between the substrate 100 and bonded layer 120
With certain bond strength, in the subsequent process, the probability that the chip 200 drifts about accordingly is reduced, and also helps
The process time for reducing subsequent technique is conducive to the yield for improving subsequent formed encapsulating structure and reliability, improves encapsulation effect
Rate.
The technique of the pre- bonding processing can be thermocompression bonding or pressurization bonding.Specifically, the thermocompression bonding includes
Pressurized treatments and heat treatment, the thermocompression bonding are suitable for just showing the bonding material of certain cohesive force in a heated condition
Material, such as: the bonding material be can photoetching dry film;The pressurization bonding only includes pressurized treatments, and the pressurization bonding is suitable
For without heating under conditions of i.e. with certain cohesive force bonding material, such as: the bonding material be chip bonding
Glue film or non-heated condition lower surface have the dry film of cohesive force.
In the present embodiment, in order to improve cohesive force of the bonded layer 120 in the pre- bonding process, described pre-
It is bonded the efficiency of processing, and improves the substrate 100 and bonded layer 120 in pre- bonding treated the bond strength, it is described
The technique of pre- bonding processing is thermocompression bonding.
Specifically, the pre- bonding handle the step of include: at least one of the chip 200 and substrate 100 into
The first pressurized treatments of row, and while carrying out first pressurized treatments, the chip 200 and the substrate 100 are carried out
First heat treatment.
In the present embodiment, in order to improve process operability, the technology difficulty of the pre- bonding processing is reduced, and improve and add
The precision of intermediate pressure section carries out first pressurized treatments backwards to the surface in the described second face 201 to be bonded to the chip 200
(as shown by the arrow in Figure 4), and while carrying out first pressurized treatments, to the chip 200 backwards to described second
The surface in face 201 to be bonded and the substrate back 102 carry out first heat treatment.
During the described first heat treatment, the bonded layer 120 can soften, therefore described second to key
The contact surface in conjunction face 201 and the bonded layer 120, the bonded layer 120 has cohesive force, thus in first pressurized treatments
Under the action of, so that the chip 200 and bonded layer 120 is realized preliminary bonding.
In the step of carrying out pre- bonding processing to the substrate 100 and chip 200, the process warm of first heat treatment
Degree is unsuitable too low, also unsuitable excessively high.If the technological temperature of first heat treatment is too low, it is difficult to reach the bonded layer
120 softening point temperature, the chip 200 and bonded layer 120 realize that the effect being tentatively bonded is accordingly poor, alternatively, in order to protect
Hinder the chip 200 and bonded layer 120 realizes the effect being tentatively bonded, the process time of the pre- bonding processing, phase need to be extended
The decline of packaging efficiency should be will lead to;If the technological temperature of first heat treatment is excessively high, the bonded layer 120 is easy hair
It is raw to melt, decompose, it will cause the yield of encapsulating structure and the decline of reliability instead.For this purpose, in the present embodiment, to the substrate
100 and chip 200 carry out pre- bonding processing the step of in, it is described first heat treatment technological temperature be 150 degrees Celsius to 250
Degree Celsius.
In the step of carrying out pre- bonding processing to the substrate 100 and chip 200, the pressure of first pressurized treatments is not
It is preferably too small, also it should not be too large.If the pressure of first pressurized treatments is too small, the chip 200 and bonded layer are also resulted in
120 realize that the effect being tentatively bonded is deteriorated;If the pressure of first pressurized treatments is excessive, it is easy to cause the chip
200 rupture, and accordingly will also result in the yield of encapsulating structure and the decline of reliability, and are also easy to shorten the bonding and set
Standby service life.For this purpose, being carried out in the step of pre- bonding is handled to the substrate 100 and chip 200, institute in the present embodiment
The pressure for stating the first pressurized treatments is 100 newton to 400 newton.
In order to improve packaging efficiency, the substrate 100 and chip 200 are carried out in the step of pre- bonding is handled, to described
Chip 200 carries out Quick-pressing backwards to the surface in the described second face 201 to be bonded, realizes the chip 200 and bonded layer 120
While preferable preliminary bonding effect, shorten the process time of the pre- bonding processing, therefore, the pre- bonding as much as possible
The process time of processing is unsuitable too long, be easy to cause the waste of process time, otherwise so as to cause the decline of packaging efficiency;But
It is that the process time of the pre- bonding processing is also unsuitable too short, if the process time of the pre- bonding processing is too short, the core
Piece 200 and bonded layer 120 realize that the effect being tentatively bonded is accordingly poor.For this purpose, in the present embodiment, to the substrate 100 and core
Piece 200 carried out in the step of pre- bonding processing, and the process time of the pre- bonding processing is 1 second to 30 seconds.
In the present embodiment, the substrate 100 and chip 200 are carried out in the step of pre- bonding is handled, first heating
The process time of the technological temperature of processing, the pressure size of first pressurized treatments and the pre- bonding processing should be reasonable
Collocation, to make packaging efficiency while ensureing that the chip 200 and bonded layer 120 preferably can realize preliminary bonding
It is improved.
Specifically, in the step of carrying out pre- bonding processing to the substrate 100 and chip 200, using the thermal head 320
First pressurized treatments are carried out backwards to the surface in the described second face 201 to be bonded to the chip 200, using the thermal head
320 pairs of chips 200 carry out first heat treatment backwards to the surface in the described second face 201 to be bonded, using described the
One heating plate 310 carries out first heat treatment to the substrate back 102.Wherein, the technique of first heat treatment
Temperature is the temperature of the thermal head 320 and the first heating plate 310.
Since several described chips 200 are placed on the substrate 100 by the thermal head 320 one by one, use
It, can be to the chip 200 after one chips 200 are placed in the predetermined position on the substrate 100 by the thermal head 320
The pre- bonding processing is carried out, technique is relatively simple, is conducive to improve packaging efficiency.
In the present embodiment, the pre- bonding handle the step of further include: at first pressurized treatments and the first heating
Before reason, the first vacuumize process is carried out, the process pressure of the pre- bonding processing is made to reach default pressure.
By first vacuumize process, be conducive to the air being discharged between the chip 200 and bonded layer 120, drop
The low probability that bubble is generated between the chip 200 and bonded layer 120, therefore after the pre- bonding processing, described second
Face 201 to be bonded can be fitted closely with the bonded layer 120, be conducive to promote the chip 200 and bonded layer 120 is realized just
Walk the effect of bonding.
Specifically, when first heating plate 310 and thermal head 320 start to warm up, while to the bonding apparatus
Chamber is vacuumized, until the chamber pressure of the bonding apparatus reaches default pressure.
In the step of carrying out pre- bonding processing to the substrate 100 and chip 200, the default pressure is smaller, in chamber
Vacuum degree it is accordingly higher, the fitting effect of second face 201 to be bonded and the bonded layer 120 is better;But if institute
Default too little pressure is stated, corresponding process costs and the process time that will increase evacuation process again, so as to cause packaging cost
Increase, the decline of packaging efficiency.For this purpose, carrying out the step of pre- bonding processing to the substrate 100 and chip 200 in the present embodiment
In rapid, the default pressure is greater than or equal to 5 kPas and less than 1 standard atmospheric pressure.
It should be noted that in other embodiments, it, can not also be to the bonding apparatus according to actual process situation
Chamber is vacuumized, i.e., the pre- bonding processing is carried out under normal pressure (i.e. 1 standard atmospheric pressure).Such as: when described second
When face to be bonded is the chip back, the chip back refers to the substrate bottom in the chip far from lead pad side
Face, compared with the chip front side, the flatness of the chip back is higher, therefore is carried out at the pre- bonding under normal pressure
Reason, is also able to maintain higher compactness between the chip and the bonded layer.
Moreover, carrying out the pre- bonding processing under normal pressure, accordingly also helps and reduce process costs and process time.
It should also be noted that, in other embodiments, when the substrate is used to realize permanently with several described chips
When bonding, i.e., when the first face to be bonded of the described substrate is in contact with the bonded layer, handled by the pre- bonding, it is also advantageous
In making that there is certain bond strength between the substrate and bonded layer, to be conducive to further increase the substrate and chip
Between bond strength.
In conjunction with reference Fig. 5 to Fig. 7, film-type encapsulating material 255 (as shown in Figure 5) is provided;It will several described chips 200
After being placed on the substrate 100, using hot pressing technique, the substrate 100 and several described chips 200 is made to pass through the key
It closes layer 120 and realizes bonding, and be filled in the encapsulating material 255 between several described chips 200 and substrate 100 and cover
Several described chips 200, the encapsulating material 255 after the hot pressing technique are used to be used as encapsulated layer 250 (as shown in Figure 7).
The hot pressing technique is the technique pressurizeed under preset temperature, by the hot pressing technique, is made described
Encapsulating material 255 softens, and under the conditions of certain pressure, between the encapsulating material insertion adjacent chips 200 after making softening,
To be close to 100 surface of bonded layer that several described chips 200 and several described chips 200 expose.Moreover, described
Under the action of hot pressing technique, contact surface in the described second face 201 and the bonded layer 120 to be bonded, the bonded layer 120
With cohesive force, so that the substrate 100 and several described chips 200 be made to realize complete bonding by the bonded layer 120.
Compared to the scheme for being bonded, using moulding technology to form encapsulated layer again for first realizing chip and substrate, due to described
Encapsulating material 255 is film-type, can reduce the side knock that the chip 200 is subject to during the hot pressing technique
Power improves to form envelope so that the probability that the chip 200 drifts about during the hot pressing technique be effectively reduced
The yield and reliability of assembling structure.Specifically, compared with using powdered or liquid encapsulating material, by using film-type
Encapsulating material significantly reduces the lateral impact forces that the chip 200 is subject to during the hot pressing technique.
Moreover, the hot pressing technique synchronizes the bonding for realizing the substrate 100 and chip 200, the base is being ensured
While there is higher bond strength between plate 100 and chip 200, the process-cycle of packaging technology is accordingly also shortened, thus
Improve packaging efficiency;Therefore, by the hot pressing technique, yield and reliability to encapsulating structure can preferably be balanced
Requirement and requirement to packaging efficiency.
In addition, the thickness of the encapsulated layer 250 is advantageously reduced by the hot pressing technique, so that encapsulation knot
Structure it is smaller, while ensureing the yield and reliability of encapsulating structure, be conducive to meet encapsulating structure miniaturization, miniature
The demand of change.
In the present embodiment, the hot pressing technique be hot press forming technology (i.e. compression molding technique) or
Hot pressing attachment process (i.e. lamination technique).
Specifically, the step of hot pressing technique includes: that the encapsulating material 255 is placed in several described chips
On 200;After the encapsulating material 255 is placed on several described chips 200, the second vacuumize process and the second heating are carried out
Processing, makes the process pressure of the hot pressing technique reach default pressure, the technological temperature of the hot pressing technique is made to reach pre-
If temperature;Under the default pressure and preset temperature, the second pressurized treatments are carried out to the substrate 100 and encapsulating material 255
To preset time, if making, the encapsulating material 255 is filled between several described chips 200 and substrate 100 and covering is described
Dry chip 200, and the substrate 100 and several described chips 200 is made to realize bonding;In the default pressure and default temperature
After lower progress second pressurized treatments of degree, under the preset temperature, heat cure processing is carried out to the encapsulating material 255,
Form the encapsulated layer 250.
Specifically, it is illustrated so that the hot pressing technique is hot press forming technology as an example.As shown in figure 5, providing hot pressing
Equipment (not shown) is provided with the second heating plate 330 and third heating plate 340 in the chamber (not shown) of the hot-press equipment;
The substrate 100 is placed in second heating plate 330;After the substrate 100 is placed in second heating plate 330,
The encapsulating material 255 is placed on several described chips 200;The encapsulating material 255 is placed in several described chips
After on 200, the third heating plate 340 is placed on the encapsulating material 255;The third heating plate 340 is placed in described
After on encapsulating material 255, the chamber of the hot-press equipment is vacuumized, the chamber pressure of the hot-press equipment is made to reach pre-
If pressure, and second heating plate 330 and third heating plate 340 are heated to preset temperature;As shown in fig. 6, described default
Under pressure and preset temperature, by second heating plate 330 and third heating plate 340 to the substrate 100 and encapsulating material
255 carry out the second pressurized treatments (as shown by the arrows in Figure 6) to preset time, if it is described to be filled in the encapsulating material 255
Between dry a chip 200 and substrate 100 and several described chips 200 are covered, and make the substrate 100 and several described cores
Piece 200 realizes complete bonding;As shown in fig. 7, after carrying out the second pressurized treatments under the default pressure and preset temperature, in institute
It states under preset temperature, to the encapsulating material 255 progress heat cure processing (as shown in Figure 6), forms the encapsulated layer 250.
In other embodiments, when the hot pressing technique be hot pressing attachment process when, then using hot pressing attaching device into
The row hot pressing technique, the hot pressing attaching device accordingly include that can heat the roll shaft of pressurization and can heat the flat of pressurization
Platform, the encapsulating material 255 are wound on the roll shaft.It wherein, can not only be by the encapsulating material by the roll shaft
255 are placed on the chip 200, and synchronize the effect for realizing heating and pressurization, that is to say, that the roll shaft is by the envelope
After package material 255 is placed on the chip 200, the bonding and encapsulation of the substrate 100 and the chip 200 can be realized
The formation of layer 250, technique are relatively simple.
The encapsulated layer 250 can play insulation, sealing and moisture-proof effect, can reduce the chip 200 it is impaired,
Probability that is contaminated or being oxidized, and then be conducive to improve the yield and reliability of formed encapsulating structure.
In the present embodiment, the base materials of the encapsulated layer 250 are epoxy resin.Epoxy resin has shrinking percentage low, viscous
Knot property good, good corrosion resistance, excellent electrical property and the advantages that cost is relatively low, therefore it is widely used as electronic device and integrated circuit
Encapsulating material.Specifically, the mass percentage content of epoxy resin is 20% to 40%.
Correspondingly, the base materials of the encapsulating material 255 are epoxy resin in the present embodiment.
Base materials are that the encapsulating material 255 of epoxy resin is the material layer that can soften after reaching softening point temperature,
To avoid the encapsulating material 255 from being broken under the pressure condition of the hot pressing technique.
In the step of providing encapsulating material 255, the thickness T2 (as shown in Figure 5) of the encapsulating material 255 should not mistake
It is small, also it should not be too large.If the thickness T2 of the encapsulating material 255 is too small, after the hot pressing technique, formed encapsulated layer
250 are difficult to that 120 surface of bonded layer that several described chips 200 and the chip 200 expose is completely covered;If the envelope
The problem of thickness T2 of package material 255 is excessive, then can cause angularity, but also will cause waste of material and encapsulating structure
The problem of volume increases.For this purpose, the thickness T2 of the encapsulating material 255 is 40 μm to 200 μm in the present embodiment.
Wherein, the thickness of the thickness T2 of the encapsulating material 255 is depending on the thickness of the chip 200, thus protecting
While demonstrate,proving the coverage effect of the encapsulated layer 250, the generation of side effect is reduced.
Specifically, the thickness T2 of the encapsulating material 255 is 40 μm to 50 μm, or is 80 μm to 100 μm.Both are thick
The encapsulating material 255 of metric lattice is the common film layer that pre-production is good in packaging technology, therefore directly by ready-made encapsulating material
255 are placed on several described chips 200, to avoid additional technique to form the encapsulating material 255, are conducive to
The step of simplifying the packaging technology improves packaging efficiency.
In the present embodiment, after the third heating plate 340 is placed on the encapsulating material 255, start to the hot pressing
The chamber of equipment is vacuumized, and starts to heat first heating plate 330 and the second heating plate 340, is made described
The chamber pressure of hot-press equipment reaches default pressure, makes first heating plate 330 and the second heating plate 340 to preset temperature,
To provide Process ba- sis for subsequent second pressurized treatments.
In the hot pressing technique the step of, the preset temperature is unsuitable too small, also should not be too large.If described default
Temperature is too small, then is difficult to reach the softening point temperature of the encapsulating material 255, i.e., the described encapsulating material 255 is difficult to reach half admittedly
Change state, during the processing of subsequent heat-insulation pressure keeping, the encapsulating material 255 is difficult to be close to several described chips 200
And 120 surface of bonded layer that the chip 200 exposes, so as to cause the degradation of the encapsulated layer 250;If described pre-
If temperature is excessively high, the quality and performance of the encapsulating material 255 can be not only reduced, is also easy to produce the performance of the chip 200
Raw adverse effect the problem of encapsulated layer 250 is easy to appear contraction, is easily reduced institute's shape moreover, when subsequent cooling instead
At the yield and reliability of encapsulating structure.For this purpose, in the present embodiment, the hot pressing technique the step of in, the default temperature
Degree is 120 degrees Celsius to 180 degrees Celsius.
In the hot pressing technique the step of, the default pressure is unsuitable too small, also should not be too large.The default pressure
Smaller, the Chamber vacuum degree of the hot-press equipment is higher, increases vacuum degree and is conducive to that the encapsulating material 255 and the core is discharged
The residual air of the contact surface of the residual air of the contact surface of piece 200 and the encapsulating material 255 and the bonded layer 120,
The bubble at the contact surface is reduced, to reduce the probability that the chip 200 aoxidizes;But the if default pressure
Strong too small, i.e., vacuum degree is excessively high, and it will cause the increases of process costs and process time.For this purpose, in the present embodiment, in the heat
In the step of process for pressing, in order to guarantee that the technological effect of the hot pressing technique, the default pressure are 5 kPas to 15,000
Pa.
In the hot pressing technique the step of, the pressure of second pressurized treatments is unsuitable too small, also should not be too large.Institute
It states hot-press equipment and imposes on 340 certain pressure of first heating plate 330 and the second heating plate, and the pressure is transferred to described
Encapsulating material 255 and substrate 100, thus by second heating plate 330 and third heating plate 340 to 100 He of substrate
Encapsulating material 255 carries out second pressurized treatments, therefore the pressure of second pressurized treatments is bigger, the encapsulating material
255 and the pressure that is subject to of substrate 100 it is then bigger, the encapsulating material 255 is filled in several described chips 200 and substrate 100
Between and the covering chip 200 effect it is better, and the bonding effect of the substrate 100 and several chips 200
Also better;But if the pressure of second pressurized treatments is excessive, it is easy to cause the chip 200 to rupture, accordingly
It will also result in the yield of encapsulating structure and the decline of reliability, and be also easy to shorten the service life of the hot-press equipment.For
This, in the present embodiment, the hot pressing technique the step of in, the pressure of second pressurized treatments is 0.1 megapascal to 10,000,000
Pa.
Specifically, according to the actual performance of hot-press equipment, when the hot pressing technique is hot press forming technology, described the
The pressure of two pressurized treatments is 3 megapascal to 10 megapascal, when the hot pressing technique is hot pressing attachment process, second pressurization
The pressure of processing is 0.1 megapascal to 3 megapascal.
In the hot pressing technique the step of, the preset time is unsuitable too short, also unsuitable too long.If described default
Time is too short, then is easily reduced the encapsulating material 255 and is filled between several described chips 200 and substrate 100 and covers
The effect of the chip 200 is also easy to reduce the bonding effect of the substrate 100 and several chips 200;If described
Preset time is too long, then be easy to cause the waste of process time, so as to cause the decline of packaging efficiency.For this purpose, in the present embodiment,
In the hot pressing technique the step of, the preset time is 30 seconds to 60 seconds.
In the present embodiment, the hot pressing technique the step of in, the preset temperature, default pressure, at the second pressurization
The pressure of reason and the time that the second pressurized treatments are carried out under the preset temperature and default pressure should be reasonably combined, from
And while ensureing the yield and reliability of formed encapsulating structure, it is improved packaging efficiency.
Moreover, the technology type according to selected by the hot pressing technique, reasonably adjusts the preset temperature, default pressure
The time of the second pressurized treatments is carried out by force and under the preset temperature and default pressure, to guarantee described hot-forming
Technique and hot pressing attachment process have close or identical technological effect.
After second pressurized treatments, heat cure processing is carried out to the encapsulating material 255, the heat cure processing is used
Solidify the required energy being crosslinked and time in providing 255 material of encapsulating material and realizing.Specifically, it is handled in the heat cure
During, keep the temperature the encapsulating material 255 under the preset temperature environment, the polymer in encapsulating material 255
Resin is changed into gel and is gradually hardened, and the polymer chain under solid state can not move due to being crosslinked mutually, fettering mutually,
There is higher hardness and high performance encapsulated layer 250 to realize the effect of heat cure, and then be formed.
Correspondingly, the process time of the heat cure processing is unsuitable too short, also not in the hot pressing technique the step of
It is preferably too long.If the process time of the heat cure processing is too short, the effect phase strain differential of heat cure processing, so as to cause institute
State the quality and performance decline of encapsulated layer 250;If the process time of the heat cure processing is too long, when be easy to causeing technique
Between waste, so as to cause the decline of packaging efficiency.For this purpose, in the present embodiment, the hot pressing technique the step of in, it is described
The process time of heat cure processing is 300 seconds to 600 seconds.
In the present embodiment, after heat cure processing, natural cooling is carried out under normal pressure, to gradually decrease the envelope
The internal stress (internal stress) of layer 250 is filled, the probability for the problems such as plate is curved, plate is stuck up occur is reduced.
It should be noted that in other embodiments, when the substrate is used to realize persistent key with several described chips
When conjunction, i.e., when the first face to be bonded of the described substrate is in contact with the bonded layer, by the hot pressing technique, also help
It realizes the complete bonding for making the substrate and bonded layer, is also beneficial to ensure the yield and reliability of formed encapsulating structure.
In conjunction with reference Fig. 8, it is also necessary to explanation, in the present embodiment, due to the substrate 100 be used for and it is described several
Chip 200 realizes interim bonding, and the substrate 100 is used in the potting process, rises to several described chips 200
To supporting role, therefore, for the progress of follow-up process, after forming the encapsulated layer 250, further includes: to the substrate 100
(as shown in Figure 7) and several chips 200 carry out solution bonding (De-bonding) processing.
It is handled, the substrate 100 and several chips 200 is separated, to remove the base by the solution bonding
Plate 100 and adhesive layer 110 (as shown in Figure 7).
In the present embodiment, the substrate 100 and the bonded layer 120 realize interim bonding, phase by the adhesive layer 110
Ying Di, during solution bonding processing, can chemically, the side such as mechanical stripping, grinding technics, reduction process
Formula removes the substrate 100 and adhesive layer 110.In other embodiments, the substrate 100 can also be removed using other modes
With adhesive layer 110.
Specifically, the adhesive layer 110 is chip bonding glue film, therefore can be using the side for removing the adhesive layer 110
Formula removes the substrate 100.
In the present embodiment, bond strength with higher between the bonded layer 120 and several described chips 200, and
The encapsulated layer 250 is close to 120 surface of bonded layer that the chip 200 and the chip 200 expose, therefore in the solution key
After conjunction processing, the bonded layer 120 remains to cover the chip 200, so that good Process ba- sis is provided for follow-up process,
Be conducive to improve the yield and reliability of formed encapsulating structure.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (15)
1. a kind of packaging method characterized by comprising
Substrate is provided, the face to be bonded of the substrate is the first face to be bonded;
Several chips are provided, the face to be bonded of the chip is the second face to be bonded;
Film-type encapsulating material is provided;
Bonded layer is formed at least one face in the described first face to be bonded and second face to be bonded;
After forming bonded layer at least one face in the described first face to be bonded and second face to be bonded, make described the
One face to be bonded and second face to be bonded are oppositely arranged, and the chip is placed on the substrate;
After the chip is placed on the substrate, using hot pressing technique, pass through the substrate and several described chips
The bonded layer realizes bonding, and if being filled in the encapsulating material between several described chips and substrate and described in covering
A chip is done, the encapsulating material after the hot pressing technique is used to be used as encapsulated layer.
2. packaging method as described in claim 1, which is characterized in that after the chip is placed on the substrate, described
Before hot pressing technique, further includes: carry out pre- bonding processing to the substrate and chip.
3. packaging method as claimed in claim 2, which is characterized in that the technique of the pre- bonding processing is thermocompression bonding or adds
Pressure bonding.
4. packaging method as claimed in claim 2, which is characterized in that the technique of the pre- bonding processing is thermocompression bonding, institute
The step of stating pre- bonding processing includes: to carry out the first pressurized treatments at least one of the chip and substrate, and carrying out
While first pressurized treatments, the first heat treatment is carried out to the chip and the substrate.
5. packaging method as claimed in claim 4, which is characterized in that in first pressurized treatments the step of, to described
Chip carries out first pressurized treatments backwards to the surface in the described second face to be bonded;
In the described first heat treatment the step of, to the chip backwards to the surface in the described second face to be bonded and described
Substrate back carries out first heat treatment.
6. packaging method as claimed in claim 4, which is characterized in that the step of pre- bonding is handled further include: described
Before first pressurized treatments and the first heat treatment, the first vacuumize process is carried out, makes the process pressure of the pre- bonding processing
Reach default pressure.
7. packaging method as described in claim 1, which is characterized in that the step of hot pressing technique includes: by the envelope
Package material is placed on several described chips;
After the encapsulating material is placed on several described chips, the second vacuumize process and the second heat treatment are carried out, is made
The process pressure of the hot pressing technique reaches default pressure, and the technological temperature of the hot pressing technique is made to reach preset temperature;
Under the default pressure and preset temperature, to the substrate and encapsulating material carry out the second pressurized treatments to it is default when
Between, be filled in the encapsulating material between several described chips and substrate and the covering chip, and make the substrate and
Several described chips realize bonding;
After carrying out second pressurized treatments under the default pressure and preset temperature, under the preset temperature, to described
Encapsulating material carries out heat cure processing, forms the encapsulated layer.
8. packaging method as described in claim 1, which is characterized in that in the step of forming the bonded layer, described first
The bonded layer is formed on face to be bonded.
9. packaging method as described in claim 1, which is characterized in that the hot pressing technique is hot press forming technology or hot pressing
Attachment process.
10. packaging method as claimed in claim 4, which is characterized in that carry out pre- bonding processing to the substrate and chip
In step, the process time of the pre- bonding processing is 1 second to 30 seconds, the pressure of first pressurized treatments be 100 newton extremely
The technological temperature of 400 newton, first heat treatment are 150 degrees Celsius to 250 degrees Celsius.
11. packaging method as claimed in claim 6, which is characterized in that carry out pre- bonding processing to the substrate and chip
In step, the default pressure is 5 kPas to one standard atmospheric pressures.
12. packaging method as claimed in claim 7, which is characterized in that described default in the hot pressing technique the step of
Pressure is 5 kPas to 15 kPas, and the preset temperature is 120 degrees Celsius to 180 degrees Celsius, the pressure of second pressurized treatments
For 0.1 megapascal to 10 megapascal, the preset time is 30 seconds to 60 seconds, the process time of the heat cure processing be 300 seconds extremely
600 seconds.
13. packaging method as described in claim 1, which is characterized in that the encapsulating material with a thickness of 40 μm to 200 μm.
14. packaging method as described in claim 1, which is characterized in that the substrate is device wafers, carrier wafer or face
Plate.
15. packaging method as described in claim 1, which is characterized in that in the step of providing several chips, in the chip
It is formed with pad, the chip surface for exposing the pad is chip front side, and the face opposite with the chip front side is chip back;
Second face to be bonded is the chip front side or chip back.
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CN202111338313.4A CN114050113A (en) | 2018-08-06 | 2018-08-06 | Packaging method |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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CN110379721A (en) * | 2019-07-30 | 2019-10-25 | 中芯集成电路(宁波)有限公司 | Fan-out package method and encapsulating structure |
CN111128760A (en) * | 2019-12-27 | 2020-05-08 | 广东工业大学 | Chip packaging method and chip packaging structure based on fan-out type packaging process |
CN111377393A (en) * | 2018-12-27 | 2020-07-07 | 中芯集成电路(宁波)有限公司上海分公司 | MEMS packaging structure and manufacturing method thereof |
CN111696876A (en) * | 2019-03-15 | 2020-09-22 | 细美事有限公司 | Bonding apparatus and bonding method |
CN113030706A (en) * | 2021-03-12 | 2021-06-25 | 长江存储科技有限责任公司 | Failure analysis sample manufacturing method and failure analysis sample |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002270712A (en) * | 2001-03-14 | 2002-09-20 | Sony Corp | Semiconductor element integrated multi-layer wiring board, semiconductor element integrated device, and manufacturing method therefor |
CN1868062A (en) * | 2003-09-09 | 2006-11-22 | 三洋电机株式会社 | Semiconductor module including circuit device and insulating film, method for manufacturing same, and application of same |
CN101288351A (en) * | 2005-10-14 | 2008-10-15 | 株式会社藤仓 | Printed wiring board and method for manufacturing printed wiring board |
TW201201288A (en) * | 2010-06-30 | 2012-01-01 | Siliconware Precision Industries Co Ltd | Chip-sized package and fabrication method thereof |
CN103632987A (en) * | 2012-08-24 | 2014-03-12 | 台湾积体电路制造股份有限公司 | Carrier warpage control for three dimensional integrated circuit (3DIC) stacking |
CN104145328A (en) * | 2012-03-07 | 2014-11-12 | 东丽株式会社 | Method and apparatus for manufacturing semiconductor device |
US20150035146A1 (en) * | 2013-08-05 | 2015-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through Package Via (TPV) |
CN105244341A (en) * | 2015-09-01 | 2016-01-13 | 华进半导体封装先导技术研发中心有限公司 | Semiconductor device FOWLP packaging structure and manufacturing method thereof |
CN105339410A (en) * | 2014-06-04 | 2016-02-17 | 日立化成株式会社 | Film-shaped epoxy resin composition, method for manufacturing film-shaped epoxy resin composition, and method for manufacturing semiconductor device |
US20160218082A1 (en) * | 2015-01-22 | 2016-07-28 | Qualcomm Incorporated | Damascene re-distribution layer (rdl) in fan out split die application |
US9524958B2 (en) * | 2013-06-27 | 2016-12-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of individual die bonding followed by simultaneous multiple die thermal compression bonding |
CN106415823A (en) * | 2014-03-31 | 2017-02-15 | 信越化学工业株式会社 | Semiconductor device, layered semiconductor device, sealed-then-layered semiconductor device, and manufacturing methods therefor |
CN106876291A (en) * | 2016-12-30 | 2017-06-20 | 清华大学 | A kind of thin chip flexibility is fanned out to method for packing and prepared encapsulating structure |
CN108335986A (en) * | 2017-09-30 | 2018-07-27 | 中芯集成电路(宁波)有限公司 | A kind of wafer scale system packaging method |
-
2018
- 2018-08-06 CN CN202111338313.4A patent/CN114050113A/en not_active Withdrawn
- 2018-08-06 CN CN201810883152.9A patent/CN109003907B/en active Active
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002270712A (en) * | 2001-03-14 | 2002-09-20 | Sony Corp | Semiconductor element integrated multi-layer wiring board, semiconductor element integrated device, and manufacturing method therefor |
CN1868062A (en) * | 2003-09-09 | 2006-11-22 | 三洋电机株式会社 | Semiconductor module including circuit device and insulating film, method for manufacturing same, and application of same |
CN101288351A (en) * | 2005-10-14 | 2008-10-15 | 株式会社藤仓 | Printed wiring board and method for manufacturing printed wiring board |
TW201201288A (en) * | 2010-06-30 | 2012-01-01 | Siliconware Precision Industries Co Ltd | Chip-sized package and fabrication method thereof |
CN104145328A (en) * | 2012-03-07 | 2014-11-12 | 东丽株式会社 | Method and apparatus for manufacturing semiconductor device |
CN103632987A (en) * | 2012-08-24 | 2014-03-12 | 台湾积体电路制造股份有限公司 | Carrier warpage control for three dimensional integrated circuit (3DIC) stacking |
US9524958B2 (en) * | 2013-06-27 | 2016-12-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of individual die bonding followed by simultaneous multiple die thermal compression bonding |
US20150035146A1 (en) * | 2013-08-05 | 2015-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through Package Via (TPV) |
CN106415823A (en) * | 2014-03-31 | 2017-02-15 | 信越化学工业株式会社 | Semiconductor device, layered semiconductor device, sealed-then-layered semiconductor device, and manufacturing methods therefor |
CN105339410A (en) * | 2014-06-04 | 2016-02-17 | 日立化成株式会社 | Film-shaped epoxy resin composition, method for manufacturing film-shaped epoxy resin composition, and method for manufacturing semiconductor device |
US20160218082A1 (en) * | 2015-01-22 | 2016-07-28 | Qualcomm Incorporated | Damascene re-distribution layer (rdl) in fan out split die application |
CN105244341A (en) * | 2015-09-01 | 2016-01-13 | 华进半导体封装先导技术研发中心有限公司 | Semiconductor device FOWLP packaging structure and manufacturing method thereof |
CN106876291A (en) * | 2016-12-30 | 2017-06-20 | 清华大学 | A kind of thin chip flexibility is fanned out to method for packing and prepared encapsulating structure |
CN108335986A (en) * | 2017-09-30 | 2018-07-27 | 中芯集成电路(宁波)有限公司 | A kind of wafer scale system packaging method |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111377393A (en) * | 2018-12-27 | 2020-07-07 | 中芯集成电路(宁波)有限公司上海分公司 | MEMS packaging structure and manufacturing method thereof |
CN111377393B (en) * | 2018-12-27 | 2023-08-25 | 中芯集成电路(宁波)有限公司上海分公司 | MEMS packaging structure and manufacturing method thereof |
CN109799663A (en) * | 2019-01-25 | 2019-05-24 | 中山大学 | Electronics paper product and its packaging method based on stretchable substrate |
CN111696876A (en) * | 2019-03-15 | 2020-09-22 | 细美事有限公司 | Bonding apparatus and bonding method |
CN111696876B (en) * | 2019-03-15 | 2023-09-19 | 细美事有限公司 | Bonding device and bonding method |
CN110379721A (en) * | 2019-07-30 | 2019-10-25 | 中芯集成电路(宁波)有限公司 | Fan-out package method and encapsulating structure |
CN111128760A (en) * | 2019-12-27 | 2020-05-08 | 广东工业大学 | Chip packaging method and chip packaging structure based on fan-out type packaging process |
CN111128760B (en) * | 2019-12-27 | 2020-09-15 | 广东工业大学 | Chip packaging method and chip packaging structure based on fan-out type packaging process |
CN113030706A (en) * | 2021-03-12 | 2021-06-25 | 长江存储科技有限责任公司 | Failure analysis sample manufacturing method and failure analysis sample |
CN113030706B (en) * | 2021-03-12 | 2021-11-23 | 长江存储科技有限责任公司 | Failure analysis sample manufacturing method and failure analysis sample |
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CN109003907B (en) | 2021-10-19 |
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