JP2004072009A - Semiconductor device, and manufacturing method thereof - Google Patents

Semiconductor device, and manufacturing method thereof Download PDF

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JP2004072009A
JP2004072009A JP2002232452A JP2002232452A JP2004072009A JP 2004072009 A JP2004072009 A JP 2004072009A JP 2002232452 A JP2002232452 A JP 2002232452A JP 2002232452 A JP2002232452 A JP 2002232452A JP 2004072009 A JP2004072009 A JP 2004072009A
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semiconductor chip
adhesive layer
wire
insulating film
insulating
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JP3912223B2 (en
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Kinichi Kumagai
熊谷　欣一
Mitsuhisa Watabe
渡部　光久
Akira Takashima
高島　晃
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Fujitsu Ltd
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-cost semiconductor device and the manufacturing method thereof which relaxes the restrictions related to the shapes of its mounted semiconductor chips, etc., with respect to a stacked package wherein a plurality of semiconductor chips are mounted on a wiring board in a laminated manner and in a face-up state, and the wire-bonding electrode pattern portions of the insulating board and the wire-bonding electrode patterns of the semiconductor chips are connected respectively by wire bondings. <P>SOLUTION: In the stacked package, the thickness of an insulating bonding layer whereby semiconductor chips are bonded to each other is made not smaller than at least the height ranging from the surface of a lower-side semiconductor chip to the uppermost point of the wire loop of its bonding wire. That is, the region present above the surface of the lower-side semiconductor chip which is occupied by the insulating bonding layer is so formed as to overlap at least partially with the wire-bonding electrode region of the lower-side semiconductor chip and that its bonding wire is integrated into the insulating bonding layer. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、複数個の半導体チップを積層させ搭載することにより実装密度を高めたパッケージ構造を有する半導体装置（以下「スタックドパッケージ」という）及び製造方法に関し、特に、半導体チップをフェイスアップ状態で、表面側配線層が中間絶縁層を貫通して形成された貫通孔を通して裏面側配線層と電気的に接続された実装用外部端子を有する配線基板上に搭載され、前記配線基板の表面側配線面に形成されたワイヤーボンディング電極パターンとをワイヤーボンディングにより接続することを特徴とする半導体装置及びその製造方法に関する。
【０００２】
【従来の技術】
近年、携帯機器及びパソコン等の小型化にともない、半導体装置の実装基板への実装に際して、高密度化が要求されている。しかし、上記機器では半導体装置の低コストも求められており、低コストのスタックドパッケージ技術が注目されている。
【０００３】
図８に、低コストのスタックドパッケージ技術を適用した半導体装置の例を示す。ここで、図８の半導体装置は下側半導体チップ１と、上側半導体チップ２と、裏面に実装用外部端子（すなわち半田ボール５）を有する配線基板７と、ボンディングワイヤー４と、封止樹脂６と絶縁性フィルム状接着層３とから構成されており、上側半導体チップの裏面（非回路形成面）を、下側半導体チップ１の回路形成面上に、２０〜５０μｍ程度の厚さを有する上記絶縁性フィルム状接着層３を介して接着し、上記配線基板７の表面側配線形成面と下側半導体チップ１の裏面（非回路形成面）とを絶縁性フィルム状接着層３を介して接着し、下側半導体チップの回路形成面上のワイヤーボンディング電極パターン及び上側半導体チップのワイヤーボンディング電極パターンと、上記配線基板の表面側配線形成面上のワイヤーボンディング電極パターンとをボンディングワイヤー４で接続した後、封止樹脂６で封止することにより製造されている。
【０００４】
しかし、図８に示すように、スタックドパッケージ内に搭載し、積層した各半導体チップの回路形成面上のワイヤーボンディング電極パターンと実装用外部端子を有する配線基板上のワイヤーボンディング電極パターンとを接続する手段として、ワイヤーボンディングを使用する場合には、積層する半導体チップはすべて配線基板に対してフェイスアップ状態で搭載する必要があり、下側半導体チップ面上のワイヤーボンディング電極パターンに対しワイヤーボンディング時に、上側の半導体チップが障害とならないようにするには、上側の半導体チップのサイズ及び形状に制限があった。
【０００５】
そこで、上記制限を緩和する為、半導体チップの積層に係わる構造及びその製造方法には、様々なものが提案され、実現された。
例えば、図９に示す半導体装置もスタックドパッケージの例である。ここで、図９は半導体装置の断面構造を示しており、上記半導体装置は、下側半導体チップ１と、上側半導体チップ２と、裏面に実装用外部端子（すなわち半田ボール５）を有する配線基板７と、絶縁性フィルム状接着層３と、金属バンプ８と、ボンディングワイヤー４と、封止樹脂６から構成されており、上記上下の各半導体チップの裏面（非回路形成面）同士を絶縁性フィルム状接着層３を介して接着した半導体チップの組を、上記下側半導体チップの回路形成面と配線基板の上側配線面とを、金属バンプ８を介して積み重ね（以下「フリップチップ構造」という。）、下側半導体チップと配線基板の間にはアンダーフィル材を充填し、フェイスアップ状態である上側半導体チップ２のワイヤーボンディング電極パターンと配線基板７のワイヤーボンディング電極パターンはボンディングワイヤー４で接続した後、封止樹脂６で封止することにより、製造されている。
【０００６】
ところで、上記の説明中、アンダーフィル材とは、エポキシ樹脂等にフィラー（材質がＳｉＯ２等である、粒径２０〜１００μ程度の粒状物質をいう）を含ませ、熱硬化性を有するものをいう。
また、図１０に示す半導体装置も例としてあげられる。ここで、図１０は半導体装置の断面構造を示しているが、上記半導体装置は、下側半導体チップ１と、上側半導体チップ２と、実装用外部端子（すなわち半田ボール５）を有する配線基板７と、スペーサー９と、ボンディングワイヤー４と、封止樹脂６と絶縁性フィルム状接着層３とから構成されており、ワイヤーボンディングができる程度の隙間をあくように、下側半導体チップ１の回路形成面上に２００μｍ〜３００μの高さのスペーサー９を搭載し、上側半導体チップ２の裏面（非回路形成面）を上記スペーサー９を介して、下側半導体チップの回路形成面上に搭載し、下側半導体チップ１裏面（非回路形成面）と配線基板７の上側配線面を絶縁性フィルム状接着層３を介して積み重ね（以下「スペーサー構造」という）、下側半導体チップの回路形成面上のワイヤーボンディング電極パターン及び上側半導体チップの回路形成面上のワイヤーボンディング電極パターンとを、配線基板の上側配線面のワイヤーボンディング電極パターンとをボンディングワイヤー４で接続した後、封止樹脂６で封止することにより製造されている。
【０００７】
【発明が解決しようとする課題】
図９のフリップチップ構造をとる半導体装置の場合、上側半導体チップと下側半導体チップは裏面同士で接続していること、及び、下側半導体チップの回路形成面内のワイヤーボンディング電極パターンと配線基板の上側配線面のワイヤーボンディング電極パターンとは金属バンプで接続されるので、下側半導体チップのワイヤーボンディング電極パターンと配線基板のワイヤーボンディング電極パターンの接続において、上側半導体チップの形状及び大きさに係わる制限が緩和された。しかし、下側半導体チップ及び配線基板のワイヤーボンディング電極パターン上に金属バンプを形成する工程、上記金属バンプを接続する工程、アンダーフィル材の注入工程が増加し、コストアップは避けられない。また、金属バンプによる接合技術はワイヤーボンディングによる接合技術に比較し、成熟していない為、金属バンプによる接合点が増加すると歩留りの低下を招いていた。
【０００８】
他方、図１０のスペーサー構造をとる半導体装置の場合でも、上側半導体チップの回路形成面上のワイヤーボンディング電極パターンと配線基板の上側配線面上のワイヤーボンディング電極パターンをボンディングワイヤーによる接続を行う目的で、上側半導体チップと下側半導体チップの間にスペーサーを挟んだ為、その隙間を利用してボンディングが行えるから、上側半導体チップの形状及び大きさに係わる制限が緩和された。しかし、上記スペーサーを搭載する工程の追加、及び、スペーサーに使用する部材が追加となるので、コストアップは避けられない。
【０００９】
そこで、本発明は、上記課題に鑑み、それ程工程及び部材の追加がなく、低コスト、かつ、上側半導体チップの形状及び大きさに係わる制限が緩和されたスタックドパッケージを実現する半導体製造装置及びその製造方法を提供することを目的とする。
【００１０】
【課題を解決するための手段】
上記目的を達成する為に、請求項１に係わる本発明は、少なくとも、第１の半導体チップと、第２の半導体チップとが、表面側配線層が中間絶縁層を貫通して形成された貫通孔を通して裏面側配線層と電気的に接続された実装用外部端子を有する配線基板に搭載され、封止用樹脂にて封止されている半導体装置であって、
前記配線基板の表面と、前記第１の半導体チップの非回路形成面とが第１の絶縁性接着層を介して接着され、前記第１の半導体チップのワイヤーボンディング電極パターンを有する回路形成面と前記第２の半導体チップの非回路形成面とが前記第１の半導体チップのワイヤボンディング電極パターンの領域の少なくとも一部を含むように、第２の絶縁性接着層を介して接着され、前記配線基板の前記表面側配線層に形成されたワイヤーボンディング電極パターンと、前記第１の半導体チップ及び前記第２の半導体チップのワイヤーボンディング電極パターンを有する回路形成面のワイヤーボンディング電極パターンとが、ボンディングワイヤーで接続され、かつ、前記第２の絶縁性接着層は少なくとも前記第１の半導体チップに接続形成されたボンディングワイヤーのワイヤーループ最頂点高さより厚く形成されていることを特徴とする半導体装置を提供する。
【００１１】
上記の発明によれば、上下の半導体チップの間の絶縁性フィルム状接着層の厚さを厚くして、下側半導体チップの表面に貼られたボンディングワイヤーを傷つけない程度に上下半導体チップ間の隙間を空けることができる。従って、下側半導体チップの形状及び大きさに対して、上側の半導体チップの形状及び大きさ制限を設けること必要がない。
【００１２】
課題を解決する為、請求項２に係わる発明は、
前記第２の絶縁性フィルム状接着層の全部又は一部に、前記ボンディングワイヤーを内在させることができる程度の粘度を与える工程と、前記ボンディングワイヤーを前記第２の絶縁性フィルム状接着層に内在させると同時に前記第２の半導体チップを前記第１の半導体チップの回路形成面上に搭載する工程と、前記第２の絶縁性フィルム状接着層を固まらせる工程を少なくとも含むことを特徴とする半導体装置の製造方法を提供する。
【００１３】
上記の発明によれば、まず、下側半導体チップの裏面（非回路形成面）と配線基板の上側配線面とを接着した後、下側半導体チップの回路形成面上のボンディングワイヤー電極パターンと配線基板の上側配線面上のボンディングワイヤー電極パターンとをボンディングワイヤーにて接続し、上下の半導体チップを第２の絶縁性フィルム状接着層を介して接着するとき、ボンディングワイヤーを内在することができる程度に上記第２の絶縁性フィルム上接着層の粘度をさげておき、下側半導体チップ上のワイヤーボンディングを上記第２の絶縁性フィルム状接着層に取り込みながら接着し、その後、上記第２の絶縁性フィルム状接着層を固化させて、上記半導体装置を完成させれば、下側半導体チップ面上のワイヤーボンディング電極パターンに対し貼られているワイヤーを、上側半導体チップが傷つけることなく、半導体装置を組み立てることができる。
【００１４】
課題を解決する為、請求項３に係わる発明は、
前記第２の絶縁性フィルム状接着層は、低粘度熱可塑性の絶縁性フィルム状接着層と高粘度熱可塑性の絶縁性接着層とから構成されていることを特徴とする請求項１に記載の半導体装置を提供する。
上記の半導体装置によれば、上下の半導体チップを接着する際に、上記第２の絶縁性フィルム状接着層が、上側半導体チップの裏面（非回路形成面）に近い側は高粘度層、下側半導体チップの回路形成面に近い側が低粘度層に分かれているので、下側の半導体チップの回路形成面に貼られているボンディングワイヤーを絶縁性フィルム状接着層に内在させる場合に、高粘度層による上記ボンディングワイヤーの取り込み量を少なくでき、上記ボンディングワイヤーのワイヤーループの頂点が上側半導体チップの裏面（非回路形成面）に接触しないことを担保することができる。
【００１５】
課題を解決する為、請求項４に係わる発明は、
前記第２の絶縁性フィルム状接着層は、さらに、前記ボンディングワイヤーを内在させることができない程度の高硬度層を含むことを特徴とする請求項４に記載の半導体装置を提供する。
上記の半導体装置によれば、上下の半導体チップを接着する際に、絶縁性フィルム状接着層が、粘度の高い層と、上記ボンディングワイヤーを内在させることができない程度の高硬度層と、粘度の低い層に分かれているので、下側の半導体チップに貼られているボンディングワイヤーを前記第２の絶縁性フィルム状接着層に内在させる場合に、一定の深さ以上には取り込まないようにすることができ、上記ボンディングワイヤーのワイヤーループの頂点が上側半導体チップの裏面（非回路形成面）に接触しないことを担保することができる。
【００１６】
課題を解決する為、請求項５に係わる発明は、
前記第２の半導体チップの非回路形成面に請求項３及び請求項４に記載した第２の絶縁性接着層を形成する工程は、少なくとも表面に所定の回路が形成されたウエハーの裏面に前記低粘度可塑性を有する絶縁性フィルム状接着層を貼り付ける工程と、前記高硬度フィルム状絶縁層を貼り付ける工程と、前記高粘度可塑性を有する絶縁性フィルム状接着層を貼り付ける工程と、ダイシングすることにより前記第２の半導体チップに分離する工程とにより構成されていることを特徴とする請求項１に記載の半導体装置の製造方法を提供する。
【００１７】
上記の半導体装置の製造方法によれば、
上記第２の半導体チップの裏面に、複数の性質が異なる絶縁性フィルム状接着層を容易に形成できる。
以上より、図８に示した、従来例の半導体装置を組み立て工程に比較し、それ程工程の追加はなく、また、使用する部材の増加もないので、基本的には、図８に示した従来例と同程度の低い組み立てコストにより、上側に積層される半導体チップの形状及び大きさの制限を緩和した半導体装置及び半導体装置の製造方法を提供できる。
【００１８】
【発明の実施の形態】
以下、本発明の実施例を図面に基づいて説明する。
図１及び図２は請求項１の発明が提供する半導体装置の第１の実施例を示す。図１は断面図であり、上記半導体装置が、下側半導体チップ１と、上側半導体チップ２と、第１の絶縁性フィルム状接着層と、ボンディングワイヤー４と、半田ボール５と、封止樹脂６と、配線基板７と、第２の絶縁性フィルム状接着層１０とで構成されているところを示している。また、下側半導体チップの裏面と絶縁性基板の表面は第１の絶縁性フィルム状接着層を介して接着され、上側半導体チップの裏面は下側半導体チップの表面と１００μｍ〜２００μｍ程度の厚さを有する第２の絶縁性フィルム状半導体層を介して接着され、上側半導体チップ及び下側半導体チップの表面側回路形成面上のワイヤーボンディング電極パターンと配線基板表面のワイヤーボンディング電極パターンとはボンディングワイヤーにて接続されている。
【００１９】
図２は斜視図の例による立体構造図であり、半導体装置の構成要素は図１に示す要素と、完全に一致しており、各要素については、同一の番号を付している。次に図３は、請求項２の発明が提供する製造方法の実施例を示し、特に図１及び図２に示す請求項１に係わる半導体装置を請求項２に示す製造方法により製造する時の工程及び上側半導体チップに絶縁性フィルム状接着層を貼り付ける工程を示す。ここで、図３中の数字１〜１０は半導体装置の構成要素を示し、図１及び図２において示した、数字と構成要素の対応がそのまま使用されている。また、図１及び図２にない、数字１５はダイシングシートを示す。ダイシングシートとは、ウエハー状態の半導体をチップ状にダイシング装置により、個片化する際にウエハーの裏面に貼り付け、主に、ダイシング時の応力緩衝の為に使用されるものをいう。
【００２０】
以下、まず、図面左側の流れに沿って、半導体装置の製造工程について各工程毎に説明をする。
工程１は下側の半導体チップの裏面に絶縁性フィルム状接着層を作成し、配線基板と接着する工程を示す。
工程２は、下側半導体チップの表面側回路形成面上のワイヤーボンディング電極パターンと配線基板の表面上のワイヤーボンディング電極パターンをボンディングワイヤーで接続する工程を示す。
【００２１】
工程３は、上側半導体チップに絶縁性フィルム状接着層を、図面の右側に示す工程にて貼り付けし、そのまま、絶縁性フィルム接着層とともに１５０℃〜２００℃で１０秒程度熱処理を施し、絶縁性フィルム状接着層の粘度を　１００Ｐａ・ｓ程度から３０Ｐａ・ｓ程度へ軟化させるた後、徐々に上側半導体チップを下側半導体チップの表面に近づけ、下側半導体チップの表面にあるボンディングワイヤーを第２の絶縁性フィルム状接着層に内在させながら、上下の半導体チップを接着し、１５０℃〜２００℃で１時間〜２時間程度熱処理をして、第２の絶縁性フィルム状接着層を硬化させる工程を示す。
【００２２】
工程４は、上側半導体チップの表面に形成されているワイヤーボンディング電極パターンと配線基板状のワイヤーボンディング電極パターンをボンディングワイヤーで接続する工程を示す。
工程５は、全体を封止樹脂で覆い、硬化させて固める工程を示す。
上記の工程中、第２の絶縁性フィルム状接着層は、エポキシ樹脂とポリイミド樹脂を混合させて作成する。その粘度は、常温において、混合比率により変化し、エポキシ樹脂の混合比率が低い時は粘度は約１００Ｐａ・ｓ程度であり、混合比率が数十％程度では１００００Ｐａ・ｓ程度である。また、上記第２の絶縁性フィルム状接着層は、１５０℃〜２００℃で１〜２Ｓ程度の加熱処理後には、粘度は３０Ｐａ・Ｓ程度に下がるが、さらに、１５０℃〜２００℃で１時間から２時間の熱処理を行うと硬化する樹脂であることが望ましい。ここで、上記第２の絶縁性フィルム状接着層を構成するエポキシ樹脂は、例えば、化１及び化２に示す化学構造をもち、上記ポリイミド樹脂については、例えば、化３に示すような化学構造をもっており、表１に示すような諸元をもっているものが望ましい。
【００２３】
【化１】

Figure 2004072009
【００２４】
【化２】
Figure 2004072009
【００２５】
【化３】
Figure 2004072009
【００２６】
【表１】
Figure 2004072009
【００２７】
次に、図３の右側の流れに沿って、上側半導体チップに絶縁性フィルム状接着層を貼り付ける工程を説明する。
工程１は、上側半導体チップが個片化される前のウエハー状態であるときに、絶縁性フィルム状接着層をウエハー裏面に貼り付ける工程を示す。
工程２は、上記、絶縁性フィルム状接着層を貼り付けたウエハーをダイシングシート上に貼り付ける工程を示す。
【００２８】
工程３は、上側半導体チップをダイシング装置により、個片化する工程を示す。
以上、図８に示す従来の半導体装置を製造する工程に比較し、図３の左側の工程フロー中、工程２において、下側半導体チップの回路形成面上のボンディングワイヤー電極パターンと配線基板の表側配線面上のボンディングワイヤー電極パターンとをワイヤーボンディングにて接続した後、工程３で、ボンディングワイヤーを第２の絶縁性フィルム状接着層に内在させること及び図３の右側の工程フロー中、工程１で貼り付ける絶縁性フィルム状接着層の厚さが厚いことが相違点である。しかし、その相違点によるコストの上昇はそれ程でもなく、図８に示す半導体装置の製造コストとほぼ同程度のコストで、請求項２の発明が提供する製造方法によれば図３に示す半導体装置を製造することができる。
【００２９】
次に図４において、請求項３の発明が提供する半導体装置に係わる第２の実施例を示す。ここで、図４は、すべての半導体装置を表しているわけではなく、上側半導体チップ２と、下側半導体チップ１が第２の絶縁性フィルム状接着層１０を介して接着されているところを示している。また、ワイヤーが表示されているのは、第２の絶縁性フィルム状接着層１０が粘度の高い５０μｍ程度の厚さを有する第３の絶縁性フィルム状接着層１２と粘度の低い１００μｍ程度の第４の絶縁性フィルム状接着層１１とで構成されており、ワイヤーは粘度の低い絶縁性フィルム状接着層内に内在させている状態を示す為である。
【００３０】
第２の実施例によれば、ワイヤーは粘度の高い第３の絶縁性フィルム状接着層には、その粘度から考えて、それ程内在させることができず、上側半導体チップの裏面と接触しない利点がある。
さらに、図５において、請求項４の発明が提供する半導体装置に係わる第３の実施例を示す。ここで、図５は、すべての半導体装置を表しているわけではなく、上側半導体チップ２と、下側半導体チップ１が第２の絶縁性フィルム状接着層９を介して接着されているところを示している。また、ワイヤーが表示されているのは、第２の絶縁性フィルム状接着層が粘度の高い５０μｍ程度の厚さを有する第３の絶縁性フィルム状接着層１２と、一定の硬度を有する５０μｍ程度の厚さの第５の層１３と、粘度の低い１００μｍ程度の厚さを有する第４の絶縁性フィルム状接着層１１とで構成されており、ワイヤーは粘度の低い絶縁性フィルム状接着層内に内在させている状態を示す為である。
【００３１】
第３の実施例によれば、ワイヤーは第２の絶縁性フィルム状接着層１０が一定の硬度を有する第５の層１３を間に含んでいるので、一定の硬度を有する第５の層１３によって、上側半導体チップの裏面と接触しない利点がある。
さらに、図６において、請求項４の発明が提供する半導体装置に係わる第４の実施例を示す。ここで、図６は、すべての半導体装置を表しているわけではなく、上側半導体チップ２と、下側半導体チップ１が第２の絶縁性フィルム状接着層１０を介して接着されているところを示している。また、ワイヤーが表示されているのは、第２の絶縁性フィルム状接着層が粘度の高い第３の絶縁性フィルム状接着層１２であって層状態にフィラーを配置した部分１４が存在する層と、粘度の低い第４の絶縁性フィルム状接着層１１とで構成されており、ワイヤーは粘度の低い絶縁性フィルム状接着層内に内在させている状態を示す為である。
【００３２】
ここで、フィラーとは、ＳｉＯ２等の絶縁物を粒状にしたもので、その粒径はおよそ３０μｍ〜１００μｍ程度である粒状物質をいう。また、フィラーの層状態配置は、第３の絶縁性フィルム状接着層を製造する際に、予めフィラーを配置しておいた容器の中に第３の絶縁性フィルム状接着層の材料である接着剤を流しこむ方法または、上記容器の中に上記接着剤を流し入れた後、フィラーを加え沈殿するまで待つ方法により達成可能である。
【００３３】
第４の実施例によれば、ワイヤーは第２の絶縁性フィルム状接着層１０がフィラーを層状態に配置した部分を間に含んでいるので、フィラーを層状態に配置した部分がある程度の硬度を有する為、上側半導体チップの裏面と接触しない利点がある。
加えて、図７に、第２の実施例及び第３の実施例において必要な、上側半導体チップに第２の絶縁性フィルム状接着層を貼り付ける工程を示す。
【００３４】
まず、左側の工程フローに沿って、第２の実施例において、上側半導体チップに絶縁性フィルム状接着層を貼り付ける工程を以下に説明する。
工程１は、上側半導体チップ２が形成されているウエハーの裏面に、接着層作成工程を経た、粘度の高い絶縁性フィルム状接着層と粘度の低い絶縁性フィルム状接着層を貼り合わせて作成された絶縁性フィルム状接着層を、貼り付けることにより一体化させる工程を示す。
【００３５】
工程２は、工程１で一体化したものに、さらに、ダイシングシート１５を貼り付ける工程を示す。
工程３は、上側半導体チップが形成されているウエハーをダイシングして、絶縁性フィルム状接着層が裏面に形成されている半導体チップとして個片化する工程を示す。
【００３６】
次に、図７の右側に、第３の実施例において、上側半導体チップに絶縁性フィルム状接着層を貼り付ける工程を示す。以下、図７の右側に示す工程に沿って工程を説明する。
工程１は、上側半導体チップ２が形成されているウエハーの裏面に、接着層作成工程を経た、粘度の高い絶縁性フィルム状接着層と、一定の硬度を有する層と、粘度の低い絶縁性フィルム状接着層を、順次、貼り合わせて作成された絶縁性フィルム状接着層を、貼り付けることにより一体化させる工程を示す。
【００３７】
工程２は、工程１で一体化したものに、さらに、ダイシングシート１５を貼り付ける工程を示す。
工程３は、上側半導体チップが形成されているウエハーをダイシングして、絶縁性フィルム状接着層が裏面に形成されている半導体チップとして個片化する工程を示す。
【００３８】
上記の図７に示す工程から構成される、製造方法によれば、容易に、上側半導体チップの裏面に絶縁性フィルム状接着層１０を構成する層を貼り付けることができる。ここで、絶縁性フィルム状接着層１１、１２はエポキシ樹脂及びポリイミド樹脂を混合して制作し、上記混合比率を変えて粘度を調節することが望ましい。また、一定の硬度を有する層１３はポリイミド樹脂のみで作成することが望ましく、それにより、一定の硬度だけでなく、熱耐性をもつことができる。
【００３９】
以上、実施例１〜実施例４に示す半導体装置及びそれらを製造する方法によれば、複数の半導体チップを積層的に、１のスタックドパッケージに低コストで搭載でき、半導体装置を実装基板上に実装うえで、高密度化が達成できる。
（付記１）　　少なくとも、第１の半導体チップと、第２の半導体チップとが、表面側配線層が中間絶縁層を貫通して形成された貫通孔を通して裏面側配線層と電気的に接続された実装用外部端子を有する配線基板に搭載され、封止用樹脂にて封止されている半導体装置であって、前記配線基板の表面と、前記第１の半導体チップの非回路形成面とが第１の絶縁性接着層を介して接着され、前記第１の半導体チップのワイヤーボンディング電極パターンを有する回路形成面と前記第２の半導体チップの非回路形成面とが前記第１の半導体チップのワイヤボンディング電極パターンの領域の少なくとも一部を含むように、第２の絶縁性接着層を介して接着され、前記配線基板の前記表面側配線層に形成されたワイヤーボンディング電極パターンと、前記第１の半導体チップ及び前記第２の半導体チップのワイヤーボンディング電極パターンを有する回路形成面のワイヤーボンディング電極パターンとが、ボンディングワイヤーで接続され、かつ、前記第２の絶縁性接着層は少なくとも前記第１の半導体チップに接続形成されたボンディングワイヤーのワイヤーループ最頂点高さより厚く形成されていることを特徴とする半導体装置。
【００４０】
（付記２）　前記第２の絶縁性接着層の全部又は一部に、前記ボンディングワイヤーを内在させることができる程度の粘度を与える工程と、前記ボンディングワイヤーを前記第２の絶縁性接着層に内在させると同時に前記第２の半導体チップを前記第１の半導体チップの回路形成面上に搭載する工程と、前記第２の絶縁性フィルム状接着層を固まらせる工程を少なくとも含むことを特徴とする請求項１に記載の半導体装置の製造方法。
【００４１】
（付記３）　前記第２の半導体チップの裏面に第２の絶縁性接着層形成する工程は、少なくとも、表面に所定の回路が形成されたウエハーの裏面に絶縁性フィルム状接着層を貼り付ける工程と、ダイシングすることにより前記第２の半導体チップに分離する工程とにより構成されていることを特徴とする付記１に記載の半導体装置の製造方法。
【００４２】
（付記４）　前記第２の絶縁性接着層は、低粘度熱可塑性を有する絶縁性フィルム状接着層と高粘度熱可塑性を有する絶縁性フィルム上接着層とから構成されていることを特徴とする付記１に記載の半導体装置。
（付記５）　前記第２の絶縁性接着層は、さらに、前記ワイヤーを内在させることができない程度の高硬度層を含むことを特徴とする付記４に記載の半導体装置。
【００４３】
（付記６）　前記高硬度層はポリイミド樹脂で構成されていることを特徴とする付記５に記載の半導体装置。
（付記７）　前記高硬度層は前記第２の絶縁性接着層内にフィラーを含有させ、層状態に配置させることにより形成したことを特徴とした付記５に記載の半導体装置。
【００４４】
（付記８）　前記第２の半導体チップの裏面に付記４及び付記５に記載した第２の絶縁性フィルム状接着層を形成する工程は、少なくとも表面に所定の回路が形成されたウエハーの裏面に前記高粘度熱可塑性を有する絶縁性フィルム状接着層を貼り付ける工程と、前記高硬度層を貼り付ける工程と、前記低粘度熱可塑性を有する絶縁性フィルム状接着層を貼り付ける工程と、ダイシングすることにより前記第２の半導体チップに分離する工程とにより構成されていることを特徴とする付記１に記載の半導体装置の製造方法。
【００４５】
【発明の効果】
以上の詳細説明したように、本発明の半導体装置及びその製造方法によれば、工程の増加なく、それ程部材費用の追加がない為、低コストなスタックドパッケージを実現でき、低コストな半導体製造装置及びその製造方法を提供することができる。
【図面の簡単な説明】
【図１】実施例１
【図２】実施例１の斜視図の例による立体構造図
【図３】実施例１に係わる半導体装置の製造工程
【図４】実施例２
【図５】実施例３
【図６】実施例４
【図７】実施例２及び実施例３に係わる半導体装置の製造工程
【図８】従来例１
【図９】従来例２
【図１０】従来例３
【符号の説明】
１　下側半導体チップ
２　上側半導体チップ
３　第１の絶縁性フィルム状接着層
４　ワイヤー
５　半田ボール
６　封止樹脂
７　配線基板
８　金属バンプ
９　スペーサー
１０　第２の絶縁性フィルム状接着層
１１　粘度の低い第４の絶縁性フィルム状接着層
１２　粘度の高い第３の絶縁性フィルム状接着層
１３　一定の硬度を有する第５の層
１４　フィラーを層状に配置した部分
１５　ダイシングシート[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device (hereinafter, referred to as a “stacked package”) having a package structure in which a plurality of semiconductor chips are stacked and mounted to increase a mounting density, and a manufacturing method thereof. A front-side wiring layer mounted on a wiring board having mounting external terminals electrically connected to the back-side wiring layer through a through-hole formed through the intermediate insulating layer; The present invention relates to a semiconductor device wherein a wire bonding electrode pattern formed on a surface is connected by wire bonding and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, with the miniaturization of portable devices, personal computers, and the like, higher density is required when semiconductor devices are mounted on mounting substrates. However, low cost semiconductor devices are also required in the above-mentioned devices, and low-cost stacked package technology is attracting attention.
[0003]
FIG. 8 shows an example of a semiconductor device to which a low-cost stacked package technology is applied. Here, the semiconductor device of FIG. 8 includes a lower semiconductor chip 1, an upper semiconductor chip 2, a wiring substrate 7 having external terminals for mounting (ie, solder balls 5) on the back surface, bonding wires 4, and a sealing resin 6. And an insulating film-like adhesive layer 3. The back surface (non-circuit forming surface) of the upper semiconductor chip has a thickness of about 20 to 50 μm on the circuit forming surface of the lower semiconductor chip 1. The bonding is performed via the insulating film-like adhesive layer 3, and the surface-side wiring forming surface of the wiring board 7 and the back surface (non-circuit forming surface) of the lower semiconductor chip 1 are bonded via the insulating film-like bonding layer 3. A wire bonding electrode pattern on the circuit forming surface of the lower semiconductor chip, a wire bonding electrode pattern on the upper semiconductor chip, and a wire bonding electrode pattern on the surface wiring forming surface of the wiring substrate. After connecting the electrode pattern in the bonding wires 4 are produced by sealing with the sealing resin 6.
[0004]
However, as shown in FIG. 8, the wire bonding electrode pattern on the circuit forming surface of each semiconductor chip mounted and stacked in the stacked package is connected to the wire bonding electrode pattern on the wiring board having external terminals for mounting. When wire bonding is used as a means for mounting, all the semiconductor chips to be stacked must be mounted face-up on the wiring board, and the wire bonding electrode pattern on the lower semiconductor chip surface must be mounted at the time of wire bonding. In order to prevent the upper semiconductor chip from hindering, the size and shape of the upper semiconductor chip are limited.
[0005]
Therefore, in order to alleviate the above-mentioned limitation, various structures and methods for manufacturing semiconductor chips have been proposed and realized.
For example, the semiconductor device shown in FIG. 9 is also an example of a stacked package. Here, FIG. 9 shows a cross-sectional structure of the semiconductor device. The semiconductor device is a wiring board having a lower semiconductor chip 1, an upper semiconductor chip 2, and mounting external terminals (ie, solder balls 5) on the back surface. 7, an insulating film-like adhesive layer 3, metal bumps 8, bonding wires 4, and a sealing resin 6. The upper and lower semiconductor chips (non-circuit forming surfaces) are insulated from each other. A set of semiconductor chips adhered via the film-like adhesive layer 3 is stacked on the circuit forming surface of the lower semiconductor chip and the upper wiring surface of the wiring board via metal bumps 8 (hereinafter referred to as “flip chip structure”). ), The space between the lower semiconductor chip and the wiring board is filled with an underfill material, and the wire bonding electrode pattern of the upper semiconductor chip 2 and the wiring board 7 in the face-up state are filled. After ear bonding electrode patterns connected by the bonding wires 4, by sealing with the sealing resin 6, it is manufactured.
[0006]
By the way, in the above description, the underfill material refers to a material which has a thermosetting property by adding a filler (referred to as a particulate material having a particle size of about 20 to 100 μm made of SiO2 or the like) to an epoxy resin or the like. .
Further, the semiconductor device shown in FIG. 10 is also given as an example. Here, FIG. 10 shows a cross-sectional structure of the semiconductor device. The semiconductor device has a lower semiconductor chip 1, an upper semiconductor chip 2, and a wiring board 7 having external terminals for mounting (that is, solder balls 5). , A spacer 9, a bonding wire 4, a sealing resin 6 and an insulating film-like adhesive layer 3, and a circuit is formed on the lower semiconductor chip 1 so as to leave a gap for wire bonding. A spacer 9 having a height of 200 μm to 300 μm is mounted on the surface, and the back surface (non-circuit forming surface) of the upper semiconductor chip 2 is mounted on the circuit forming surface of the lower semiconductor chip via the spacer 9. The back surface (non-circuit formation surface) of the side semiconductor chip 1 and the upper wiring surface of the wiring board 7 are stacked via an insulating film-like adhesive layer 3 (hereinafter referred to as a “spacer structure”), and the lower semiconductor chip After connecting the wire bonding electrode pattern on the circuit forming surface of the chip and the wire bonding electrode pattern on the circuit forming surface of the upper semiconductor chip to the wire bonding electrode pattern on the upper wiring surface of the wiring board with bonding wires 4, It is manufactured by sealing with a sealing resin 6.
[0007]
[Problems to be solved by the invention]
In the case of the semiconductor device having the flip chip structure shown in FIG. 9, the upper semiconductor chip and the lower semiconductor chip are connected to each other on the back surface, and the wire bonding electrode pattern and the wiring board in the circuit formation surface of the lower semiconductor chip are provided. Is connected to the wire bonding electrode pattern on the upper wiring surface by metal bumps, so that the connection between the wire bonding electrode pattern on the lower semiconductor chip and the wire bonding electrode pattern on the wiring board depends on the shape and size of the upper semiconductor chip. Restrictions have been relaxed. However, a step of forming a metal bump on the wire bonding electrode pattern of the lower semiconductor chip and the wiring board, a step of connecting the metal bump, and a step of injecting an underfill material are increased, so that an increase in cost is inevitable. In addition, the bonding technique using metal bumps is less mature than the bonding technique using wire bonding, so that an increase in the number of bonding points using metal bumps causes a decrease in yield.
[0008]
On the other hand, even in the case of the semiconductor device having the spacer structure of FIG. 10, the wire bonding electrode pattern on the circuit forming surface of the upper semiconductor chip and the wire bonding electrode pattern on the upper wiring surface of the wiring board are connected by bonding wires. Since the spacer is interposed between the upper semiconductor chip and the lower semiconductor chip, bonding can be performed using the gap, so that restrictions on the shape and size of the upper semiconductor chip are relaxed. However, an additional step of mounting the spacer and a member used for the spacer are added, so that an increase in cost cannot be avoided.
[0009]
In view of the above problems, the present invention provides a semiconductor manufacturing apparatus and a semiconductor manufacturing apparatus that realizes a stacked package in which the number of steps and members is not so large, the cost is low, and the restrictions on the shape and size of the upper semiconductor chip are relaxed. It is an object of the present invention to provide a manufacturing method thereof.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the present invention according to claim 1, wherein at least a first semiconductor chip and a second semiconductor chip have a through-hole in which a surface-side wiring layer is formed through an intermediate insulating layer. A semiconductor device mounted on a wiring board having mounting external terminals electrically connected to the backside wiring layer through the holes and sealed with a sealing resin,
A circuit forming surface having a wire bonding electrode pattern of the first semiconductor chip, wherein a surface of the wiring substrate and a non-circuit forming surface of the first semiconductor chip are bonded via a first insulating adhesive layer; The second semiconductor chip is bonded via a second insulating adhesive layer so as to include at least a part of a region of a wire bonding electrode pattern of the first semiconductor chip; A wire bonding electrode pattern formed on the front surface side wiring layer of the substrate and a wire bonding electrode pattern on a circuit forming surface having the wire bonding electrode patterns of the first semiconductor chip and the second semiconductor chip are formed by bonding wires. And the second insulating adhesive layer is formed to be connected to at least the first semiconductor chip. To provide a semiconductor device which is characterized in that it is thicker than the wire loop top apex height of the bonding wire.
[0011]
According to the above invention, the thickness of the insulating film-like adhesive layer between the upper and lower semiconductor chips is increased, so that the bonding wire attached to the surface of the lower semiconductor chip is not damaged. A gap can be made. Therefore, there is no need to limit the shape and size of the upper semiconductor chip with respect to the shape and size of the lower semiconductor chip.
[0012]
In order to solve the problem, the invention according to claim 2 is
Giving a viscosity to the whole or a part of the second insulating film-like adhesive layer to such an extent that the bonding wire can be included therein; and providing the bonding wire in the second insulating film-like adhesive layer. At the same time, mounting the second semiconductor chip on the circuit forming surface of the first semiconductor chip, and hardening the second insulating film-like adhesive layer. An apparatus manufacturing method is provided.
[0013]
According to the above invention, first, the back surface (non-circuit formation surface) of the lower semiconductor chip is bonded to the upper wiring surface of the wiring board, and then the bonding wire electrode pattern and the wiring on the circuit formation surface of the lower semiconductor chip are bonded. When the bonding wire electrode pattern on the upper wiring surface of the substrate is connected with the bonding wire and the upper and lower semiconductor chips are bonded via the second insulating film-like bonding layer, the bonding wire can be contained therein. The viscosity of the second adhesive layer on the insulating film is lowered in advance, and the wire bonding on the lower semiconductor chip is bonded to the second insulating film-like adhesive layer while being taken into the second insulating film-like adhesive layer. When the semiconductor device is completed by solidifying the adhesive film layer, the wire bonding electrode pattern on the lower semiconductor chip surface The wire is affixed against, without the upper semiconductor chip is hurt, it is possible to assemble the semiconductor device.
[0014]
In order to solve the problem, the invention according to claim 3 is:
The said 2nd insulating film adhesive layer is comprised from a low viscosity thermoplastic insulating film adhesive layer and a high viscosity thermoplastic insulating adhesive layer, The Claims characterized by the above-mentioned. Provided is a semiconductor device.
According to the above-described semiconductor device, when the upper and lower semiconductor chips are bonded, the second insulating film-like adhesive layer has a high-viscosity layer on the side close to the back surface (non-circuit formation surface) of the upper semiconductor chip, and Since the side near the circuit forming surface of the side semiconductor chip is divided into a low viscosity layer, when the bonding wire attached to the circuit forming surface of the lower semiconductor chip is embedded in the insulating film-like adhesive layer, high viscosity The amount of the bonding wire taken in by the layer can be reduced, and it can be ensured that the apex of the wire loop of the bonding wire does not contact the back surface (non-circuit formation surface) of the upper semiconductor chip.
[0015]
In order to solve the problem, the invention according to claim 4 is
5. The semiconductor device according to claim 4, wherein the second insulating film-like adhesive layer further includes a high-hardness layer that does not allow the bonding wire to be included therein.
According to the above-described semiconductor device, when bonding the upper and lower semiconductor chips, the insulating film-like adhesive layer has a high viscosity layer, a high hardness layer in which the bonding wire cannot be embedded, and a high viscosity layer. Since it is divided into lower layers, when the bonding wire attached to the lower semiconductor chip is included in the second insulating film-like adhesive layer, it should not be taken in beyond a certain depth. Thus, it can be ensured that the apex of the wire loop of the bonding wire does not contact the back surface (non-circuit formation surface) of the upper semiconductor chip.
[0016]
In order to solve the problem, the invention according to claim 5 is:
The step of forming the second insulating adhesive layer according to claim 3 or claim 4 on the non-circuit forming surface of the second semiconductor chip comprises the step of: A step of attaching an insulating film-like adhesive layer having low viscosity plasticity, a step of attaching the high-hardness film-like insulating layer, a step of attaching the insulating film-like adhesive layer having high viscosity plasticity, and dicing. 2. A method of manufacturing a semiconductor device according to claim 1, further comprising the step of: separating the semiconductor device into the second semiconductor chips.
[0017]
According to the method of manufacturing a semiconductor device described above,
An insulating film-like adhesive layer having a plurality of different properties can be easily formed on the back surface of the second semiconductor chip.
As described above, the conventional semiconductor device shown in FIG. 8 is compared with the assembling process, so that there is not much additional process and the number of members used is not increased. A semiconductor device and a method of manufacturing a semiconductor device in which the restrictions on the shape and size of the semiconductor chip stacked on the upper side are relaxed at the same low assembly cost as in the example.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 and 2 show a first embodiment of a semiconductor device provided by the present invention. FIG. 1 is a cross-sectional view, in which the semiconductor device includes a lower semiconductor chip 1, an upper semiconductor chip 2, a first insulating film-like adhesive layer, a bonding wire 4, a solder ball 5, and a sealing resin. 6, a wiring board 7, and a second insulating film-like adhesive layer 10. Further, the back surface of the lower semiconductor chip and the front surface of the insulating substrate are bonded via a first insulating film-like adhesive layer, and the back surface of the upper semiconductor chip is approximately 100 μm to 200 μm thick with the front surface of the lower semiconductor chip. The wire bonding electrode pattern on the surface-side circuit forming surface of the upper semiconductor chip and the lower semiconductor chip and the wire bonding electrode pattern on the surface of the wiring board are bonded via a second insulating film-like semiconductor layer having a bonding wire. Connected at
[0019]
FIG. 2 is a three-dimensional structure diagram according to an example of a perspective view. The components of the semiconductor device completely correspond to the components shown in FIG. 1, and the same numbers are assigned to the components. Next, FIG. 3 shows an embodiment of the manufacturing method provided by the invention of claim 2, particularly when the semiconductor device according to claim 1 shown in FIGS. 1 and 2 is manufactured by the manufacturing method according to claim 2. 2 shows a process and a process of attaching an insulating film-like adhesive layer to the upper semiconductor chip. Here, numerals 1 to 10 in FIG. 3 indicate the components of the semiconductor device, and the correspondence between the numerals and the components shown in FIGS. 1 and 2 is used as it is. Numeral 15 not shown in FIGS. 1 and 2 indicates a dicing sheet. The dicing sheet refers to a sheet that is attached to the back surface of the wafer when the semiconductor in a wafer state is cut into individual chips by a dicing apparatus and is mainly used for buffering stress during dicing.
[0020]
Hereinafter, first, the manufacturing process of the semiconductor device will be described for each process along the flow on the left side of the drawing.
Step 1 shows a step of forming an insulating film-like adhesive layer on the back surface of the lower semiconductor chip and bonding the same to a wiring board.
Step 2 shows a step of connecting the wire bonding electrode pattern on the front-side circuit forming surface of the lower semiconductor chip and the wire bonding electrode pattern on the surface of the wiring board with bonding wires.
[0021]
In step 3, an insulating film-like adhesive layer is attached to the upper semiconductor chip in the step shown on the right side of the drawing, and is subjected to a heat treatment at 150 ° C. to 200 ° C. for about 10 seconds together with the insulating film adhesive layer. After softening the viscosity of the conductive film adhesive layer from about 100 Pa · s to about 30 Pa · s, the upper semiconductor chip is gradually brought closer to the surface of the lower semiconductor chip, and the bonding wire on the surface of the lower semiconductor chip is removed. The upper and lower semiconductor chips are adhered to each other while being included in the second insulating film-like adhesive layer, and heat-treated at 150 ° C. to 200 ° C. for about 1 to 2 hours to cure the second insulating film-like adhesive layer. The steps will be described.
[0022]
Step 4 shows a step of connecting the wire bonding electrode pattern formed on the surface of the upper semiconductor chip and the wiring board-shaped wire bonding electrode pattern with bonding wires.
Step 5 is a step of covering the whole with a sealing resin, curing and solidifying.
In the above process, the second insulating film-like adhesive layer is formed by mixing an epoxy resin and a polyimide resin. The viscosity changes at room temperature depending on the mixing ratio. When the mixing ratio of the epoxy resin is low, the viscosity is about 100 Pa · s, and when the mixing ratio is about several tens%, it is about 10,000 Pa · s. In addition, the second insulating film-like adhesive layer has a viscosity of about 30 Pa · S after a heat treatment of about 1 to 2 S at 150 ° C. to 200 ° C., and further has a viscosity of 1 hour at 150 ° C. to 200 ° C. It is preferable that the resin is a resin that cures when heat treatment is performed for 2 hours. Here, the epoxy resin constituting the second insulating film-like adhesive layer has, for example, the chemical structure shown in Chemical formula 1 and Chemical formula 2, and the polyimide resin has the chemical structure shown in Chemical formula 3, for example. It is desirable to have the specifications as shown in Table 1.
[0023]
Embedded image
Figure 2004072009
[0024]
Embedded image
Figure 2004072009
[0025]
Embedded image
Figure 2004072009
[0026]
[Table 1]
Figure 2004072009
[0027]
Next, the step of attaching the insulating film-like adhesive layer to the upper semiconductor chip will be described along the flow on the right side of FIG.
Step 1 shows a step of attaching an insulating film-like adhesive layer to the back surface of the wafer when the upper semiconductor chip is in a wafer state before being singulated.
Step 2 shows a step of attaching the wafer to which the insulating film-like adhesive layer has been attached, on a dicing sheet.
[0028]
Step 3 shows a step of singulating the upper semiconductor chip by using a dicing apparatus.
As compared with the process of manufacturing the conventional semiconductor device shown in FIG. 8, the bonding wire electrode pattern on the circuit formation surface of the lower semiconductor chip and the front side of the wiring substrate are found in Step 2 in the process flow on the left side of FIG. After connecting the bonding wire electrode pattern on the wiring surface to the bonding wire electrode pattern by wire bonding, in step 3, the bonding wire is made to be present in the second insulating film-like adhesive layer. The difference is that the thickness of the insulating film-like adhesive layer to be stuck is large. However, the increase in cost due to the difference is not so large, and is substantially the same as the manufacturing cost of the semiconductor device shown in FIG. 8, and according to the manufacturing method provided by the invention of claim 2, the semiconductor device shown in FIG. Can be manufactured.
[0029]
Next, FIG. 4 shows a second embodiment according to the semiconductor device provided by the third aspect of the present invention. Here, FIG. 4 does not show all the semiconductor devices, and shows a case where the upper semiconductor chip 2 and the lower semiconductor chip 1 are bonded via the second insulating film-like bonding layer 10. Is shown. Also, the wires are indicated by the fact that the second insulating film-like adhesive layer 10 has a high viscosity of about 50 μm and a third insulating film-like adhesive layer 12 of low viscosity of about 100 μm. This is for the purpose of showing a state in which the wire is included in the low-viscosity insulating film-like adhesive layer.
[0030]
According to the second embodiment, there is an advantage that the wire cannot be included in the third insulating film-like adhesive layer having a high viscosity because of its viscosity, and the wire does not contact the back surface of the upper semiconductor chip. is there.
FIG. 5 shows a third embodiment of the semiconductor device provided by the invention of claim 4. Here, FIG. 5 does not show all the semiconductor devices, and shows a case where the upper semiconductor chip 2 and the lower semiconductor chip 1 are bonded via the second insulating film-like bonding layer 9. Is shown. In addition, the wires are indicated by a third insulating film-like adhesive layer 12 having a high viscosity of about 50 μm and a second insulating film-like adhesive layer of about 50 μm having a certain hardness. And a fourth insulating film-like adhesive layer 11 having a low viscosity of about 100 μm, and the wire is formed in the low-viscosity insulating film-like adhesive layer. This is to show the state of being included in the subroutine.
[0031]
According to the third embodiment, the wire has a fifth layer 13 having a certain hardness because the second insulating film-like adhesive layer 10 includes a fifth layer 13 having a certain hardness therebetween. Therefore, there is an advantage that it does not come into contact with the back surface of the upper semiconductor chip.
FIG. 6 shows a fourth embodiment according to the semiconductor device provided by the invention of claim 4. Here, FIG. 6 does not show all the semiconductor devices, but shows a state where the upper semiconductor chip 2 and the lower semiconductor chip 1 are bonded via the second insulating film-like bonding layer 10. Is shown. Also, the wires are indicated by a layer in which the second insulating film-like adhesive layer is a third insulating film-like adhesive layer 12 having a high viscosity and a portion 14 in which a filler is arranged in a layer state is present. And a fourth insulating film-like adhesive layer 11 having a low viscosity, and this is for showing a state in which the wire is provided inside the insulating film-like adhesive layer having a low viscosity.
[0032]
Here, the filler refers to a granular material obtained by granulating an insulating material such as SiO2 and having a particle size of about 30 μm to 100 μm. When the third insulating film-like adhesive layer is manufactured, the filler is placed in a container in which the filler is arranged in advance in the third insulating film-like adhesive layer. It can be achieved by a method of pouring an agent or a method of pouring the adhesive into the container, adding a filler, and then waiting until precipitation occurs.
[0033]
According to the fourth embodiment, since the wire includes a portion where the second insulating film-like adhesive layer 10 has the filler arranged in a layer state, the wire having the filler arranged in the layer state has a certain hardness. Has the advantage of not contacting the back surface of the upper semiconductor chip.
In addition, FIG. 7 shows a step of attaching a second insulating film-like adhesive layer to the upper semiconductor chip, which is required in the second and third embodiments.
[0034]
First, the process of attaching an insulating film-like adhesive layer to an upper semiconductor chip in the second embodiment will be described below along the process flow on the left.
Step 1 is formed by laminating a high-viscosity insulating film-like adhesive layer and a low-viscosity insulating film-like adhesive layer, which have undergone an adhesive layer forming step, on the back surface of the wafer on which the upper semiconductor chip 2 is formed. The step of integrating the insulating film-like adhesive layer by bonding is shown.
[0035]
Step 2 shows a step of further attaching a dicing sheet 15 to the one integrated in step 1.
Step 3 is a step of dicing the wafer on which the upper semiconductor chip is formed to singulate the semiconductor chip having the insulating film adhesive layer formed on the back surface.
[0036]
Next, on the right side of FIG. 7, a step of attaching an insulating film-like adhesive layer to the upper semiconductor chip in the third embodiment is shown. Hereinafter, the steps will be described along the steps shown on the right side of FIG.
Step 1 includes a step of forming an adhesive layer having a high viscosity, an insulating film-like adhesive layer having a high viscosity, a layer having a certain hardness, and a low-viscosity insulating film on the back surface of the wafer on which the upper semiconductor chip 2 is formed. A step of integrating an insulating film-like adhesive layer formed by sequentially bonding the adhesive layers in a manner of bonding is shown.
[0037]
Step 2 shows a step of further attaching a dicing sheet 15 to the one integrated in step 1.
Step 3 is a step of dicing the wafer on which the upper semiconductor chip is formed to singulate the semiconductor chip having the insulating film adhesive layer formed on the back surface.
[0038]
According to the manufacturing method including the steps shown in FIG. 7, the layer constituting the insulating film-like adhesive layer 10 can be easily attached to the back surface of the upper semiconductor chip. Here, it is desirable that the insulating film-like adhesive layers 11 and 12 are produced by mixing epoxy resin and polyimide resin, and that the viscosity is adjusted by changing the mixing ratio. Further, it is desirable that the layer 13 having a certain hardness is made of only a polyimide resin, whereby not only a certain hardness but also heat resistance can be obtained.
[0039]
As described above, according to the semiconductor devices according to the first to fourth embodiments and the method of manufacturing the same, a plurality of semiconductor chips can be stacked and mounted on one stacked package at low cost, and the semiconductor device can be mounted on a mounting substrate. In mounting, high density can be achieved.
(Supplementary Note 1) At least the first semiconductor chip and the second semiconductor chip are electrically connected to the backside wiring layer through through holes formed by the frontside wiring layer penetrating the intermediate insulating layer. A semiconductor device mounted on a wiring board having external terminals for mounting and sealed with a sealing resin, wherein a surface of the wiring board and a non-circuit forming surface of the first semiconductor chip are second A circuit forming surface of the first semiconductor chip having a wire bonding electrode pattern and a non-circuit forming surface of the second semiconductor chip are bonded to each other through the insulating adhesive layer of the first semiconductor chip; A wire bonding electrode pattern formed on the front-side wiring layer of the wiring board, the bonding being performed via a second insulating adhesive layer so as to include at least a part of a region of the bonding electrode pattern; The first semiconductor chip and the wire bonding electrode pattern on the circuit forming surface having the wire bonding electrode pattern of the second semiconductor chip are connected by bonding wires, and the second insulating adhesive layer is at least A semiconductor device characterized in that the bonding wire is formed thicker than the height of the apex of the wire loop of the bonding wire connected to the first semiconductor chip.
[0040]
(Supplementary Note 2) A step of giving a viscosity to the whole or a part of the second insulating adhesive layer such that the bonding wire can be included therein, and a step of providing the bonding wire in the second insulating adhesive layer. And simultaneously mounting the second semiconductor chip on the circuit forming surface of the first semiconductor chip and hardening the second insulating film-like adhesive layer. Item 2. A method for manufacturing a semiconductor device according to item 1.
[0041]
(Supplementary Note 3) The step of forming the second insulating adhesive layer on the back surface of the second semiconductor chip includes the step of attaching the insulating film adhesive layer to at least the back surface of a wafer having a predetermined circuit formed on the front surface. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising: dicing the semiconductor chip into the second semiconductor chips by dicing.
[0042]
(Supplementary Note 4) The second insulating adhesive layer includes an insulating film-like adhesive layer having low-viscosity thermoplastic and an adhesive-on-insulating-film adhesive layer having high-viscosity thermoplastic. The semiconductor device according to supplementary note 1.
(Supplementary Note 5) The semiconductor device according to Supplementary Note 4, wherein the second insulating adhesive layer further includes a high-hardness layer that does not allow the wires to be included therein.
[0043]
(Supplementary Note 6) The semiconductor device according to Supplementary Note 5, wherein the high hardness layer is made of a polyimide resin.
(Supplementary Note 7) The semiconductor device according to Supplementary Note 5, wherein the high hardness layer is formed by including a filler in the second insulating adhesive layer and arranging the filler in a layer state.
[0044]
(Supplementary Note 8) The step of forming the second insulating film-like adhesive layer described in Supplementary Notes 4 and 5 on the back surface of the second semiconductor chip includes the step of forming the second insulating film-like adhesive layer on at least the back surface of the wafer on which a predetermined circuit is formed. A step of attaching the insulating film-like adhesive layer having high viscosity thermoplasticity, a step of attaching the high hardness layer, a step of attaching the insulating film-like adhesive layer having low viscosity thermoplasticity, and dicing. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of: separating the semiconductor device into the second semiconductor chip.
[0045]
【The invention's effect】
As described above in detail, according to the semiconductor device and the method of manufacturing the same of the present invention, a low-cost stacked package can be realized because the number of steps is not increased and the member cost is not significantly added. An apparatus and a method for manufacturing the same can be provided.
[Brief description of the drawings]
FIG. 1 Example 1
FIG. 2 is a three-dimensional structure diagram according to an example of a perspective view of the first embodiment.
FIG. 3 is a manufacturing process of the semiconductor device according to the first embodiment;
FIG. 4 is a second embodiment.
FIG. 5 is a third embodiment.
FIG. 6 is a fourth embodiment.
FIG. 7 is a manufacturing process of the semiconductor device according to the second and third embodiments.
FIG. 8: Conventional example 1
FIG. 9 is a conventional example 2.
FIG. 10 is a conventional example 3.
[Explanation of symbols]
1 Lower semiconductor chip
2 Upper semiconductor chip
3 First insulating film adhesive layer
4 wires
5 Solder balls
6 sealing resin
7 Wiring board
8 Metal bump
9 Spacer
10 Second insulating film-like adhesive layer
11. Low-viscosity fourth insulating film-like adhesive layer
12. High viscosity third insulating film adhesive layer
13 Fifth layer having constant hardness
14 Part where fillers are arranged in layers
15 Dicing sheet

Claims (5)

少なくとも、第１の半導体チップと、第２の半導体チップとが、表面側配線層が中間絶縁層を貫通して形成された貫通孔を通して裏面側配線層と電気的に接続された実装用外部端子を有する配線基板に搭載され、封止用樹脂にて封止されている半導体装置であって、
前記配線基板の表面と、前記第１の半導体チップの非回路形成面とが第１の絶縁性接着層を介して接着され、
前記第１の半導体チップのワイヤーボンディング電極パターンを有する回路形成面と前記第２の半導体チップの非回路形成面とが前記第１の半導体チップのワイヤボンディング電極パターンの領域の少なくとも一部を含むように、第２の絶縁性接着層を介して接着され、
前記配線基板の前記表面側配線層に形成されたワイヤーボンディング電極パターンと、前記第１の半導体チップ及び前記第２の半導体チップのワイヤーボンディング電極パターンを有する回路形成面のワイヤーボンディング電極パターンとが、ボンディングワイヤーで接続され、
かつ、前記第２の絶縁性接着層は少なくとも前記第１の半導体チップに接続形成されたボンディングワイヤーのワイヤーループ最頂点高さより厚く形成されていることを特徴とする半導体装置。At least a mounting external terminal in which the first semiconductor chip and the second semiconductor chip are electrically connected to the backside wiring layer through a through hole formed by penetrating the intermediate insulating layer through the frontside wiring layer. A semiconductor device mounted on a wiring board having
A surface of the wiring substrate and a non-circuit-forming surface of the first semiconductor chip are bonded via a first insulating adhesive layer;
A circuit forming surface of the first semiconductor chip having a wire bonding electrode pattern and a non-circuit forming surface of the second semiconductor chip include at least a part of a region of the wire bonding electrode pattern of the first semiconductor chip. Is bonded through a second insulating adhesive layer,
A wire bonding electrode pattern formed on the front-side wiring layer of the wiring substrate, and a wire bonding electrode pattern on a circuit forming surface having the wire bonding electrode patterns of the first semiconductor chip and the second semiconductor chip, Connected by bonding wires,
Further, the semiconductor device is characterized in that the second insulating adhesive layer is formed to be thicker than at least the maximum height of a wire loop of a bonding wire connected to the first semiconductor chip. 前記第２の絶縁性接着層の全部又は一部に、前記ボンディングワイヤーを内在させることができる程度の粘度を与える工程と、
前記ボンディングワイヤーを前記第２の絶縁性接着層に内在させるとともに前記第２の半導体チップを前記第１の半導体チップの回路形成面上に搭載する工程と、
前記第２の絶縁性接着層を固化する工程を少なくとも含むことを特徴とする請求項１に記載の半導体装置の製造方法。A step of giving the whole or a part of the second insulating adhesive layer a viscosity that allows the bonding wire to be contained therein;
Placing the bonding wire inside the second insulating adhesive layer and mounting the second semiconductor chip on a circuit forming surface of the first semiconductor chip;
2. The method according to claim 1, further comprising a step of solidifying the second insulating adhesive layer. 前記第２の絶縁性接着層は、低粘度熱可塑性を有する絶縁性フィルム状接着層と高粘度可塑性を有する絶縁性フィルム状接着層とから構成されていることを特徴とする請求項１に記載の半導体装置。The said 2nd insulating adhesive layer is comprised from the insulating film-like adhesive layer which has low viscosity thermoplasticity, and the insulating film-like adhesive layer which has high viscosity plasticity, The Claim 1 characterized by the above-mentioned. Semiconductor device. 前記第２の絶縁性接着層は、さらに、前記ボンディングワイヤーを内在させることができない程度の高硬度絶縁層を含むことを特徴とする請求項３に記載の半導体装置。4. The semiconductor device according to claim 3, wherein the second insulating adhesive layer further includes a high-hardness insulating layer to such an extent that the bonding wire cannot be contained therein. 5. 前記第２の半導体チップの非回路形成面に請求項３及び請求項４に記載した第２の絶縁性接着層を形成する工程は、
少なくとも表面に所定の回路が形成されたウエハーの裏面に前記低粘度可塑性を有する絶縁性フィルム状接着層を貼り付ける工程と、前記高硬度フィルム状絶縁層を貼り付ける工程と、前記高粘度可塑性を有する絶縁性フィルム状接着層を貼り付ける工程と、ダイシングすることにより前記第２の半導体チップに分離する工程とにより構成されていることを特徴とする請求項１に記載の半導体装置の製造方法。The step of forming the second insulating adhesive layer according to claim 3 or 4 on the non-circuit formation surface of the second semiconductor chip,
A step of attaching the insulating film-like adhesive layer having low-viscosity plasticity to the back surface of the wafer on which at least a predetermined circuit is formed, and a step of attaching the high-hardness film-like insulating layer to the high-viscosity plasticity. 2. The method of manufacturing a semiconductor device according to claim 1, comprising: a step of attaching an insulating film-like adhesive layer having the same; and a step of separating the second semiconductor chip by dicing.
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