TWI304644B - A stack of flip chip packages - Google Patents

Description

1304644

[Technical field to which the invention pertains]

The present invention relates to a package, 3D package) electronic component stacking to form a [previously] three-dimensional package structure (three dimensi〇n 'specially related to a flip chip package stack structure having a flip chip. Just in the future, electronic products are trending toward thin thickness, versatility and extreme performance. Therefore, semiconductor packaging is required to be a system package (SIp), usually by stacking multiple chip package structures to form A three-dimensional package structure (3D package).

Referring to FIG. 1 , in a conventional three-dimensional package structure, a first electronic component 110, a guiding plate 120 and a second electronic component 130 are included, wherein the first electronic component 11 includes There is a first substrate lu and a first wafer 11 2 , the first wafer 11 2 is disposed on an upper surface 1 11 a ' of the first substrate ii and electrically connected to the first plurality of bonding wires 1 1 3 a substrate 11 1 , a gel 114 sealing the first wafer 112 and the bonding wires 113 ′′, wherein the first electronic component no further includes a plurality of zinc balls 11 5 , which are disposed on the first substrate 111 . One of the lower surfaces 丨丨丨b. The guiding plate 120 is disposed on the upper surface 丨丨1 of the first substrate 1 11 , and the guiding plate 120 is electrically connected to the first substrate 丨丨 1 by a plurality of solder balls 121 . The second electronic component 130 is disposed on the conductive board 120. The second electronic component 130 includes a second substrate 1 31 and a plurality of second wafers 132, and the second wafers 132. The plurality of bonding wires 133 are electrically connected to the second substrate 131 and the second wafers 133, and the plurality of sealing bodies 134 are sealed. Two wafers 1 3 2 and the soldering

Page 7 1304644 V. Inventive Note (2) - ' ------ - The conductive plate 120 is electrically connected to the second substrate 131 by a plurality of solder balls 122. In the three-dimensional sealing structure 1GG, the first electronic component 110; the electronic component 130 is stacked to achieve a highly functional S-type stack: * in the edge - electronic component 13M system The guide plate 12 is upward with the upper surface 131a. Therefore, the second wafer and the encapsulation system protrude from the second substrate, thereby causing the overall thickness of the three-dimensional package structure 100 to be thick, which is not conducive to electronic products. The thickness is required to be thinned. /, ', f Π Π = = Patent Announcement No. 589688 "Multi-chip package structure ii" a variety of flip-chip package stacking three-dimensional package structure; ;;; structure;!, including - first package, - middle a first package of the carrier strips, wherein, in the first package, the twin is bonded to one surface of a first carrier, and the plurality of first conductive members are disposed on the first carrier a surface for electrically connecting the intermediate carrier strips, the intermediate carrier strips are stacked on the first package body, and a plurality of conductive elements are disposed on the second surface of the intermediate carrier strips for Connecting the intermediate carrier strip and the second sealing body disposed on the intermediate carrier strip in the second package, a second wafer is bonded to one surface of the second carrier The second conductive elements are disposed on the second other surface for electrically connecting other components. The above-mentioned three-dimensional package has the function of versatility, but because the second package system is being stacked on the intermediate carrier strip, the first wafer system protrudes below the three-dimensional sealing structure, thereby causing The three-dimensional package structure has a better overall

1304644 V. INSTRUCTIONS (3) Thickness, which is not conducive to the thinning requirements of electronic products. SUMMARY OF THE INVENTION The main object of the present invention is to provide a kind of crystal crystallization, which is transmitted by Xiao Ling, a complex _ ray;; # _ 隹 构 构 、, 1 music ^ 3 笔 笔 、 、, a second electronic 亓 Du ★ ▲ Ding 7L piece, a plurality of manufacturing = guiding elements and - heat sink, the first electronic component system: containing: J: the second electronic component comprising - the second substrate and the setting of the second surface of the 'the lower surface a flip chip, the first substrate of the electrically conductive vias and the (four) two pure, the m 1 is connected to the second electronic component, the heat sink is disposed on the first right f!" coupling the first flip chip Wafer and the second flip chip,

The three-dimensional package stack of germanium thickness can improve the heat dissipation efficiency of the first and second flip chip. The second purpose of the present invention is to provide a flip chip package stack structure: electrical connection:::: connecting the first substrate and the second substrate for the component and the second electronic component And, the 曰: piece "the heat sink between the sulcus 7 substrate provides the first -1 曰I ΐ /, the first electrical barrier between the day and the day, reducing the incidence of electrical interference According to the present invention, a flip chip package stack structure includes a first electronic component, a plurality of electrical conductive components, and a plurality of electrical conductive components. An electronic component comprises a first substrate and a wire-clad crystal chip 2=7 flip chip is disposed on an upper surface of the first substrate, the one-piece component comprises a second substrate and a first Two flip chip, the first

1304644 V. INSTRUCTION DESCRIPTION (4) - The flip chip is disposed on the lower surface of one of the 土 甘 甘 俨 俨 t t t , , , , , , , , , , , , , , , , , , , , , , Private 丨r an electronic element β π /, a substrate, electrically conductive to the first% 7L 1 noon and the second electronic open do substrate, and the political hot film is set in the first The second crystal: work;; =, and heat the heat dissipation efficiency of the first flip-chip and the first n-sound, flip-chip package stack structure, and reduce the thickness to reduce the volume of the product. [Embodiment] The present invention will be described by way of the following examples. (4) The first specific embodiment of the invention, please refer to FIG. 2, a type of flip-chip Linger® structure 20 0 includes a first electronic component 21〇, a second electronic component 220, and a plurality of electrical leads. The bonding element 23Q and a smk) ^ a flip chip, the chip 212, the first flip chip 212 is provided with a plurality of bumps 212a 1 on an upper surface 2 11 a of the first substrate 21 1 . Preferably, an underfilling material 213 is filled between the upper surface 211 a and the first flip chip 2 12 to seal and protect the active surface of the first flip chip 21 2 . Bump 212 a. The flip chip package stack structure 200 can further include a plurality of solder balls 250 disposed on a lower surface 21 lb of the first substrate 211 for bonding to a printed circuit board. The second electronic component 220 includes a second substrate 221 and a second flip chip 222. The second flip chip 222 is disposed on the lower surface 221b of the second substrate 221 by a plurality of bumps 222a. Preferably, an underfill 223 is filled between the lower surface 221b and the second flip chip 222 to seal and protect the active surface of the second flip chip 222 and the bumps.

Page 10 1304644 V. Description of the invention (5) 222a. The electrical conductive elements 230 are connected to the first substrate 2U and the second substrate 22 1 for electrically conducting the first electronic component 2 and the second electronic component 220. The size of the first substrate 211 is the same as the size of the second substrate “I. The heat sink 240 is disposed between the first substrate 2Π and the second substrate 221, and the heat sink 240 is double-sided thermocoupled. Bonding the first flip chip 2 1 2 and the second flip chip 2 22 to improve heat dissipation efficiency of the first flip chip 21 2 and the second flip chip 222. In this embodiment, The first electronic component 21 0 further includes a first stiffener 214 disposed on the upper surface 211 a of the first substrate 211 , and the first reinforcing material 21 4 is adhered by a glue 24 1· The heat sink 240 is disposed, the first reinforcing material 214 is annular, strip-shaped or block-shaped, and the first reinforcing material 214 can surround the first flip chip 21 2 to strengthen the first electron. The structural strength of the component 210 is fixed to the heat sink 240 to avoid damaging the first flip chip 2 1 2 . Further, in the embodiment, the first electronic component 220 includes a second reinforcing material (seconcj stiffener) 224, which is disposed on the lower surface 221b of the second substrate 221, and the second reinforcing member 224 is also a glue 241. The heat sink 240 is disposed on the second reinforcing material 2 2 4 in a shape of a strip, a strip or a block, and the second reinforcing material 2 2 4 surrounds the second flip chip 21 2 to strengthen The structure of the second electronic component 2 2 0 and the protective flip-chip wafer 2 2 2 . Preferably, the flip chip package stack structure 20 0 further includes a heat dissipating component 260 , the heat dissipating component 26 The 0-series can be a heat sink or a heat sink, which can be disposed on the upper surface 221a of the second substrate 221, and the heat dissipating component 260 is thermally coupled to the second reinforcement 224 by the second substrate 221 The heat sink 240 for heat

Page 11 1304644 V. Conduction of the invention (6). In addition, in the present embodiment, the electrical conductive elements 23 are wound around the wafer, the second flip chip 2 2 2 and the heat sink 240. % θθ

In the flip chip package stack structure 200, the heat sink 240 is disposed between the first substrate 211 and the second substrate 21, and thermally couples the first flip chip 21 2 and the second flip chip. The heat dissipation efficiency of the first flip chip 212 and the flip chip 222 is increased, and the first electronic component 210 and the first electronic component 220 are stacked, because the first The flip chip 210 2 and the second flip chip 2 2 2 are located between the first substrate 21 1 and the first substrate 2 21 , so the flip chip package stack structure 2 can have a stereoscopic shape of 4 The package thickness is packaged to facilitate the thinning of the thickness of the electronic product' and the flip chip package stack structure 200 has better heat dissipation. Furthermore, the heat sink 240 disposed between the first substrate 211 and the second substrate 221 can provide an electrical barrier between the first flip chip 212 and the second flip chip 222 to reduce the first The flip chip 2 i 2 and the second flip chip 222 are electrically disturbed, thereby improving the electrical performance of the product.

In a second embodiment of the present invention, referring to FIG. 3, a flip chip package stack structure 30 includes a first substrate 31 (), a first flip chip 320, a second substrate 3 30, and a first substrate. a first flip chip 34 〇, a heat sink 350 and a plurality of electrical conductive elements 36 〇, the first substrate 31 has an upper surface 3 11 'the first flip chip 3 2 〇 is a plurality of convex Block 3 2 is joined to the upper surface 311. The second flip chip 34 is bonded to the lower surface 331 of the second substrate 330 by a plurality of bumps 341. The heat sink 350 is disposed on the upper surface 3 U of the first substrate 3 10 and is disposed on the first flip chip

Page 12 1304644 'Description of the invention (7) Between the sheet 3 2 0 and the second flip chip 34 4 。. In this embodiment, the heat sink 350 has a cavity 351 for receiving the first flip chip 320. The first conductive substrate 306 is connected to the first substrate 310 and the second substrate 330. The electrical conductive elements 306 surround the first flip chip 320 and the second flip chip. 34 〇 and the heat sink 35 〇 outside, in this embodiment, the electrical conductive elements 3 6 are solder balls. In the flip chip package stack structure 300, since the heat sink 3 50 is provided

The first substrate 310 0 is disposed between the first flip chip 320 and the second flip chip 340, so that the first flip chip 32 and the second flip chip 340 can be lifted. The heat dissipation efficiency is further ensured by the first flip chip 32 between the first flip chip 32 〇 and the second flip chip 34 籍 by the electrical barrier provided by the heat sink 350 . In the case of occurrence or electrical interference, the electrical performance of the flip-chip package stack structure is 3 〇〇. 1 The present invention is not limited to the spirit of the present invention. The scope of protection of the present invention is subject to change, and any changes and modifications made in the garden are known to those skilled in the art.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a conventional three-dimensional package stack structure; FIG. 2 is a cross-sectional view showing a flip chip package stack structure according to a first embodiment of the present invention; And FIG. 3 is a schematic cross-sectional view showing a stacked structure of a flip chip package according to a second embodiment of the present invention. Brief description of component symbols: 100-dimensional package structure 110 first electronic component 111 first substrate 111a upper surface 111b lower surface 112 first wafer 113 bonding wire 114 sealing body 115 fresh ball 120 guiding plate 121 fresh ball 122 solder ball 130 second Electronic component 131 second substrate 131a upper surface 131b lower surface 132 first - wafer 133 bonding wire 134 encapsulant 200 flip chip package stack: structure 210 first electronic component 211 - substrate 211a upper surface 211b lower surface 212 first Crystal chip 212a bump 213 underfill 214 first - reinforcing member 220 *---- electronic component 221 first - _ a substrate 221a upper surface 221b lower surface

Page 14 1304644 Brief description of the drawing 222 First-- flip chip 222a bump 223 underfill 224 second reinforcement 230 electrical conduction element 240 heat sink 250 solder ball 260 heat dissipation element 300 flip-chip package stack configuration 310 first The upper surface 320 of the substrate 311 is the first flip chip 321 bump 33 0 the second substrate 331 the lower surface 340 the second flip chip 341 the bump 350 the heat sink 351 the cavity 360 the electrical conductive element 241

Page 15

Claims (1)

1304644 ^·— τ, the scope of application for patents [application of patent specification 1, a type of flip chip, a first electric wafer, the first second electric wafer, the second plurality of electric substrates; and a heat sink and two substrates Between, film. 2. If the application contains a plurality of 3, such as the application of the first electronic stiffener), the heat sink. 4. If the application is for the first reinforcement 5, such as applying for a specialization, the first stiffener), the heat sink. 6. If the application for the special power is placed on the lower surface of the second substrate to adhere to the flip chip package stack structure described in item 5 of the scope, the package structure includes: the sub-element The first substrate and the first flip-chip wafer are disposed on an upper surface of the first substrate; the sub-element includes a second substrate and a second flip-chip wafer system disposed thereon a lower surface of the second substrate; the first conductive substrate is connected to the first substrate, and the second substrate is coupled to the first substrate and the first thermal substrate And a flip chip package stack structure according to the second flip-chip range, wherein the solder ball is disposed on the first substrate, and the flip chip package stack structure according to claim 1 is The component further includes a first reinforcing material (first is disposed on the upper surface of the first substrate to adhere to the flip chip package stack structure according to item 3 of the benefit range, and the material is annular. The flip chip package stack structure described in the above item 1 or 3, a first reinforcing material (se Cond Page 16 1304644 Sixth, the scope of application for patents 7 The reinforcement is a ring. In the second; the size and the filling of the wafer-sliding substrate described in the first item of the range and the straightening > the construction of the stack, 8. If the scope of the application is the same, the size is the same. The electrical conductive elements are in a ring-mounted stacked configuration, the gusset and the outer periphery of the heat sink. , μ 汲曰曰曰曰 汲曰曰曰曰 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Heat dissipating component; ^ : = ^ stacked structure, 11 , such as the patent application Fan Gu / / δ; set the ^ where the heat sink 俜Α 1 @, the day of the day package stack structure, 12, - kind of cover ^ The substrate is thermally coupled to the heat sink. The solar cell package stack structure comprises: two first substrate 'having an upper surface; a surface first-clad wafer disposed on the upper surface of the first substrate a second substrate; having a lower surface; a second flip chip, which is disposed on the lower surface of the second substrate; and a heat-dissipating layer disposed on the first substrate And a plurality of electrical conductive elements connected between the first substrate and the substrate; and 13, as claimed in claim 12 The flip chip package stack structure, Page 17 1304644 VI. Patent Application Coverage The heat sink has a cavity for receiving the first flip chip. The flip chip package stack structure of claim 12, wherein the electrical conductive elements surround the first flip chip, the second crystal wafer and the outer periphery of the heat sink. The flip chip package stack structure of claim 12, wherein the electrical conductive elements are solder balls. Page 18