TWM269571U - Multi-chip-on-film package and the flexible multi-layer wiring board for the same - Google Patents
Multi-chip-on-film package and the flexible multi-layer wiring board for the same Download PDFInfo
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- TWM269571U TWM269571U TW093220969U TW93220969U TWM269571U TW M269571 U TWM269571 U TW M269571U TW 093220969 U TW093220969 U TW 093220969U TW 93220969 U TW93220969 U TW 93220969U TW M269571 U TWM269571 U TW M269571U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Wire Bonding (AREA)
Description
M269571_ 四、創作說明(1) 【新型所屬之技術領域】 本創作係有關於一種半導體封裝構造,特別係有關於 一種適用於封裝南逸、度^子數之多晶片薄膜封裝^造及其 可撓性多層電路板。 ' 【先前技術】 習知晶片薄膜封裝(Chip-on-film package,c〇F)係 為一種常見的半導體封裝型態,其係將晶片覆晶接合' (Flip chip bonding)於軟性電路板(Flexible circuit board,FPC)之技術,其可將驅動Ic及其它電子 零件直接設置於薄膜(以11„)上,以達到更輕薄短小之目 的。 由於現今之電子產品皆要求具有較強之功能性,因此 必須增加晶片之輸出入端的數量,且用以承載晶片之可 性電路板其連接墊勢必要隨著晶片之輸出入端的數量而^ 加,但以現今之技術中,縮小連接墊之間距有其製程能力 的限制,當連接墊之間距小於6〇111]]時,排列過於密集之連 ^塾則容易發生短路之情況,倘若無法縮小連接墊之間距 $ ’則必須增長晶片之長度以配合無法縮小間距之連接 墊,:此,在晶圓切割與晶片封裝時容易發生晶 壞之情況。 s 人二f,第1圖,一種習知晶片薄膜封裝構造1 0 0係包 ^nn \ 日日片120及一底部填充材130,該電 捲為単層線路結構並包含—基材iu、一線路層 呆濩層1 1 3 ,該線路層丨i 2係形成於該基材丨丨丨之一M269571_ IV. Creation Instructions (1) [Technical Field to which the New Type belongs] This creation relates to a semiconductor package structure, and in particular to a multi-chip thin film package that is suitable for packaging Nanyi, and its number Flexible multilayer circuit board. '[Prior art] The conventional chip-on-film package (COF) is a common type of semiconductor package, which is used for flip chip bonding on flexible circuit boards ( Flexible circuit board (FPC) technology, which can drive the Ic and other electronic components directly on the film (with 11 „), in order to achieve lighter, thinner and shorter. Because today's electronic products are required to have strong functionality Therefore, the number of I / O terminals of the chip must be increased, and the connection pads of the flexible circuit board used to carry the chip must be increased with the number of I / O terminals of the chip. However, in the current technology, the distance between the connection pads is reduced. There is a limitation in its process capability. When the distance between the connection pads is less than 6〇111]], the arrangement is too dense and the short circuit is prone to occur. If the distance between the connection pads cannot be reduced, the length of the chip must be increased to With connection pads that cannot reduce the pitch: this, crystal breakage is easy to occur during wafer dicing and wafer packaging. Figure 2f, Figure 1, a conventional wafer thin film package 1 0 0 series package ^ nn \ RiRi film 120 and an underfill material 130, the electric coil is a layered circuit structure and includes-the substrate iu, a circuit layer dull layer 1 1 3, the circuit layer 丨 i 2 series is formed on one of the substrates
第6頁 M269571_ 四、創作說明(2) 表面11 1 a ’該保護層11 3係形成於該線路層i丨2,以保護該 線路層11 2 ’其中,該線路保護層丨丨3係具有一開口 11 3 a以 顯露出該線路層11 2之複數個覆晶接墊丨丨2a。該晶片1 2 〇係 具有一主動面121 ’並包含形成於該主動面121之複數個凸 塊122(如第2圖所示),其係電性連接該晶片12〇與該些覆 晶接塾112a。該底部填充材13〇係形成於該電路捲帶丨丨〇與 該晶片1 2 0之間,以密封該晶片1 2 〇之該主動面j 2 1與該些 覆晶接墊112a。 由於在習知多晶片薄膜封裝構造中,該晶片i 2 〇係藉 由该些覆晶接墊i 1 2 a電性連接至該電路捲帶11 〇,然而, 隨著該晶片1 20之端子數增加,該晶片12〇之該些凸塊j 22 數則會跟著增加,但由於該些覆晶接墊丨丨2a之排列間距有 一製程能力的限制,若排列間距過小該些覆晶接墊丨丨2 a會 有短路之問題發生,且會增加該些覆晶接墊112&於製造過 程中之困難度。 【新型内容】 本創作之主要目的係在於提供一種多晶片薄膜封裝構 造’其係包含一可撓性多層電路板、一第一晶片、複數個 凸塊、一第二晶片及複數個鮮線,該可撓性多層電路板係 包含一第一線路層、複數個打線接墊、一第二線路層及複 數個覆晶接墊,該些打線接墊係電性連接至該第一線路 層,該些覆晶接墊係電性連接至該第二線路層,該第一晶 片係藉由該些凸塊以連接至該些覆晶接墊,該些銲線係連 接違第二晶片與該些打線接塾,該可撓性多層電路板係以 M269571__ 四、創作說明(3) 該第一線路層與該第二線 二晶片,故可增強該多晶 本創作之次一目的係 板’其係包含一基材、一 一第一線路層及複數個覆 接至該第一線路層,該些 路層,其中,該些覆晶接 曰日片電性連接’因此該可 複數個晶片,以製造出高 依本創作之多晶片薄 第^一晶片 多層電路板 數個銲線,該可撓性多層 路層、複數個打線接墊、 墊,該基材係具有一上表 形成於該基材之該上表面 之該上表面並電性連接至 形成於該基材之該下表面 二線路層,該第一晶片係 含在該主動面上之複數個 一晶片之該些第一銲塾與 有一主動面並包含複數個 墊,該些銲線係連接該第 線接墊,以適用於封裝高 【實施方式】 路層電性連接該第一晶 片薄膜封裝之功能性。 在於提供一種可撓性多 第一線路層、複數個打 晶接塾,該些打線接塾 覆晶接墊係電性連接至 墊與該些打線接墊係可 撓性多層電路板係可適 功能性之多晶片薄膜封 膜封裝構造,其係包含 、複數個凸塊、一第二 電路板係包含^—基材、 一第二線路層及複數個 面及一下表面,該第一 ’該些打線接墊係顯露 該第一線路層,該第二 ,該些覆晶接墊係電性 具有一主動面以及一背 第一輝墊,該些凸塊係 該些覆晶接墊,該第二 在該主動面上之複數個 二晶片之該些第二銲塾 密度端子數之晶片。 片與該第 層電路 線接墊、 係電性連 該第二線 供複數個 用於承載 裝構造。 一可撓性 晶片及複 一第一線 覆晶接 線路層係 於該基材 線路層係 連接該第 面,並包 連接該第 晶片係具 第二銲 與該些打Page 6 M269571_ IV. Creation Instructions (2) Surface 11 1 a 'The protective layer 11 3 is formed on the circuit layer i 丨 2 to protect the circuit layer 11 2', where the circuit protective layer 丨 丨 3 has An opening 11 3 a is provided to expose the plurality of flip-chip pads 2 a of the circuit layer 11 2. The wafer 1 2 0 has an active surface 121 ′ and includes a plurality of bumps 122 (as shown in FIG. 2) formed on the active surface 121, which are electrically connected to the wafer 12 0 and the flip-chips.塾 112a. The underfill material 13 is formed between the circuit tape 丨 丨 0 and the wafer 120 to seal the active surface j 2 1 of the wafer 120 and the flip-chip pads 112a. Because in the conventional multi-chip thin film package structure, the chip i 2 0 is electrically connected to the circuit tape 11 by the flip-chip pads i 1 2 a, however, with the number of terminals of the chip 1 20 Increase, the number of bumps j 22 of the wafer 12 will increase, but due to the limitation of the process capability of the 2P array pads, the 2C pads will be limited if the array pitch is too small.丨 2 a There will be a short circuit problem, and it will increase the difficulty of the flip-chip pads 112 & in the manufacturing process. [New content] The main purpose of this creation is to provide a multi-chip thin-film package structure, which includes a flexible multilayer circuit board, a first chip, a plurality of bumps, a second chip, and a plurality of fresh wires. The flexible multilayer circuit board includes a first circuit layer, a plurality of wire bonding pads, a second circuit layer, and a plurality of flip-chip pads. The wire bonding pads are electrically connected to the first circuit layer. The flip-chip pads are electrically connected to the second circuit layer, the first chip is connected to the flip-chip pads through the bumps, and the bonding wires are connected to the second chip and the chip. These flexible multi-layer circuit boards are based on M269571__ IV. Creation instructions (3) The first circuit layer and the second wire and two chips can enhance the second-purpose system board of the polycrystalline book creation. It includes a substrate, a first circuit layer, and a plurality of circuit layers connected to the first circuit layer, the circuit layers, wherein the flip-chips are electrically connected to the Japanese chip, so the plurality of chips can be connected. To make as many thin wafers as possible. Layer circuit board with several bonding wires, the flexible multilayer circuit layer, a plurality of wire bonding pads, and pads, the substrate has an upper surface formed on the upper surface of the upper surface of the substrate and is electrically connected to the upper surface The two circuit layers formed on the lower surface of the substrate, the first chip includes the first solder pads of a plurality of wafers on the active surface and an active surface and includes a plurality of pads, the bonding wires It is connected to the first wire pad, which is suitable for packaging. [Embodiment] The circuit layer is electrically connected to the functionality of the first chip thin film package. The invention is to provide a flexible first circuit layer and a plurality of chip bonding pads. The chip bonding pads are electrically connected to the pads and the multi-layer printed circuit boards are flexible. Functional multi-chip thin film encapsulation package structure, which includes, a plurality of bumps, a second circuit board includes a substrate, a second circuit layer and a plurality of surfaces and a lower surface. The wire bonding pads expose the first circuit layer, the second, the flip-chip pads have an active surface and a first glow pad, and the bumps are the flip-chip pads. A plurality of second wafers with a plurality of second solder density terminals on the active surface. The chip is electrically connected to the first-layer circuit line pad, and the second line is provided for a plurality of load-bearing structures. A flexible chip and a plurality of first-line chip-on-chip circuit layers are connected to the substrate, the circuit layer system is connected to the first surface, and the first chip device is connected to the second solder and the plurality of printed circuits.
第8頁 M269571 _ 四、創作說明(4) 參閱所附圖式,本創作將列舉以下之實施例說明。 依本創作之第一具體實施例,請參閱第3及4圖,一 多晶片薄膜封裝構造200係包含一可撓性多層電路板21 〇、 一第一晶片220、一第二晶片230及複數個銲線240,該可 撓性多層電路板21 〇係包含一基材21 1、一第一線路層 2 1 2、複數個覆晶接墊21 3、一第二線路層214及複數個打 線接墊215。其中,該基材211係具有一上表面2 lla、一下 表面21 lb,該第一線路層212係形成於該基材21 1之該上表 面211a,該第二線路層2 14係形成於該基材211之該下表面 21 lb ’複數個打線接墊2 15係顯露於該基材211之該上表面 211 a並電性連接至該第一線路層2丨2,且複數個覆晶接墊 213係顯露於該基材211之該上表面2 1 ia並電性連接至該第 二線路層21 4。在本實施例中,該可撓性多層電路板2丨〇係 包含複數個鍍通孔21 6,其係電性連接該些覆晶接墊21 3與 該第二線路層21 4,此外,該些覆晶接墊21 3之間距係可大 於6 0 /z m,較佳地,該可撓性多層電路板21 〇係包含一第一 保護層217,其係形成於該第一線路層212與該基材211之 該上表面211a,並具有至少一開口217a,該開口217a係顯 露該些覆晶接墊21 3,該開口 21 7a係更顯露該些打線接墊 21 5。該可撓性多層電路板2 1 〇係另包含一第二保護層 218,其係形成於该第一線路層214與該基材211之該下表 面2 11 b以保護該該第二線路層21 4。 該第一晶片220係覆晶接合至該基材2U之該上表面 211a ’該第一晶片220係具有一主動面221以及一背面222Page 8 M269571 _ IV. Creation Instructions (4) With reference to the attached drawings, this creation will enumerate the following embodiment descriptions. According to the first embodiment of this creation, please refer to FIGS. 3 and 4. A multi-chip thin film package structure 200 includes a flexible multilayer circuit board 21, a first chip 220, a second chip 230 and a plurality of Bonding wires 240. The flexible multilayer circuit board 21 includes a substrate 21, a first circuit layer 2 1 2, a plurality of flip-chip pads 21 3, a second circuit layer 214, and a plurality of bonding wires.接 垫 215。 215 pads. The substrate 211 has an upper surface 21a and a lower surface 21 lb. The first circuit layer 212 is formed on the upper surface 211a of the substrate 21 1. The second circuit layer 214 is formed on the substrate. The lower surface 21 lb of the substrate 211 is provided with a plurality of wire bonding pads 2 15 exposed on the upper surface 211 a of the substrate 211 and electrically connected to the first circuit layer 2 丨 2, and a plurality of flip-chip contacts The pad 213 is exposed on the upper surface 2 1 ia of the substrate 211 and is electrically connected to the second circuit layer 21 4. In this embodiment, the flexible multilayer circuit board 20 includes a plurality of plated through holes 21 6, which are electrically connected to the flip-chip pads 21 3 and the second circuit layer 21 4. In addition, The distance between the flip-chip pads 21 3 may be greater than 60 / zm. Preferably, the flexible multilayer circuit board 21 includes a first protective layer 217 formed on the first circuit layer 212. The upper surface 211a of the substrate 211 has at least one opening 217a. The opening 217a exposes the flip-chip pads 21 3, and the opening 21 7a exposes the wire bonding pads 21 5. The flexible multilayer circuit board 2 10 further includes a second protective layer 218 formed on the lower surface 2 11 b of the first circuit layer 214 and the substrate 211 to protect the second circuit layer. 21 4. The first wafer 220 is flip-chip bonded to the upper surface 211a of the substrate 2U. The first wafer 220 has an active surface 221 and a back surface 222.
M269571 四、創作說明(5)M269571 Fourth, creation instructions (5)
並包含在該主動面221上之複數個第一銲墊223,複數個凸 塊224係連接該第一晶片220之該些第一銲墊223與該些覆 晶接墊2 1 3,在本實施例中,該第一保護層21 7之該開口 217係大於該第一晶片220之主動面221,較佳地,該多晶 片薄膜封裝構造200係包含一底部填充材(Underfilling material )25 0於該第一晶片220與該可撓性多層電路板21〇 之間,以密封該些覆晶接墊2 1 3與該第一晶片2 2 0之該主動 面221。或者,形成一角隅接合膠(c〇rner b〇nd)於該該第 一晶片220與該可撓性多層電路板21 〇之間,以密封該些覆 晶接塾213及該些凸塊224,以節省膠量。該第二晶片230 係堆疊設置於該第一晶片220之該背面222,該第二晶片 230係具有一主動面231,並包含複數個在該主動面231上 之第二銲墊232,該些銲線240係連接該第二晶片230之該 些第一銲墊2 3 2與該些打線接墊2 1 5,在本實施例中,該多 晶片薄膜封裝構造200係包含一封膠體26〇,其係形成於該 基材21 1之該上表面21 la,以密封該第一晶片22〇、該第二 晶片230與該些銲線240。其中,該封膠體26()係可為一種 點塗形成之液態膠(liquid compound)。A plurality of first pads 223 are included on the active surface 221, and a plurality of bumps 224 are connected to the first pads 223 of the first wafer 220 and the flip-chip pads 2 1 3. In the embodiment, the opening 217 of the first protective layer 21 7 is larger than the active surface 221 of the first chip 220. Preferably, the multi-chip thin film packaging structure 200 includes an underfilling material 250. Between the first chip 220 and the flexible multilayer circuit board 210, the chip-on pads 2 1 3 and the active surface 221 of the first chip 220 are sealed. Alternatively, a corner bonding adhesive (corner bond) is formed between the first chip 220 and the flexible multilayer circuit board 21 o to seal the flip-chip connectors 213 and the bumps 224. To save glue volume. The second wafer 230 is stacked on the back surface 222 of the first wafer 220. The second wafer 230 has an active surface 231 and includes a plurality of second pads 232 on the active surface 231. The bonding wire 240 is connected to the first bonding pads 2 3 2 and the bonding pads 2 1 5 of the second chip 230. In this embodiment, the multi-chip thin film packaging structure 200 includes a colloid 26. It is formed on the upper surface 21 la of the substrate 21 1 to seal the first wafer 22, the second wafer 230 and the bonding wires 240. The sealing compound 26 () may be a liquid compound formed by spot coating.
依據本創作之多晶片薄膜封裝構造2 〇 〇,由於該第一 晶片22 0、該第二晶片23 0係設置於該可撓性多層電路板 wo並個別藉由該些打線接墊214、該些覆晶接墊213與該 可撓性多層電路板200電性導通,以適用於封裝高密度端 =數之晶片,可解決該些覆晶接墊213或打線接墊215之數 篁不足之問題,進而使得產品之體積得以縮小,且又可提According to the multi-chip thin-film package structure 2000 created by this creation, since the first chip 220 and the second chip 230 are disposed on the flexible multilayer circuit board wo, and individually through the wire bonding pads 214, the The flip-chip pads 213 are electrically connected to the flexible multilayer circuit board 200 so as to be suitable for packaging high-density terminals. The chip-pads 213 or wiring pads 215 can solve the deficiency Problems, which in turn reduces the size of the product, and
第10頁 M269571___ 四、創作說明(6) 昇產品之功能性。 本創作係可將裝設之晶片作適當調整,在本創作之第 二具體實施例中,另一種多晶片薄膜封裝構造係可設置複 數個晶片於一捲帶之不同表面,請參閱第5圖,一多晶片 薄膜封裝構造300係包含一可撓性多層電路板31〇、一第一 晶片320、複數個凸塊330、一第二晶片350及複數個銲線 360,該可撓性多層電路板310係包含一基材311、一第一 線路層312、複數個打線接墊313、一第二線路層314及複 數個覆晶接墊315,其中該基材3 11係具有一上表面3lla及 一下表面311b,該第一線路層312係形成於該基材3 11之該 上表面311a,複數個打線接墊313係顯露於該基材3 11之該 上表面311a並電性連接至該第一線路層312,該第二線路 層314係形成於e亥基材311之該下表面311b,複數個覆晶接 塾315係顯露於该基材311之該下表面311b,並且,該些覆 晶接墊3 1 5係電性連接至該第二線路層3丨4,較佳地,該可 撓性多層電路板3 1 0係包含複數個黏膠層3丨6,其係形成於 該基材311之該上表面3 lla與該下表面311b,以分別黏結 該第一線路層312與該第二線路層314於該基材311。在本 實施例中,該可撓性多層電路板3丨〇係包含一第一保護層 3 1 7與一第二保護層3 1 8,該第一保護層3丨7係形成於該第 一線路層312與該基材311之該上表面311a上,該第二保護 層318係另形成於該第二線路層314與該基材311之該下表 面311b上並具有一顯露該些覆晶接墊315之開口3i8a。 該第一晶片32 0係覆晶接合至該可撓性多層電路板3 i ◦ 第11頁 M269571 四、創作說明(7) 之該下表面311b,該第一晶片320係具有一主動面321並包 含複數個在該主動面321之第一銲墊322,該些第一銲塾 322係藉由複數個凸塊330與該些覆晶接塾315連接,較佳 地’ 一角隅接合膠340(corner bond)係形成於該可撓性多 層電路板3 1 0與該第一晶片3 2 0之間,以密封該些覆晶接墊 315、該些凸塊330及該第一晶片320之該主動面321。該第 二晶片3 5 0係設置於該基材3 11之該上表面311 a,且該第二 晶片350係具有一主動面351並包含複數個在該主動面351 上之第二銲墊352。複數個銲線360係電性連接該第二晶片 350之該些第二銲墊352與該些打線接墊31 3。在本實施例 中,一種可由液態膠固化形成之封膠體370係形成於該基 材3 11之該上表面3 11 a,以密封該第二晶片3 5 0與該些銲線 360 。 — 'Page 10 M269571___ IV. Creative Instructions (6) Functionality of the product. In this creation, the installed wafer can be adjusted appropriately. In the second embodiment of this creation, another multi-chip thin film packaging structure can be provided with a plurality of wafers on different surfaces of a reel, please refer to FIG. 5 A multi-chip thin-film package structure 300 includes a flexible multilayer circuit board 310, a first chip 320, a plurality of bumps 330, a second chip 350, and a plurality of bonding wires 360. The flexible multilayer circuit The board 310 includes a substrate 311, a first circuit layer 312, a plurality of wiring pads 313, a second circuit layer 314, and a plurality of flip-chip pads 315. The substrate 3 11 has an upper surface 31a. With the lower surface 311b, the first circuit layer 312 is formed on the upper surface 311a of the substrate 3 11, and a plurality of wire bonding pads 313 are exposed on the upper surface 311 a of the substrate 3 11 and are electrically connected to the upper surface 311 a. The first circuit layer 312 and the second circuit layer 314 are formed on the lower surface 311b of the substrate 311, and a plurality of flip-chip contacts 315 are exposed on the lower surface 311b of the substrate 311. The flip-chip pads 3 1 5 are electrically connected to the second circuit layer 3 丨 4, preferably The flexible multilayer circuit board 3 1 0 includes a plurality of adhesive layers 3 丨 6, which are formed on the upper surface 3 lla and the lower surface 311b of the substrate 311 to respectively bond the first circuit layer. 312 and the second circuit layer 314 are on the substrate 311. In this embodiment, the flexible multilayer circuit board 3 1 0 includes a first protective layer 3 1 7 and a second protective layer 3 1 8, and the first protective layer 3 1 7 is formed on the first The circuit layer 312 and the upper surface 311a of the substrate 311, the second protective layer 318 is further formed on the second circuit layer 314 and the lower surface 311b of the substrate 311 and has a plurality of exposed crystals The opening 3i8a of the pad 315. The first wafer 320 is bonded to the flexible multilayer circuit board 3 i ◦ M269571 on page 11. Fourth, the lower surface 311b of the creative description (7), the first wafer 320 has an active surface 321 and Containing a plurality of first pads 322 on the active surface 321, the first pads 322 are connected to the flip-chip pads 315 through a plurality of bumps 330, preferably a corner joint adhesive 340 ( corner bond) is formed between the flexible multilayer circuit board 3 1 0 and the first wafer 3 2 0 to seal the flip-chip pads 315, the bumps 330 and the first wafer 320. Active surface 321. The second wafer 3 50 is disposed on the upper surface 311 a of the substrate 3 11, and the second wafer 350 has an active surface 351 and includes a plurality of second pads 352 on the active surface 351. . The plurality of bonding wires 360 are electrically connected to the second bonding pads 352 of the second chip 350 and the bonding pads 31 3. In this embodiment, a sealant 370 formed by curing the liquid glue is formed on the upper surface 3 11 a of the substrate 3 11 to seal the second wafer 3 50 and the bonding wires 360. — '
在該多晶片薄膜封裝構造3 0 0中,為了增加其功能 性,藉由該可撓性多層電路板310之該些打線接墊3 13、該 些覆晶接墊315使該第一晶片320、該第二晶片350與該可 撓性多層電路板31 0電性導通,因此,該些覆晶接墊3丨3之 間距則可以大於60 /z m,以避免產生短路之情況,此外,也 可避免因该第一晶片320或第二晶片350之長度過長,而使 該第一晶片320或該第二晶片350發生破裂之情況,以增加 產品之良率。 本創作之保護範圍當視後附之申請專利範圍所界定者 為準,任何熟知此項技藝者,在不脫離本創作之精神和範 圍内所作之任何變化與修改,均屬於本創作之保護範圍。In the multi-chip thin-film package structure 300, in order to increase its functionality, the first chip 320 is made by the wire bonding pads 3 of the flexible multilayer circuit board 310 and the flip-chip pads 315. 2. The second chip 350 and the flexible multilayer circuit board 3100 are electrically connected. Therefore, the distance between the flip-chip pads 3 and 3 can be greater than 60 / zm to avoid the occurrence of a short circuit. In addition, It is possible to prevent the first wafer 320 or the second wafer 350 from being cracked due to the length of the first wafer 320 or the second wafer 350 to increase the yield of the product. The scope of protection of this creation shall be determined by the scope of the attached patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of this creation shall fall within the scope of protection of this creation. .
M269571 — 圖式簡單說明 ^ ------ 1 - 【圖式簡單說明】 第1圖··習知晶片薄膜封裝構造之截面示意圖; 第2圖··習知晶片薄膜封裝構造之一晶片之底視圖;(文 中未提) 第3圖:依據本創作之第一具體實施例,一種多晶片薄膜 封裝構造之截面示意圖; 第4圖··依據本創作之第一具體實施例,該可撓性多層電 路板之上視圖;及 'M269571 — Simple illustration ^ ------ 1-[Simplified illustration] Figure 1 ·· Sectional schematic diagram of the conventional wafer thin film packaging structure; Figure 2 ·· One of the conventional wafer thin film packaging structures Bottom view; (not mentioned in the text) Figure 3: A cross-sectional view of a multi-chip thin film package structure according to the first specific embodiment of the present invention; Figure 4 · According to the first specific embodiment of the present invention, the Overhead view of a flexible multilayer circuit board; and '
第5圖:依據本創作之第二具體實施例,一種多晶片薄膜 封裝構造之截面示意圖。FIG. 5 is a schematic cross-sectional view of a multi-chip thin film package structure according to a second embodiment of the present invention.
元件符號簡單說明: 100 晶片薄膜封裝構造 110 捲帶 111 基材 111a 表面 112 線路層 112a 覆晶接墊 113 保護層 113a 開口 120 晶片 121 主動面 122 凸塊 130 底部填充材 200 多晶片薄膜封裝構造 210 可撓性多層 電路板 211 基材 211a 上表面 211b 下表面 212 第一線路層 213 覆晶接墊 214 第—線路層 215 打線接塾 216 鍍通孔 217 第一保護層 217a 開口Simple explanation of component symbols: 100-chip thin-film package structure 110 tape 111 substrate 111a surface 112 circuit layer 112a flip-chip pad 113 protective layer 113a opening 120 chip 121 active surface 122 bump 130 underfill material 200 multi-chip thin film package structure 210 Flexible multilayer circuit board 211 substrate 211a upper surface 211b lower surface 212 first circuit layer 213 flip-chip pad 214 first-circuit layer 215 wiring connection 216 plated through hole 217 first protective layer 217a opening
第13頁 M96QS71 圖式簡單說明Page 13 M96QS71 Schematic description
第14頁 218 第二保護層 220 第一晶片 221 主動面 222 背面 223 第一鲜墊 224 凸塊 230 第二晶片 231 主動面 232 第二銲 240 銲線 250 底部填充材 260 封膠體 300 多晶片薄膜封裝構 造 310 可撓性多層電路板 311 基材 311a 上表面 311b 下表面 312 第一線路層 313 打線接墊 314 第二線路層 315 覆晶接墊 316 黏膠層 317 第一保護層 318 第二保護層 318a 開口 320 第一晶片 321 主動面 322 第一銲 330 凸塊 340 角隅接合膠 350 第二晶片 351 主動面 352 第二銲 360 銲線 370 封膠體Page 14 218 Second protective layer 220 First wafer 221 Active surface 222 Back surface 223 First fresh pad 224 Bump 230 Second wafer 231 Active surface 232 Second welding 240 Welding wire 250 Underfill 260 Sealant 300 Multi wafer film Package structure 310 Flexible multilayer circuit board 311 Substrate 311a Upper surface 311b Lower surface 312 First circuit layer 313 Wire bonding pads 314 Second circuit layer 315 Chip-on-chip pads 316 Adhesive layer 317 First protective layer 318 Second protection Layer 318a, opening 320, first wafer 321, active surface 322, first solder 330, bump 340, fillet bonding adhesive 350, second wafer 351, active surface 352, second welding 360, welding line 370, and sealant
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TWI460797B (en) * | 2011-02-23 | 2014-11-11 | Sharp Kk | Semiconductor device and method for manufacturing type carrier semiconductor device |
CN111584436A (en) * | 2020-05-27 | 2020-08-25 | 上海天马微电子有限公司 | Chip on film and method for manufacturing the same |
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Cited By (2)
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TWI460797B (en) * | 2011-02-23 | 2014-11-11 | Sharp Kk | Semiconductor device and method for manufacturing type carrier semiconductor device |
CN111584436A (en) * | 2020-05-27 | 2020-08-25 | 上海天马微电子有限公司 | Chip on film and method for manufacturing the same |
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