CN111584436A - Chip on film and method for manufacturing the same - Google Patents

Chip on film and method for manufacturing the same Download PDF

Info

Publication number
CN111584436A
CN111584436A CN202010460228.4A CN202010460228A CN111584436A CN 111584436 A CN111584436 A CN 111584436A CN 202010460228 A CN202010460228 A CN 202010460228A CN 111584436 A CN111584436 A CN 111584436A
Authority
CN
China
Prior art keywords
layer
patterned
substrate
mother substrate
patterned conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010460228.4A
Other languages
Chinese (zh)
Inventor
周一安
王林志
董崔健
席克瑞
孔祥建
刘金娥
秦锋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Tianma Microelectronics Co Ltd
Original Assignee
Shanghai Tianma Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Tianma Microelectronics Co Ltd filed Critical Shanghai Tianma Microelectronics Co Ltd
Priority to CN202010460228.4A priority Critical patent/CN111584436A/en
Publication of CN111584436A publication Critical patent/CN111584436A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

The invention discloses a chip on film and a manufacturing method thereof. The embodiment of the invention provides a manufacturing method of a chip on film, which comprises the following steps: sequentially forming a first seed layer and a first light resistance layer on the mother substrate; patterning the first photoresist layer to form a first intermediate substrate having a first patterned photoresist layer and a first hollow area; forming a first metal layer on the first seed layer exposed at least in the first hollow area; and removing the first patterned photoresist layer and the first seed layer which is not covered by the first metal layer in the first hollow-out area to form the initial conductive substrate with the first patterned conductive layer. According to the chip on film and the manufacturing method thereof, the metal layer has higher precision and thicker thickness.

Description

Chip on film and method for manufacturing the same
Technical Field
The invention relates to the field of electronic circuits, in particular to a chip on film and a manufacturing method thereof.
Background
Generally, an electronic device (e.g., a display device) includes a flexible circuit board (flexible circuit board) provided with an integrated circuit Chip (ic Chip), which is called a Chip On Film (COF), and the COF in the display device is generally bound to a binding region of a display panel for driving a display device.
However, the conventional flexible circuit board process has limited accuracy and cannot meet the requirements of the chip on film.
Disclosure of Invention
The invention provides a chip on film and a manufacturing method thereof, which can enable a metal layer to have higher precision and thicker thickness.
In a first aspect, an embodiment of the present invention provides a method for manufacturing a chip on film, including: providing a mother substrate; sequentially forming a first seed layer and a first light resistance layer on the mother substrate; patterning the first photoresist layer to form a first intermediate substrate with a first patterned photoresist layer and a first hollow area, wherein at least part of the first seed layer is exposed on the first intermediate substrate through the first hollow area; forming a first metal layer on the first seed layer exposed at least in the first hollow area; and removing the first patterned photoresist layer and the first seed layer which is not covered by the first metal layer in the first hollow-out area to form an initial conductive substrate with a first patterned conductive layer, wherein the initial conductive substrate is divided into a first binding area, a second binding area and a wiring area clamped between the first binding area and the second binding area in the first direction.
In a second aspect, an embodiment of the present invention provides a chip on film, including: a mother substrate; the first patterned conductive layer is located on the mother substrate and provided with a first pattern, the first patterned conductive layer comprises a first patterned seed layer and a first patterned metal layer, the first patterned seed layer is located on the mother substrate and provided with the first pattern, the first patterned metal layer is located on one side, back to the mother substrate, of the first patterned seed layer and provided with the first pattern, and the orthographic projection of the first patterned seed layer on the mother substrate is overlapped with the orthographic projection of the first patterned metal layer on the mother substrate.
According to the manufacturing method of the chip on film provided by the embodiment of the invention, the first metal layer is formed in the first hollow-out area of the first intermediate substrate through the first seed layer, so that the precision of the first metal layer is basically equal to that of the patterned first photoresist layer in the first intermediate substrate, and the patterned first photoresist layer can have higher precision, so that the first metal layer has higher precision. In addition, because the thicker whole layer of metal is difficult to etch the metal wiring layer with higher precision, the first metal layer is formed in the first hollow-out area after the first middle substrate is formed, so that the thickness can be thicker while the precision is ensured.
Drawings
Other features, objects and advantages of the invention will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.
FIG. 1 is a flow chart illustrating a method for manufacturing a chip on film according to an embodiment of the invention;
fig. 2 is a schematic top view of a flip chip film according to an embodiment of the invention;
fig. 3 to 14 are schematic structural diagrams illustrating steps of an embodiment of a method for manufacturing a chip on film according to the present invention;
fig. 15 to 33 are schematic structural diagrams illustrating steps of another embodiment of a method for manufacturing a chip on film according to the embodiment of the invention;
FIG. 34 illustrates a schematic cross-sectional view of one embodiment taken along line B-B in FIG. 2;
FIG. 35 shows a schematic cross-sectional view of another embodiment taken along line B-B in FIG. 2.
In the figure:
100-a mother substrate;
200-a first intermediate substrate; 210-a first patterned photoresist layer; 220-a first hollowed-out area;
300-an initial conductive substrate; 310-a first patterned conductive layer; 311-a first patterned seed layer; 312 — a first patterned metal layer;
400-a second intermediate substrate; 410-a second patterned photoresist layer; 420-a second hollowed-out area;
500-a second conductive substrate; 510-a second patterned conductive layer; 511-a second patterned seed layer; 512-a second patterned metal layer;
600-a planarization layer; 610-connecting hole;
700-a first conductive substrate; 710-a third patterned conductive layer;
810-a first protective layer; 820-a second protective layer;
900-packaging material;
f1-first seed layer; f2-first photoresist layer; f3 — first metal layer; f4-second seed layer; f5-second photoresist layer; f6-second metal layer; f7-third metal layer; BA 1-first binding area; BA 2-second binding area; LA-routing area; c1-chip; j1-pin.
Detailed Description
Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.
The wiring layer in the chip on film is usually manufactured by a flexible circuit board process, which etches the whole layer of metal to obtain a metal wiring layer.
However, as the resolution of the display panel in the display device is improved, the density of the metal wiring in the chip on film connected to the display panel is increased, and it is required to ensure good contact between the metal wiring and the chip in the chip on film while the density of the metal wiring is increased.
The applicant finds that increasing the thickness of the metal wiring layer in the flip chip enables the chip in the flip chip to be in better contact with the metal wiring layer in the flip chip. Moreover, the applicant finds that a thicker whole layer of metal is difficult to etch out a metal wiring layer with higher precision.
In order to solve the above problems, the present invention provides a flip chip film and a method for manufacturing the same, which can make a metal layer in the flip chip film have higher precision and thicker thickness.
Referring to fig. 1, fig. 1 is a flow chart illustrating a method for manufacturing a chip on film according to an embodiment of the invention.
As shown in fig. 1, an embodiment of the invention provides a method for manufacturing a chip on film.
The chip on film can be used for a display device. The chip on film may include a flexible circuit board and a chip disposed on the flexible circuit board.
The manufacturing method of the chip on film provided by the embodiment of the invention comprises the following steps:
s110: a mother substrate is provided.
The mother substrate may include a transparent or opaque insulating material. The mother substrate may include one or more layers. The mother substrate may include a flexible organic material layer, such as a polyimide-based resin layer. The mother substrate may further include an inorganic material layer, such as a silicon oxide layer, a silicon nitride layer.
In some embodiments, the mother substrate includes a stiffening layer and a flexible base layer disposed on the stiffening layer. The stiffening layer can be used for increasing the strength of the mother substrate, so that other layer structures can be formed on the mother substrate in a subsequent method. The stiffening layer may also be stripped off in a subsequent process step. The stiffening layer may be a layer of inorganic material, such as a silicon oxide layer, a silicon nitride layer. The flexible base layer may comprise one or more layers. The flexible base layer may include an organic material layer, such as a polyimide-based resin layer. The flexible base layer may also include a layer of inorganic material, such as a silicon oxide layer, a silicon nitride layer.
S120: a first seed layer and a first photoresist layer are sequentially formed on the mother substrate.
The first seed layer can be used as a conductive layer and a seed layer in the electroplating process. The first seed layer may be a metallic material, such as copper. The first seed layer may be entirely formed on the mother substrate through a sputtering process.
The first photoresist layer is formed on the surface of the first seed layer, which faces away from the mother substrate. The first photoresist layer may be a photoresist layer. The first photoresist layer can be formed by a spin-on process, for example.
S130: the first photoresist layer is patterned to form a first intermediate substrate having a first patterned photoresist layer and a first hollow area, and at least a portion of the first seed layer is exposed by the first intermediate substrate through the first hollow area.
The first photoresist layer can be exposed and developed by using a mask with a photoetching pattern to form a first intermediate substrate with a first hollow area.
S140: and forming a first metal layer on the first seed layer exposed at least in the first hollow area.
The first metal layer can be formed by electroplating or sputtering.
When the first metal layer is formed by electroplating, the first seed layer can be used as a conductive layer and a seed layer of the electroplating process. The first metal layer may be formed only on the first seed layer exposed in the first hollow area, that is, the first metal layer is located in the first hollow area of the first intermediate substrate. The thickness of the first metal layer can be controlled by controlling the rate and time of electroplating. The first metal layer with a relatively thick thickness can be prepared by an electroplating process. The thickness of the first metal layer may be 1 μm to 9 μm, for example 4 μm.
When the first metal layer is formed by sputtering, the first metal layer is formed on the first patterned photoresist layer and the first seed layer exposed in the first hollow area. Wherein the first metal layer on the first patterned photoresist layer can be removed in subsequent method steps.
S150: and removing the first patterned photoresist layer and the first seed layer which is not covered by the first metal layer in the first hollow-out area to form an initial conductive substrate with a first patterned conductive layer, wherein the initial conductive substrate is divided into a first binding area, a second binding area and a wiring area clamped between the first binding area and the second binding area in the first direction.
Wherein, the first patterned photoresist layer can be removed by an ashing process or a suitable wet or dry etching process. The first seed layer not covered by the first metal layer in the first hollow area may be removed by a wet or dry etching process.
The first direction may be a length extension direction of the flip chip. The initial conductive substrate may have a first terminal electrically connected to an external device such as a display panel, for example, at the first bonding region. The initial conductive substrate may have a second terminal electrically connected to the chip, for example, at the second bonding region. The routing region may include a lead. The first terminal and the second terminal may be electrically connected by a lead.
According to the manufacturing method of the chip on film provided by the embodiment of the invention, the first metal layer is formed in the first hollow-out area of the first intermediate substrate through the first seed layer, so that the precision of the first metal layer is basically equal to that of the patterned first photoresist layer in the first intermediate substrate, and the patterned first photoresist layer can have higher precision, so that the first metal layer has higher precision. In addition, the first metal layer is formed in the first hollow-out area after the first intermediate substrate is formed, so that the first metal layer can have a thicker thickness while the accuracy is ensured.
Referring to fig. 2 and fig. 3 to 14 together, fig. 2 is a schematic top view of a flip chip film according to an embodiment of the invention, and fig. 3 to 14 are schematic structural diagrams illustrating steps of an embodiment of a method for manufacturing a flip chip film according to an embodiment of the invention. The structural schematic diagrams of each step in fig. 3 to 14 are cross-sectional structural schematic diagrams along the line B-B in fig. 2.
In some embodiments, as shown in fig. 2, the flip chip has a first bonding area BA1, a second bonding area BA2, and a wiring area LA sandwiched between the first bonding area BA1 and the second bonding area BA 2.
As shown in fig. 3 to 14, the method for manufacturing a chip on film according to an embodiment of the present invention includes:
s201: as shown in fig. 3, a mother substrate 100 is provided.
As shown in fig. 3, the mother substrate 100 may include a stiffening layer 110 and a flexible base layer 120 on the stiffening layer 110. The stiffening layer 110 may be an inorganic material layer, such as a glass substrate. The flexible substrate 120 may be an organic material layer, a polyimide-based resin layer. The step S201 of providing the mother substrate 100 may specifically include providing a stiffening layer 110 and disposing a flexible base layer 120 on the stiffening layer 110.
S202: as shown in fig. 4, a first seed layer F1 and a first photoresist layer F2 are sequentially formed on the mother substrate 100.
The first seed layer F1 may be a metal layer, such as copper, among others. The first seed layer F1 may be deposited on the surface of the flexible base layer 120 facing away from the stiffening layer 110 by a sputtering process.
The first photoresist layer F2 may be a photoresist layer. The first photoresist layer F2 may be formed on the surface of the first seed layer F1 opposite to the stiffening layer 110 by a spin coating process.
S203: as shown in fig. 5, the first photoresist layer F2 is patterned to form a first intermediate substrate 200 having a first patterned photoresist layer 210 and first hollow areas 220, and the first intermediate substrate 200 exposes at least a portion of the first seed layer F1 through the first hollow areas 220.
The first photoresist layer F2 may be patterned by exposure and development processes to form the first intermediate substrate 200 having the first hollow areas 220.
S204: as shown in fig. 6, a first metal layer F3 is formed on the first seed layer F1 exposed at least in the first hollow area 220, and a first metal layer F3 is formed at least in the first hollow area 220.
The first metal layer F3 may be copper, for example. The first metal layer F3 may be formed on the first seed layer F1 exposed at the first hollow area 220 by electroplating using the first seed layer F1 as a conductive layer of an electroplating process. The first metal layer F3 is formed only on the first seed layer F1 exposed by the first hollow area 220.
S205: as shown in fig. 7 and 8, the first patterned photoresist layer 210 and the first seed layer F1 not covered by the first metal layer F3 in the first hollow area 220 are removed to form the initial conductive substrate 300 having the first patterned conductive layer 310, wherein the initial conductive substrate 300 corresponds to the first bonding area BA1, the second bonding area BA2 and the routing area LA sandwiched between the first bonding area BA1 and the second bonding area BA2 in the first direction.
Wherein, the first patterned photoresist layer 210 may be removed by an ashing process or a suitable wet or dry etching process. The first seed layer F1, which is not covered by the first metal layer F3 within the first hollow area 220, may be removed by a wet or dry etching process.
The formed first patterned conductive layer 310 may include a first patterned seed layer 311 and a first patterned metal layer 312.
The manufacturing method of the chip on film provided by the embodiment of the invention also comprises the following steps:
s206: as shown in fig. 9, a third metal layer F7 is further formed on the first patterned conductive layer 310 of the initial conductive substrate 300, and the third metal layer F7 covers the exposed surface of the first patterned conductive layer 310 to form the first conductive substrate 700 having the third patterned conductive layer 710.
The third metal layer F7 may be used to protect the first patterned conductive layer 310, for example, to prevent the first patterned conductive layer 310 from being oxidized. The material of the third metal layer F7 may be tin. The third metal layer F7 may be formed on the exposed surface of the first patterned conductive layer 310 by electroplating the first patterned conductive layer 310 as a conductive layer of an electroplating process.
S207: as shown in fig. 10, a first protective layer 810 is disposed in the routing area LA, and the first protective layer 810 covers the third patterned conductive layer 710 in the routing area LA and fills gaps between conductors therein.
The first protective layer 810 may be an insulating layer. The first protective layer 810 may be a solder resist, and the material may be, for example, a resin. The first protective layer 810 may electrically insulate the third patterned conductive layer 710 from other layers, and may also protect the third patterned conductive layer 710 from damage during other process (e.g., soldering process) steps. The first protective layer 810 may be formed by screen printing or stencil printing, for example.
In an embodiment where the third metal layer F7 is not formed on the first patterned conductive layer 310, the first protective layer 810 may cover the first patterned conductive layer 310 in the routing area LA and fill the gaps between the conductors therein.
In the step S207 of disposing the first passivation layer 810, the method for manufacturing the flip chip film according to the embodiment of the invention may include a step of dicing the flip chip film to form a flip chip film with a suitable size.
The manufacturing method of the chip on film of the embodiment of the invention also comprises the following steps:
s208: as shown in fig. 11, a chip C1 having leads J1 is disposed in the second bonding area BA2, and the leads J1 of the chip C1 are bond-connected to the third patterned conductive layer 710.
Wherein the pin J1 contacts and forms an electrical connection with the third patterned conductive layer 710, the chip C1 can receive and transmit electrical signals through the pin J1 and the third patterned conductive layer 710.
In an embodiment where the third metal layer F7 is not formed on the first patterned conductive layer 310, the lead J1 of the chip C1 may be in bonding connection with the first patterned conductive layer 310. The lead J1 makes contact and electrical connection with the first patterned conductive layer 310.
S209: as shown in fig. 12, an encapsulation material 900 is filled between the chip C1 and the mother substrate 100, such that the encapsulation material 900 covers the connected leads J1 and the third patterned conductive layer 710.
The encapsulation material 900 may be, for example, epoxy. The encapsulant 900 can fix the leads J1 and the third patterned conductive layer 710, and make good contact between the leads J1 and the third patterned conductive layer 710.
In an embodiment where the third metal layer F7 is not formed on the first patterned conductive layer 310, the encapsulant 900 may encapsulate the connected leads J1 and the first patterned conductive layer 310. The encapsulant 900 can fix the leads J1 and the first patterned conductive layer 310, and make good contact between the leads J1 and the first patterned conductive layer 310.
S210: as shown in fig. 13, a second protection layer 820 is disposed at the second bonding area BA2, and the second protection layer 820 covers at least the packaging material 900.
The second protective layer 820 may be an insulating layer. The material of the second protective layer 820 may be the same as that of the first protective layer 810. The second protective layer 820 can electrically insulate the leads J1 and the third patterned conductive layer 710 from other layers, and can also protect the leads J1 and the third patterned conductive layer 710 from damage during other process (e.g., soldering process) steps. The second protective layer 820 may be formed by screen printing or stencil printing, for example.
S211: as shown in fig. 14, the stiffening layer 110 is removed. The stiffening layer 110 may be removed by separating the stiffening layer 110 from the flexible base layer 120.
According to the method for manufacturing the chip on film of the embodiment of the invention, the first metal layer F3 is formed in the first hollow-out area 220 of the first intermediate substrate 200 through the first seed layer F1, so that the precision of the first metal layer F3 is substantially equal to that of the patterned first photoresist layer 210 in the first intermediate substrate 200, and the patterned first photoresist layer 210 can have higher precision, so that the first metal layer F3 has higher precision. Also, the first metal layer F3 according to the embodiment of the present invention is formed in the first hollow area 220 after the first intermediate substrate 200 is formed, so that it is possible to have a relatively thick thickness while ensuring accuracy.
According to the method for manufacturing the flip chip film of the embodiment of the invention, since the flip chip film is flexible and the flexible substrate 120 is relatively thin and flexible, the stiffening layer 110 is disposed to help support the formation of the first patterned conductive layer 310 and other layers.
Referring to fig. 2 and fig. 15 to 33 together, fig. 2 is a schematic top view of a flip chip film according to an embodiment of the invention, and fig. 15 to 33 are schematic structural diagrams illustrating steps of another embodiment of a method for manufacturing a flip chip film according to an embodiment of the invention. The structural schematic diagrams of each step in fig. 15 to 33 are cross-sectional structural schematic diagrams along the line B-B in fig. 2.
In other embodiments, the flip chip may have multiple wiring layers, which may be stacked. In the following embodiments, a flip-chip on film having two wiring layers is taken as an example for illustration.
The manufacturing method of the chip on film provided by the embodiment of the invention comprises the following steps:
s301: as shown in fig. 15, a mother substrate 100 is provided.
As shown in fig. 15, the mother substrate 100 may include a stiffening layer 110 and a flexible base layer 120 on the stiffening layer 110. The stiffening layer 110 may be an inorganic material layer, such as a glass substrate. The flexible substrate 120 may be an organic material layer, a polyimide-based resin layer. The step S301 of providing the mother substrate 100 may specifically include providing a stiffening layer 110 and disposing a flexible base layer 120 on the stiffening layer 110.
The method for manufacturing a chip on film according to the embodiment of the present invention further includes a step of forming an intermediate wiring layer on the mother substrate 100.
S302: as shown in fig. 16, a second seed layer F4 and a second photoresist layer F5 are sequentially formed on the mother substrate 100.
The second seed layer F4 may be a metal layer, such as copper. The second seed layer F4 may be deposited on the surface of the flexible base layer 120 facing away from the stiffening layer 110 by a sputtering process.
The second photoresist layer F5 may be a photoresist layer. The second photoresist layer F5 may be formed on the surface of the second seed layer F4 opposite to the stiffening layer 110 by a spin coating process.
S303: as shown in fig. 17, the second photoresist layer F5 is patterned to form a second intermediate substrate 400 having a second patterned photoresist layer 410 and second hollow areas 420, and the second intermediate substrate 400 exposes at least a portion of the second seed layer F4 through the second hollow areas 420.
The second photoresist layer F5 may be patterned by an exposure and development process to form the second intermediate substrate 400 having the second hollow area 420.
S304: as shown in fig. 18, a second metal layer F6 is formed on the second seed layer F4 exposed at least in the second hollow region 420.
The second metal layer F6 may be copper, for example. The second metal layer F6 may be formed on the second seed layer F4 exposed at the second hollow region 420 by electroplating using the second seed layer F4 as a conductive layer of an electroplating process. The second metal layer F6 is formed only on the second seed layer F4 exposed by the second hollow area 420.
In some alternative embodiments, the second metal layer F6 may be formed by sputtering, and the second metal layer F6 is formed on the second patterned photoresist layer 410 and the second seed layer F4 exposed by the second hollow area 420. Wherein the second metal layer F6 on the second patterned photoresist layer 410 can be removed in subsequent process steps.
S305: as shown in fig. 19 and 20, the second patterned photoresist layer 410 and the second seed layer F4 not covered by the second metal layer F6 in the second hollow area 420 are removed to form the second conductive substrate 500 having the second patterned conductive layer 510.
Wherein the second patterned photoresist layer 410 may be removed by an ashing process or a suitable wet or dry etching process. The second seed layer F4, which is not covered by the second metal layer F6 within the second hollow area 420, may be removed by a wet or dry etching process.
The formed second patterned conductive layer 510 may include a second patterned seed layer 511 and a second patterned metal layer 512.
S306: as shown in fig. 21, a planarization layer 600 is disposed on the second conductive substrate 500, and the planarization layer 600 fills gaps between conductors in the second patterned conductive layer 510.
The planarization layer 600 may be an organic material layer. The planarization layer 600 may be an insulating layer. The planarization layer 600 may be formed, for example, by a spin-on process.
S307: as shown in fig. 22, a connection hole 610 is opened on a surface of the planarization layer 600 facing away from the mother substrate 100, and at least a portion of the second patterned conductive layer 510 is exposed by the connection hole 610.
The connection hole 610 may be formed by a process such as wet etching, dry etching, or laser etching.
The step of forming the intermediate wiring layer on the mother substrate 100 may include the above-described steps S302 to S307.
The manufacturing method of the chip on film of the embodiment of the invention also comprises the following steps:
s308: as shown in fig. 23, a first seed layer F1 and a first photoresist layer F2 are sequentially formed on the intermediate wiring layer, specifically, a first seed layer F1 and a first photoresist layer F2 are sequentially formed on the planarization layer 600, and a first seed layer F1 is formed on the planarization layer 600 and extends to the second patterned conductive layer 510 exposed by the connection hole 610.
The first seed layer F1 may be a metal layer, such as copper, among others. The first seed layer F1 may be deposited on the surface of the flexible base layer 120 facing away from the stiffening layer 110 by a sputtering process.
The first photoresist layer F2 may be a photoresist layer. The first photoresist layer F2 may be formed on the surface of the first seed layer F1 opposite to the stiffening layer 110 by a spin coating process.
S309: as shown in fig. 24, the first photoresist layer F2 is patterned to form a first intermediate substrate 200 having a first patterned photoresist layer 210 and first hollow areas 220, and the first intermediate substrate 200 exposes at least a portion of the first seed layer F1 through the first hollow areas 220.
The first photoresist layer F2 may be patterned by exposure and development processes to form the first intermediate substrate 200 having the first hollow areas 220.
S310: as shown in fig. 25, a first metal layer F3 is formed on the first seed layer F1 exposed at least in the first hollow area 220, and a first metal layer F3 is formed at least in the first hollow area 220.
The first metal layer F3 may be copper, for example. The first metal layer F3 may be formed on the first seed layer F1 exposed at the first hollow area 220 by electroplating using the first seed layer F1 as a conductive layer of an electroplating process. The first metal layer F3 is formed only on the first seed layer F1 exposed by the first hollow area 220.
S311: as shown in fig. 26 and 27, the first patterned photoresist layer 210 and the first seed layer F1 not covered by the first metal layer F3 in the first hollow area 220 are removed to form the initial conductive substrate 300 having the first patterned conductive layer 310, wherein the initial conductive substrate 300 is divided into a first bonding area BA1, a second bonding area BA2, and a routing area LA sandwiched between the first bonding area BA1 and the second bonding area BA2 in the first direction.
Wherein, the first patterned photoresist layer 210 may be removed by an ashing process or a suitable wet or dry etching process. The first seed layer F1, which is not covered by the first metal layer F3 within the first hollow area 220, may be removed by a wet or dry etching process.
The formed first patterned conductive layer 310 may include a first patterned seed layer 311 and a first patterned metal layer 312.
The manufacturing method of the chip on film provided by the embodiment of the invention also comprises the following steps:
s312: as shown in fig. 28, a third metal layer F7 is further formed on the first patterned conductive layer 310 of the initial conductive substrate 300, and the third metal layer F7 covers the exposed surface of the first patterned conductive layer 310 to form the first conductive substrate 700 having the third patterned conductive layer 710.
The third metal layer F7 may be used to protect the first patterned conductive layer 310, for example, to prevent the first patterned conductive layer 310 from being oxidized. The material of the third metal layer F7 may be tin. The third metal layer F7 may be formed on the exposed surface of the first patterned conductive layer 310 by electroplating the first patterned conductive layer 310 as a conductive layer of an electroplating process.
S313: as shown in fig. 29, a first protective layer 810 is disposed in the routing area LA, and the first protective layer 810 covers the third patterned conductive layer 710 in the routing area LA and fills gaps between conductors therein.
The first protective layer 810 may be an insulating layer. The first protective layer 810 may be a solder resist, and the material may be, for example, a resin. The first protective layer 810 may electrically insulate the third patterned conductive layer 710 from other layers, and may also protect the third patterned conductive layer 710 from damage during other process (e.g., soldering process) steps. The first protective layer 810 may be formed by screen printing or stencil printing, for example.
In an embodiment where the third metal layer F7 is not formed on the first patterned conductive layer 310, the first protective layer 810 may cover the first patterned conductive layer 310 in the routing area LA and fill the gaps between the conductors therein.
In the step S207 of disposing the first passivation layer 810, the method for manufacturing the flip chip film according to the embodiment of the invention may include a step of dicing the flip chip film to form a flip chip film with a suitable size.
The manufacturing method of the chip on film of the embodiment of the invention also comprises the following steps:
s314: as shown in fig. 30, a chip C1 having leads J1 is disposed in the second bonding area BA2, and the leads J1 of the chip C1 are bond-connected to the third patterned conductive layer 710.
Wherein the pin J1 contacts and forms an electrical connection with the third patterned conductive layer 710, the chip C1 can receive and transmit electrical signals through the pin J1 and the third patterned conductive layer 710.
In an embodiment where the third metal layer F7 is not formed on the first patterned conductive layer 310, the lead J1 of the chip C1 may be in bonding connection with the first patterned conductive layer 310. The lead J1 makes contact and electrical connection with the first patterned conductive layer 310.
S315: as shown in fig. 31, an encapsulation material 900 is filled between the chip C1 and the mother substrate 100, such that the encapsulation material 900 covers the connected leads J1 and the third patterned conductive layer 710.
The encapsulation material 900 may be, for example, epoxy. The encapsulant 900 can fix the leads J1 and the third patterned conductive layer 710, and make good contact between the leads J1 and the third patterned conductive layer 710.
In an embodiment where the third metal layer F7 is not formed on the first patterned conductive layer 310, the encapsulant 900 may encapsulate the connected leads J1 and the first patterned conductive layer 310. The encapsulant 900 can fix the leads J1 and the first patterned conductive layer 310, and make good contact between the leads J1 and the first patterned conductive layer 310.
S316: as shown in fig. 32, a second protection layer 820 is disposed at the second bonding area BA2, and the second protection layer 820 encapsulates at least the encapsulation material 900.
The second protective layer 820 may be an insulating layer. The material of the second protective layer 820 may be the same as that of the first protective layer 810. The second protective layer 820 can electrically insulate the leads J1 and the third patterned conductive layer 710 from other layers, and can also protect the leads J1 and the third patterned conductive layer 710 from damage during other process (e.g., soldering process) steps. The second protective layer 820 may be formed by screen printing or stencil printing, for example.
S317: as shown in fig. 33, the stiffening layer 110 is removed. The stiffening layer 110 may be removed by separating the stiffening layer 110 from the flexible base layer 120.
The method for manufacturing a chip on film according to the embodiment of the invention prepares the stacked first patterned conductive layer 310 and the second patterned conductive layer 510, wherein the first metal layer F3 is formed in the first hollow-out area 220 of the first intermediate substrate 200 through the first seed layer F1, and the second metal layer F6 is formed in the second hollow-out area 420 through the second seed layer F4, so that the first metal layer F3 and the second metal layer F6 have higher precision and can have thicker thickness.
In addition, the manufacturing method of the chip on film of the embodiment of the invention can prepare the chip on film with a plurality of metal layers, so that more leads can be arranged on the chip on film under the condition that the size of the chip on film in the width direction is not too wide, and the electric signal transmission requirement between devices connected through the chip on film is met.
The embodiment of the invention provides a chip on film, which is provided with a first bonding area BA1, a second bonding area BA2 and a wiring area LA clamped between the first bonding area BA1 and the second bonding area BA 2. The chip on film includes a mother substrate 100 and a first patterned conductive layer 310.
A mother substrate 100. The mother substrate 100 may include one or more layers. The mother substrate 100 may include a flexible organic material layer, such as a polyimide-based resin layer. The mother substrate 100 may further include an inorganic material layer, such as a silicon oxide layer, a silicon nitride layer.
The first patterned conductive layer 310 is located on the mother substrate 100 and has a first pattern, the first patterned conductive layer 310 includes a first patterned seed layer 311 and a first patterned metal layer 312, the first patterned seed layer 311 is located on the mother substrate 100 and has the first pattern, the first patterned metal layer 312 is located on a side of the first patterned seed layer 311 facing away from the mother substrate 100 and has the first pattern, and an orthogonal projection of the first patterned seed layer 311 on the mother substrate 100 overlaps an orthogonal projection of the first patterned metal layer 312 on the mother substrate 100.
In some optional embodiments, the chip on film according to the embodiment of the present invention further includes a second patterned conductive layer 510 and a planarization layer 600.
The second patterned conductive layer 510 is located between the mother substrate 100 and the first patterned conductive layer 310 and has a second pattern, the second patterned conductive layer 510 includes a second patterned seed layer 511 and a second patterned metal layer 512, the second patterned seed layer 511 is located on the mother substrate 100 and has the second pattern, the second patterned metal layer 512 is located on a side of the second patterned seed layer 511 facing away from the mother substrate 100 and has the second pattern, and an orthogonal projection of the second patterned seed layer 511 on the mother substrate 100 overlaps an orthogonal projection of the second patterned metal layer 512 on the mother substrate 100.
The planarization layer 600 is located between the second patterned conductive layer 510 and the first patterned conductive layer 310, a connection hole 610 is formed on a surface of the planarization layer 600 facing away from the mother substrate 100, at least a portion of the second patterned conductive layer 510 is exposed by the connection hole 610, and at least a portion of the first patterned conductive layer 310 extends to the connection hole 610 to be electrically connected to at least a portion of the second patterned conductive layer 510.
The flip chip film of the embodiment of the invention can be prepared by the manufacturing method of the flip chip film of the embodiment of the invention.
In accordance with the above-described embodiments of the present invention, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (15)

1. A method for manufacturing a Chip On Film (COF) comprises:
providing a mother substrate;
sequentially forming a first seed layer and a first light resistance layer on the mother substrate;
patterning the first photoresist layer to form a first intermediate substrate with a first patterned photoresist layer and a first hollow area, wherein at least part of the first seed layer is exposed by the first intermediate substrate through the first hollow area;
forming a first metal layer on the first seed layer exposed in the first hollow area;
and removing the first patterned photoresist layer and the first seed layer which is not covered by the first metal layer in the first hollow-out area to form an initial conductive substrate with a first patterned conductive layer, wherein the initial conductive substrate is divided into a first binding area, a second binding area and a wiring area clamped between the first binding area and the second binding area in a first direction.
2. The method of claim 1, further comprising, after the step of providing the mother substrate and before the step of sequentially forming the first seed layer and the first photoresist layer on the mother substrate: forming an intermediate wiring layer on the mother substrate;
the step of sequentially forming a first seed layer and a first photoresist layer on the mother substrate includes: and sequentially forming the first seed layer and the first photoresist layer on the intermediate wiring layer.
3. The method of manufacturing a chip on film as claimed in claim 2, wherein the step of forming an intermediate wiring layer on the mother substrate comprises:
forming a second seed layer and a second light resistance layer on the mother substrate in sequence;
patterning the second photoresist layer to form a second intermediate substrate with a second patterned photoresist layer and a second hollow area, wherein at least part of the second seed layer is exposed by the second intermediate substrate through the second hollow area;
forming a second metal layer on the second seed layer exposed by the second hollow area;
removing the second patterned photoresist layer and the second seed layer which is not covered by the second metal layer in the second hollow-out area to form a second conductive substrate with a second patterned conductive layer;
and arranging a planarization layer on the second conductive substrate, wherein the planarization layer fills gaps among the conductors in the second patterned conductive layer.
4. The method for manufacturing a chip on film as claimed in claim 3, wherein the step of forming the intermediate wiring layer on the mother substrate further comprises, after the step of providing the planarization layer on the second conductive substrate:
and forming a connecting hole on the surface of the planarization layer, which is opposite to the mother substrate, wherein at least part of the second patterned conductive layer is exposed through the connecting hole.
5. The method of manufacturing a chip on film as claimed in claim 4, wherein in the step of sequentially forming the first seed layer and the first photoresist layer on the intermediate wiring layer, the first seed layer is formed on the planarization layer and extends to the second patterned conductive layer exposed by the connection hole.
6. The method of claim 1, wherein in the step of forming the first metal layer on the first seed layer exposed at least in the first hollow area, the first metal layer is formed by electroplating or sputtering;
when the first metal layer is formed in an electroplating manner, the first metal layer is only formed on the first seed layer exposed in the first hollow area.
7. The method of claim 3, wherein in the step of forming the second metal layer on the second seed layer exposed at least in the second hollow area, the second metal layer is formed by electroplating or sputtering;
when the second metal layer is formed in an electroplating manner, the second metal layer is only formed on the second seed layer exposed by the second hollow area.
8. The method of claim 1, wherein after the step of removing the first patterned photoresist layer and the first seed layer uncovered by the first metal layer in the first hollow area to form the initial conductive substrate having the first patterned conductive layer, the method further comprises:
and further forming a third metal layer on the first patterned conductive layer of the initial conductive substrate, wherein the third metal layer coats the exposed surface of the first patterned conductive layer so as to form the first conductive substrate with the third patterned conductive layer.
9. The method of claim 8, wherein after the step of removing the first patterned photoresist layer and the first seed layer uncovered by the first metal layer in the first hollow area to form the initial conductive substrate having the first patterned conductive layer, the method further comprises:
and arranging a first protective layer in the wiring area, wherein the first protective layer covers the first patterned conductive layer in the wiring area and fills gaps among the conductors, or the first protective layer covers the third patterned conductive layer in the wiring area and fills gaps among the conductors.
10. The method of claim 8, wherein after the step of removing the first patterned photoresist layer and the first seed layer uncovered by the first metal layer in the first hollow area to form the initial conductive substrate having the first patterned conductive layer, the method further comprises:
and arranging a chip with a lead in the second binding region, and enabling the lead of the chip to be in bonding connection with the first patterned conductive layer or the third patterned conductive layer.
11. The method for manufacturing a chip on film as claimed in claim 10, wherein after the step of disposing the chip having the pins in the second bonding region, the method further comprises:
and filling packaging materials between the chip and the mother substrate, so that the packaging materials cover the connected pins and the first patterned conductive layer or cover the connected pins and the third patterned conductive layer.
12. The method of manufacturing a chip on film as claimed in claim 11, further comprising, after the step of filling an encapsulation material between the chip and the mother substrate:
and arranging a second protective layer in the second binding region, wherein the second protective layer at least covers the packaging material.
13. The method of claim 1, wherein the step of providing a mother substrate comprises providing a stiffening layer and disposing a flexible substrate on the stiffening layer;
after the step of removing the first patterned photoresist layer and the first seed layer not covered by the first metal layer in the first hollow-out region to form the initial conductive substrate with the first patterned conductive layer, further removing the stiffening layer.
14. A chip on film, comprising:
a mother substrate;
the first patterned conductive layer is located on the mother substrate and provided with a first pattern, the first patterned conductive layer comprises a first patterned seed layer and a first patterned metal layer, the first patterned seed layer is located on the mother substrate and provided with the first pattern, the first patterned metal layer is located on one side, back to the mother substrate, of the first patterned seed layer and provided with the first pattern, and the orthographic projection of the first patterned seed layer on the mother substrate is overlapped with the orthographic projection of the first patterned metal layer on the mother substrate.
15. The chip on film of claim 14, further comprising:
the second patterned conductive layer is positioned between the mother substrate and the first patterned conductive layer and is provided with a second pattern, the second patterned conductive layer comprises a second patterned seed layer and a second patterned metal layer, the second patterned seed layer is positioned on the mother substrate and is provided with the second pattern, the second patterned metal layer is positioned on one side, back to the mother substrate, of the second patterned seed layer and is provided with the second pattern, and the orthographic projection of the second patterned seed layer on the mother substrate is overlapped with the orthographic projection of the second patterned metal layer on the mother substrate;
the planarization layer is positioned between the second patterned conductive layer and the first patterned conductive layer, the surface of the planarization layer, which faces away from the mother substrate, is provided with a connecting hole, at least part of the second patterned conductive layer is exposed by the connecting hole, and at least part of the first patterned conductive layer extends to the connecting hole to be electrically connected with at least part of the second patterned conductive layer.
CN202010460228.4A 2020-05-27 2020-05-27 Chip on film and method for manufacturing the same Pending CN111584436A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010460228.4A CN111584436A (en) 2020-05-27 2020-05-27 Chip on film and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010460228.4A CN111584436A (en) 2020-05-27 2020-05-27 Chip on film and method for manufacturing the same

Publications (1)

Publication Number Publication Date
CN111584436A true CN111584436A (en) 2020-08-25

Family

ID=72125451

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010460228.4A Pending CN111584436A (en) 2020-05-27 2020-05-27 Chip on film and method for manufacturing the same

Country Status (1)

Country Link
CN (1) CN111584436A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113038724A (en) * 2021-03-02 2021-06-25 微智医疗器械有限公司 Manufacturing method of circuit board, circuit board and electronic equipment

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWM269571U (en) * 2004-12-27 2005-07-01 Advanced Semiconductor Eng Multi-chip-on-film package and the flexible multi-layer wiring board for the same
CN1988765A (en) * 2005-12-20 2007-06-27 新光电气工业株式会社 Method of manufacturing flexible wiring substrate and method of manufacturing electronic component mounting structure
JP2009071066A (en) * 2007-09-13 2009-04-02 Sumitomo Metal Mining Package Materials Co Ltd Chip on film (cof) wiring substrate and manufacturing method of the same
CN107645824A (en) * 2016-07-22 2018-01-30 Lg伊诺特有限公司 Flexible PCB, chip on film module and the electronic equipment including flexible PCB
CN108962761A (en) * 2018-06-05 2018-12-07 信利半导体有限公司 A kind of COF preparation method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWM269571U (en) * 2004-12-27 2005-07-01 Advanced Semiconductor Eng Multi-chip-on-film package and the flexible multi-layer wiring board for the same
CN1988765A (en) * 2005-12-20 2007-06-27 新光电气工业株式会社 Method of manufacturing flexible wiring substrate and method of manufacturing electronic component mounting structure
JP2009071066A (en) * 2007-09-13 2009-04-02 Sumitomo Metal Mining Package Materials Co Ltd Chip on film (cof) wiring substrate and manufacturing method of the same
CN107645824A (en) * 2016-07-22 2018-01-30 Lg伊诺特有限公司 Flexible PCB, chip on film module and the electronic equipment including flexible PCB
CN108962761A (en) * 2018-06-05 2018-12-07 信利半导体有限公司 A kind of COF preparation method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113038724A (en) * 2021-03-02 2021-06-25 微智医疗器械有限公司 Manufacturing method of circuit board, circuit board and electronic equipment

Similar Documents

Publication Publication Date Title
US7608929B2 (en) Electrical connector structure of circuit board and method for fabricating the same
US7674362B2 (en) Method for fabrication of a conductive bump structure of a circuit board
US5977641A (en) Semiconductor device and method for manufacturing the same
US7973397B2 (en) Package substrate having embedded semiconductor chip and fabrication method thereof
KR100818088B1 (en) Semiconductor package and method of fabricating the same
US6806176B2 (en) Semiconductor device and method of manufacturing the same, circuit board and electronic instrument
EP0377932A2 (en) Package of semiconductor integrated circuits
EP0145862B1 (en) Metallization of a ceramic substrate
CN101548378A (en) Semiconductor device and manufacturing method thereof
KR100609011B1 (en) Wafer level module and fabricating method thereof
JP2019179831A (en) Wiring board and method for manufacturing wiring board
CN102214628B (en) Package substrate and fabricating method thereof
KR100452820B1 (en) Method of defining electrode for circut device, and chip package and multilayer board using that
CN108811301B (en) Circuit board structure and manufacturing method thereof
WO2019007082A1 (en) Chip encapsulation method
EP3291285A1 (en) Semiconductor package structure with a polymer gel surrounding solders connecting a chip to a substrate and manufacturing method thereof
CN111584436A (en) Chip on film and method for manufacturing the same
KR100452818B1 (en) Chip scale package and method of fabricating the same
CN112352305B (en) Chip packaging structure and chip packaging method
JP2006287094A (en) Semiconductor apparatus and manufacturing method therefor
CN104425421B (en) Chip package and forming method thereof
JP2001244366A (en) Semiconductor integrated circuit device and its manufacturing method
JP7230462B2 (en) Semiconductor device and its manufacturing method
JP3378880B2 (en) Semiconductor device and manufacturing method thereof
CN111081693B (en) Light emitting assembly packaging structure and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20200825

RJ01 Rejection of invention patent application after publication