JP3378880B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a marking and a manufacturing method thereof.

[0002]

2. Description of the Related Art Markings are formed on a semiconductor device in order to externally recognize a product number, a lot number, etc. after the semiconductor device is completed. Conventionally, a semiconductor device containing elements such as transistors is formed on a wafer and divided into semiconductor chips, and after a wiring pattern is formed on the divided semiconductor chips, an ink printing method or a laser irradiation method is used. To form the marking.

[0003]

However, according to the above conventional marking, after the semiconductor device is completed,
Since it requires a dedicated marking process that performs ink printing and laser irradiation for each semiconductor device,
There is a problem that the number of manufacturing steps increases. In addition, equipment for marking, such as an ink printer or a laser irradiation device, is required, which increases equipment cost.

In view of the above conventional problems, it is an object of the present invention to provide a semiconductor device having a marking formed therein and a method of manufacturing the same without the need for a step or device dedicated to the marking.

[0005]

Semi conductor arrangement of the present invention According to an aspect of the
Formed on the main surface of the semiconductor chip and the semiconductor chip
The low modulus and low modulus layer, the main surface of the semiconductor chip that
A wiring pattern made of a metal layer provided over the elastic layer, and the metal layer is patterned on the low elastic modulus layer.
Formed simultaneously with the wiring pattern by
It has markings for external recognition after completion.

As a result, since the marking is made of the same material as the wiring pattern, it is possible to obtain a semiconductor device having the marking without using equipment for marking such as an ink printer. Therefore, the equipment cost and the number of manufacturing steps can be reduced.

[0007] before Symbol marking, shows the attributes of semiconductor equipment
In accordance with the user's request, it is at least one of a mark indicating a wiring pattern number , a mark indicating a wiring pattern number , an alignment mark for the semiconductor device, and an alignment mark for aligning the semiconductor device. It becomes possible to display the product type.

[0008] By the components each 0.2mm or more magnitude of markings, it can easily recognize the marking to the naked eye after completion.

[0009] By a portion of wiring pattern further comprises a structure that serves as an external electrode terminal for inputting and outputting signals to the outside of the semiconductor device, is required to be formed separately from the external electrode terminals and the wiring pattern Therefore, the number of manufacturing steps of the semiconductor device can be further reduced.

[0010] further comprising a protruding electrode on the external electrode terminal
As a result, signals can be input and output more reliably between the semiconductor device and the outside via the protruding electrodes.

[0011] is formed so as to cover the portion other than the portion consisting of the external electrode terminals and marking on the main surface, by further comprising a protective film made of an insulating material, the input and output of signals with the outside on the main surface Since the wiring pattern other than the related portion is protected by the protective film and the marking is easily recognized, a semiconductor device having high reliability and a marking recognition function can be obtained.

[0012] is formed in the principal surface so as to cover the other portions of the external electrode terminals, by further comprising a transparent resin layer made of an insulating material, irrelevant portions for input and output of signals with the outside on the main surface Is protected by the transparent resin layer, and the marking is easily recognized through the transparent resin layer, so that a semiconductor device having high reliability and a high recognition function of the marking can be obtained.

[0013] Of the external electrode terminals consisting of a part of the wiring pattern, by having different shapes or sizes are predetermined external electrode terminals and the other external electrode terminal, a predetermined external electrode terminal is recognized, the Since it is not necessary to separately form a marking for indicating a predetermined external electrode terminal, the number of manufacturing steps of the semiconductor device can be further reduced.

The method of manufacturing a semi-conductor device of the present invention, the electrode
The electrode is exposed on the main surface of the semiconductor chip.
Forming a low elastic modulus layer having an opening so that
Metal over the main surface of the conductor chip and the low elastic modulus layer
Forming a layer and patterning the metal layer.
With the main surface of the semiconductor chip and the low elastic modulus layer
At the same time forming a wiring pattern over the top, low elasticity
Forming a marking on the index layer .

According to this method, the marking can be formed by using the same material as the wiring pattern without using the marking dedicated equipment such as an ink printer, so that the equipment cost and the manufacturing man-hour can be reduced. .

[0016] In the step of forming a wiring pattern and marking, to form the external electrode terminals for input and output signals to the outside of the semiconductor device in a part of the wiring pattern
As a result, it is not necessary to form the external electrode terminals separately from the wiring pattern, so that the manufacturing process is simplified.

[0017] By providing the step of further forming a projecting electrode on the external electrode terminal, since through the protruding electrodes can electrically connect the semiconductor device and the outside, can manufacture a highly reliable semiconductor device It

As the marking, the attributes of the semiconductor device
And the mark indicating the wiring pattern number
At least one of the alignment marks is formed.
be able to.

[0019]

DETAILED DESCRIPTION OF THE INVENTION (First Embodiment) A semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a perspective view showing a semiconductor device according to this embodiment. In FIG. 1, a semiconductor chip 10 is a semiconductor element having a low elastic modulus layer 20 on its main surface. The low elastic modulus layer 20 is made of a material having a low elastic modulus and an insulating property, and is an insulating layer for covering a portion other than a chip electrode (not shown) on the main surface of the semiconductor chip 10. The pad 30 is an electrode arranged in the opening of the low elastic modulus layer 20 and connected to the chip electrode. The metal wiring 31 includes the semiconductor chip 10 and the low elastic modulus layer 2
0 over the pad 30 and the land 32.
This is a pattern for connecting and. The land 32 is an external electrode terminal formed on the low elastic modulus layer 20 and for inputting / outputting a signal to / from the outside of the semiconductor chip 10.
The pad 30, the metal wiring 31, and the land 32 are made of the same metal layer, and together form a wiring pattern 33. The metal ball 40 is a protruding electrode formed on the land 32. The marking 60 is a mark formed on the main surface of the semiconductor chip 10 and made of the same metal layer as the wiring pattern 33. The mark is capable of externally recognizing at least one of an attribute of the semiconductor device, a wiring pattern number, an alignment mark for the semiconductor device, and an alignment mark for aligning the semiconductor device after completion. With the goal. The attributes of the semiconductor device are, for example, a product number and a lot number of the semiconductor device.

According to this embodiment, the wiring pattern 33 and the marking 60 are formed on the same surface by using the same material. As a result, a semiconductor device having a marking 60 formed by a device for forming the wiring pattern 33 in place of the marking formed by the ink printer or the like dedicated to marking on the completed semiconductor device can be obtained. Therefore, it is possible to reduce the equipment cost and the number of manufacturing steps in manufacturing the semiconductor device.

(Second Embodiment) A semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 2 and 3. 2 and 3, the same components as those in the first embodiment are designated by the same reference numerals as those in FIG. 1, and the description thereof will be omitted. FIG. 2 is a perspective view showing the semiconductor device according to the present embodiment. In FIG. 2, the solder resist 50A is formed on the main surface of the semiconductor chip 10 so as to have an opening at a portion between the marking 60 and a land (not shown) and cover the portion other than the portion between the marking 60 and the land. It is a protective layer.

A method of manufacturing a semiconductor device according to this embodiment will be described with reference to FIGS. Figure 3
(A)-(e) is a process flow chart showing the manufacturing method of the semiconductor device concerning this embodiment by the III-III line section of Drawing 2.

First, as shown in FIG. 3A, a photosensitive insulating material 21 is applied on the chip electrodes 11 and the passivation film 12 respectively formed on the main surface of the semiconductor chip 10 and dried. To do.

Next, as shown in FIG. 3B, the dried insulating material 21 is sequentially exposed and developed to form the low elastic modulus layer 20 in which the chip electrode 11 is opened. . In this case, for example, scattered light, not parallel light, is used for the exposure, and the cross-sectional shape of the low elastic modulus layer 20 in the opening is formed in a tapered shape instead of perpendicular to the chip electrode 11. The insulating material 21 may be a polymer having a low elastic modulus and insulating properties such as low elastic modulus polyimide and epoxy.

Next, as shown in FIG. 3C, on the main surface of the semiconductor chip 10, for example, Ti / is formed by a vacuum deposition method, a sputtering method, a CVD method or an electroless plating method.
After forming the metal thin film layer made of Cu, the metal thin film layer is patterned. As a result, the pad 30 and the metal wiring 3 are formed on the main surface of the semiconductor chip 10.
A predetermined wiring pattern 33 including 1 and a land 32;
The marking 60 is formed at the same time. Wiring pattern 33
Is the number of pads 30, that is, the number of pins and the semiconductor chip 10.
It is decided in consideration of the area and. Patterning
The procedure is as follows. A photosensitive resist is applied on the metal thin film layer, the resist other than a predetermined pattern portion is cured by exposure, and then the resist in the pattern portion is removed. A metal layer having a large film thickness made of, for example, Cu is formed on the pattern portion using electrolytic plating, and then the resist is melted and removed. After that, by immersing in an etching solution to dissolve the metal thin film layer and leave a metal layer having a large film thickness, the predetermined wiring pattern 33 and the marking 60 are simultaneously formed.

A metal film is deposited on the entire main surface, a resist is applied on the metal film, an etching mask resist is formed on a predetermined pattern portion using a photolithography technique, and the resist is used as a mask. Alternatively, the wiring pattern 33 and the marking 60 may be simultaneously formed by etching the metal layer.

Next, as shown in FIG. 3D, after applying a photosensitive solder resist on the low elastic modulus layer 20,
A photolithography technique is used to form the solder resist 50A so that only the land 32 and the marking 60 are exposed. The solder resist 50
By A, the pad 30 and the metal wiring 31, which are portions of the wiring pattern 33 other than the land 32, are protected from the molten solder.

Next, as shown in FIG. 3 (e), solder,
A metal ball 40 made of solder-plated copper, nickel, or the like is placed on the land 32, and the metal ball 40 and the land 32 are melt-bonded. The semiconductor device according to this embodiment can be obtained through the above steps.

In the description of the present embodiment, the insulating material 21 having photosensitivity is applied in order to form the low elastic modulus layer 20, but the present invention is not limited to this, and the photosensitive material formed in advance in a film shape is used. An insulating material having properties may be used.
In this case, the film-shaped insulating material is used as the semiconductor chip 1.
Then, the chip electrode 11 of the semiconductor chip 10 is exposed by exposing and developing it.

Further, an insulating material having no photosensitivity can be used. In this case, the chip electrode 11 of the semiconductor chip 10 is exposed by mechanical processing such as laser or plasma, or chemical processing such as etching.

Although Ti / Cu is used as the metal thin film layer , Cr, W, Cu, Ni or the like may be used instead.

As described above, according to this embodiment, the wiring pattern 33 made of a metal layer is formed on the main surface of the semiconductor chip 10, and at the same time, the marking 60 made of the same metal layer is formed on the main surface. . By this,
It is possible to form the wiring pattern 33 and the marking 60 at the same time without requiring a marking dedicated equipment such as an ink printer and a laser irradiation device that have been conventionally used. Therefore, it is possible to reduce the equipment cost and the number of manufacturing steps in manufacturing the semiconductor device.

(Third Embodiment) A semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. FIG. 4 is a perspective view showing the semiconductor device according to the present embodiment. The same components as those in the first embodiment are designated by the same reference numerals as those in FIG. 1, and the description thereof will be omitted. In FIG. 4, the solder resist 50B is a protective layer made of a transparent resin and formed so as to cover the main surface of the semiconductor chip 10 except the land 32.

According to this embodiment, the wiring pattern 33 and the marking 60 are formed on the same surface by using the same material. As a result, a semiconductor device having a marking 60 formed by a device for forming the wiring pattern 33 is obtained instead of the marking formed on the semiconductor device by an ink printing machine dedicated to marking or the like in the process after completion. . Therefore, it is possible to reduce the equipment cost and the number of manufacturing steps in manufacturing the semiconductor device. Furthermore,
Since the pad 30, the metal wiring 31, and the marking 60 are protected by the solder resist 50B made of a transparent resin, a highly reliable semiconductor device in which the marking can be easily recognized from the outside can be obtained.

(Fourth Embodiment) A semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 5 is a perspective view showing the semiconductor device according to the present embodiment. In FIG. 5, the low elastic modulus layer 20 is an insulating layer that is formed flat so that the central portion of the main surface of the semiconductor chip 10 is raised. The wiring pattern 33 is a wiring formed of a metal layer formed over the main surface of the semiconductor chip 10 and the low elastic modulus layer 20, and is connected to the chip electrode 11 of the semiconductor chip 10. The land 32 is a portion of the wiring pattern 33 that is present on the low elastic modulus layer 20, and is a portion that is not covered by a solder resist (not shown), that is, an exposed portion. The marking 60 is formed on the main surface of the semiconductor chip 10, is made of the same material as the wiring pattern 33, and has a product number after the semiconductor device is completed.
It is a mark for externally recognizing the attributes of the semiconductor device, such as the lot number, the wiring pattern number, the alignment mark and the like. The wiring pattern 33 and the marking 60 are
It is formed similarly to the first embodiment. In this embodiment, since the wiring pattern 33 is not fine, the wiring pattern 33 and the marking 60 can be formed by the ink printing method.

According to this embodiment, in the semiconductor device in which the wiring pattern 33 is formed on the low elastic modulus layer 20 formed flat so as to swell the central portion, the wiring is formed on the main surface of the semiconductor chip 10. The marking 60 made of the same metal layer as the pattern 33 is formed. As a result, a semiconductor device having a marking 60 formed by a device for forming the wiring pattern 33 in place of the marking formed by the ink printer or the like dedicated to marking on the completed semiconductor device can be obtained. Therefore, it is possible to reduce the equipment cost and the number of manufacturing steps in manufacturing the semiconductor device.

(Fifth Embodiment) A semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIG. 6A and 6B are plan views showing an example of the semiconductor device according to the present embodiment. The same constituent elements as those in the fourth embodiment are designated by the same reference numerals as those in FIG. 5, and the description thereof will be omitted. In FIGS. 6A and 6B, the special lands 34A,
34B is a predetermined external electrode terminal formed of, for example, the first pin, which is to be displayed separately from the land 32 in the semiconductor device. Each of the special lands 34A and 34B is a part of the wiring pattern 33, and is formed of the same material as the land 32 at the same time. The solder resist 50C is
In the central portion of the main surface of the semiconductor device, each land 32,
These are protective films opened to expose the special lands 34A and 34B, respectively.

FIG. 6A shows an example in which each land 32 has a square shape, and the special land 34A has a shape in which one of the vertices of the square is rounded. In this case, in the photomask for resist exposure used in the patterning for forming the wiring pattern 33, the pattern of the photomask is formed so that the special land 34A has a shape in which one of the square vertices is rounded. To do.

FIG. 6B shows the land 32 and the special land 3.
4B is a square, and the special land 34B is larger than the land 32. In this case, in the photomask for resist exposure used in the patterning for forming the wiring pattern 33, the special land 34B is used.
The pattern of the photomask is created so that is larger than the land 32.

According to the present embodiment, the land 32 and the special lands 34A and 34B are simultaneously formed of the same material on the low elastic modulus layer 20 formed flat so as to swell the central portion. . Special land 34A, 34
Since each B has a different shape and size from the land 32, a predetermined special land composed of, for example, pin 1 can be easily recognized from the outside after the semiconductor device is completed.
As a result, a marking for recognizing a predetermined special land can be formed at the same time when the wiring pattern is formed without using a marking-dedicated equipment such as an ink printer depending on the shape or size of the special land itself. Therefore,
It is possible to reduce the equipment cost and the number of manufacturing steps in manufacturing a semiconductor device.

In the above description, the shape of the special land is a shape in which one vertex of a square is rounded or the special land itself is large, but the shape is not limited to this and may be another shape. The land itself may be made smaller.

(Other Embodiments) Instead of each of the above embodiments, a plurality of semiconductor chips included in one wafer are collectively formed with a marking and a wiring pattern on the main surface, or a special land is formed. You may form the wiring pattern which has. This can significantly reduce the number of steps for forming markings on a plurality of semiconductor chips included in one wafer. In this case, the wiring pattern and the marking may be formed using any of plating, photolithography, and ink printing.

In each of the embodiments described above,
Predetermined wiring pattern 33 and marking 60 on the main surface
Instead of being formed simultaneously using the same material, and may be formed by successive plating steps using different metals.

The marking 60 preferably has a size of 0.2 mm or more. By this,
After the semiconductor device is completed, the marking 60 can be recognized from the outside by the device, and the marking 60 can be easily recognized from the outside with the naked eye.

As the attributes of the semiconductor device to be marked, in addition to the product number and the lot number, the type of the semiconductor device, product name, performance rank, manufacturer name, logotype, trademark, country of origin, and compatible standards. Etc. are included.

Further, the place where the marking is formed may be any main surface of the semiconductor device, and the color of the marking is not particularly limited.

[0047]

The semiconductor device of the present invention or the method of manufacturing the same is provided.
According to this, since the wiring pattern and the marking made of the same material are provided on the main surface of the semiconductor device, respectively, the marking is formed on the same surface as the wiring pattern, without requiring a dedicated marking device and process. A semiconductor device is realized. Therefore, Ru can reduce the equipment cost and manufacturing man-hours in the manufacture of a semiconductor device.

[Brief description of drawings]

FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a perspective view showing a semiconductor device according to a second embodiment of the present invention.

3A to 3E are process flow diagrams showing a method of manufacturing the semiconductor device of FIG. 2 by a cross section taken along line III-III of FIG.

FIG. 4 is a perspective view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a perspective view showing a semiconductor device according to a fourth embodiment of the present invention.

6A and 6B are plan views showing an example of a semiconductor device according to a fifth embodiment of the present invention.

[Explanation of symbols]

10 semiconductor chips 11 Chip electrode 12 passivation film 20 Low elastic modulus layer 21 Insulation material 30 pads 31 metal wiring 32 lands (external electrode terminal) 33 wiring pattern 34A, 34B Special land (external electrode terminal) 40 metal balls (protruding electrodes) 50A, 50C Solder resist (protective film) 50B Solder resist (transparent resin layer) 60 markings

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yoshifumi Nakamura Inventor, Yoshifumi Nakamura 1-1, Sachimachi, Takatsuki City, Osaka Prefecture (56) References JP-A-9-180973 (JP, A) 1-67752 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 23/00

Claims (12)

(57) [Claims] 1. A semiconductor chip, a low elastic modulus layer formed on a main surface of the semiconductor chip, and a main surface of the semiconductor chip and the low elastic modulus layer.
A wiring pattern made of a metal layer provided Te, on the low elastic modulus layer, patterning the metal layer
Accordingly , a semiconductor device is provided , which is formed at the same time as the wiring pattern and has a marking for external recognition after completion. 2. The semiconductor device according to claim 1, wherein the marking includes a mark indicating an attribute of a semiconductor device, a mark indicating a wiring pattern number , an alignment mark for the semiconductor device, and the semiconductor device. A semiconductor device characterized by being at least one of an alignment mark for alignment. 3. The semiconductor device according to claim 1, wherein each of the components of the marking has a size of 0.2 mm or more. 4. The semiconductor device according to claim 1, wherein a part of the wiring pattern functions as an external electrode terminal for inputting / outputting a signal to / from the outside of the semiconductor device. A semiconductor device characterized by the above. 5. The semiconductor device according to claim 4, further comprising a protruding electrode on the external electrode terminal. 6. The semiconductor device according to claim 4 or 5, wherein a protective film made of an insulating material is formed on the main surface so as to cover a portion other than a portion including the external electrode terminals and the marking. A semiconductor device further comprising: 7. The semiconductor device according to claim 4, further comprising a transparent resin layer formed of an insulating material on the main surface so as to cover portions other than the external electrode terminal portion. A semiconductor device characterized by: 8. The semiconductor device according to claim 4, wherein among the external electrode terminals, a predetermined external electrode terminal has a different shape or size from other external electrode terminals. apparatus. 9. A main surface of a semiconductor chip having electrodes,
Form a low elastic modulus layer that is opened to expose the electrodes.
And a step of forming the main surface of the semiconductor chip and the low elastic modulus layer.
Forming a metal layer by patterning the metal layer and patterning the metal layer
A wiring pattern extending over the main surface of the chip and the low elastic modulus layer.
Marking on the low modulus layer at the same time as forming
And a step of forming a semiconductor device. A method of manufacturing a semiconductor device, which comprises continuously performing the step of forming the marking and the step of forming the marking. 10. The method of manufacturing a semiconductor device according to claim 9 , wherein in the step of forming the wiring pattern and the marking ,
A method of manufacturing a semiconductor device, comprising forming an external electrode terminal for inputting / outputting a signal to / from the outside of the semiconductor device in a part of the wiring pattern. 11. The method of manufacturing a semiconductor device according to claim 10 , further comprising the step of forming a protruding electrode on the external electrode terminal. 12. The method according to any one of claims 9 to 11.
In the method for manufacturing a semiconductor device described above, As the marking, a mark indicating the attribute of the semiconductor device
And a mark showing the wiring pattern number and an alignment mark
Forming at least any one of
Of manufacturing a semiconductor device.