JP2009071066A - Chip on film (cof) wiring substrate and manufacturing method of the same - Google Patents

Chip on film (cof) wiring substrate and manufacturing method of the same Download PDF

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JP2009071066A
JP2009071066A JP2007238407A JP2007238407A JP2009071066A JP 2009071066 A JP2009071066 A JP 2009071066A JP 2007238407 A JP2007238407 A JP 2007238407A JP 2007238407 A JP2007238407 A JP 2007238407A JP 2009071066 A JP2009071066 A JP 2009071066A
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wiring
plating
cof
nickel
nickel plating
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JP5061805B2 (en
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Hiroki Hata
宏樹 秦
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Sumitomo Metal Mining Package Materials Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a COF wiring substrate not including a nickel-plated layer at the side surface of the wiring part. <P>SOLUTION: The COF wiring substrate is constituted by forming a wiring pattern with an additive method or semi-additive method using a base material that is formed by sequentially laminating a seed layer and a conductive layer on the front surface of an insulating film. The side surface of each wiring constituting the wiring pattern is not provided with the nickel-plated layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、各種電気機器に使用する半導体パッケージ用配線基板、特に液晶ディスプレイ、液晶TVなどに使用されるCOF(Chip On Film)配線基板とその製造方法に関する。   The present invention relates to a semiconductor package wiring board used for various electric devices, particularly a COF (Chip On Film) wiring board used for a liquid crystal display, a liquid crystal TV, and the like, and a method for manufacturing the same.

TABテープを用いたテープキャリアの一つにCOF配線基板がある。このCOF配線基板は、ポリイミドフィルム等の絶縁性フィルムの上に金属配線が形成された薄型フィルム基板であり、主として液晶ディスプレイのドライバIC用半導体パッケージの配線材料として用いられる。
このCOF配線基板の製造方法には、サブトラクティブ法やアディティブ法、セミアディティブ法がある。
One of the tape carriers using TAB tape is a COF wiring board. This COF wiring board is a thin film board in which a metal wiring is formed on an insulating film such as a polyimide film, and is mainly used as a wiring material for a semiconductor package for a driver IC of a liquid crystal display.
The COF wiring board manufacturing method includes a subtractive method, an additive method, and a semi-additive method.

例えば、特許文献1を引用してテープキャリアの製造方法を説明すると、先ず、ポリイミドテープなどの絶縁基板の表面に、下地となる第1導体の薄膜を形成する。この場合、前記第1導体には、主に、ニッケル・銅(Ni-Cu)合金あるいはニッケル・クロム(Ni-Cr)合金の如きニッケル合金が用いられ、スパッタリングにより厚さが50nmから400nm程度になるように形成するか、または、前記ニッケル合金以外にも、例えば、スパッタリングによる銅あるいは銅合金の薄膜などが用いられる。   For example, a method for manufacturing a tape carrier will be described with reference to Patent Document 1. First, a thin film of a first conductor serving as a base is formed on the surface of an insulating substrate such as a polyimide tape. In this case, a nickel alloy such as a nickel-copper (Ni-Cu) alloy or a nickel-chromium (Ni-Cr) alloy is mainly used for the first conductor, and the thickness is about 50 nm to 400 nm by sputtering. In addition to the nickel alloy, for example, copper or a thin film of copper alloy by sputtering is used.

次に、前記第1導体(ニッケル合金)上に、導体パターンを形成する部分が開口するようにレジスト(めっきレジスト)を形成する。前記めっきレジストは、感光性のドライフィルムを用いてパターンを露光、現像する写真法、あるいはスクリーン版を用いてレジストインクを印刷して硬化させる印刷法などにより形成する。   Next, a resist (plating resist) is formed on the first conductor (nickel alloy) so that a portion for forming a conductor pattern is opened. The plating resist is formed by a photographic method in which a pattern is exposed and developed using a photosensitive dry film, or a printing method in which a resist ink is printed and cured using a screen plate.

次に、前記第1導体(ニッケル合金)上の前記めっきレジストに覆われていない部分に、第2導体を形成する。前記第2導体は、主に、前記第1導体(ニッケル・銅合金)を陰極とした電解銅めっきにより形成される。またこのとき、実際の前記第2導体(電解銅めっき)の厚さは、前記第1導体(ニッケル合金)の厚さに比べて十分に厚く、例えば、10μm程度の厚さになるように形成する。   Next, a second conductor is formed on a portion of the first conductor (nickel alloy) that is not covered with the plating resist. The second conductor is mainly formed by electrolytic copper plating using the first conductor (nickel / copper alloy) as a cathode. At this time, the actual thickness of the second conductor (electrolytic copper plating) is sufficiently larger than the thickness of the first conductor (nickel alloy), for example, about 10 μm. To do.

次に、前記めっきレジストを除去した後、前記第1導体(ニッケル・銅合金)の不要な部分、言い換えると、前記第2導体(電解銅めっき)が形成されていない部分をエッチングにより除去することにより、おのおのが電気的に独立した配線が形成される。前記第1導体(ニッケル・銅合金)のエッチング処理では、例えば、塩化第二鉄(FeCl3)を水に溶解した塩化第二鉄溶液や、塩化第二銅(CuCl2・2H2O)を水に溶解し、適量の塩酸を加えた塩化第二銅溶液をエッチング液として使用する。
この場合、実際の前記第1導体(ニッケル・銅合金)の厚さは、前記第2導体の厚さに比べて非常に薄く、短時間で除去することができるため、特別なエッチングレジストは用いずにクイックエッチングする場合が多い。
Next, after removing the plating resist, unnecessary portions of the first conductor (nickel / copper alloy), in other words, portions where the second conductor (electrolytic copper plating) is not formed are removed by etching. Thus, wirings that are electrically independent from each other are formed. In the etching process of the first conductor (nickel / copper alloy), for example, a ferric chloride solution in which ferric chloride (FeCl 3 ) is dissolved in water or a cupric chloride (CuCl 2 · 2H 2 O) is used. A cupric chloride solution dissolved in water and added with an appropriate amount of hydrochloric acid is used as an etching solution.
In this case, the actual thickness of the first conductor (nickel / copper alloy) is very thin compared to the thickness of the second conductor and can be removed in a short time. Therefore, a special etching resist is used. In many cases, quick etching is performed.

そして半導体素子との接合のため、前記配線にニッケルめっき、金めっきを施す際には、エッチングにより前記第1導体を溶解除去して配線を形成した後に、配線の上面と側面とにニッケルめっきを施し、その上に金めっきを施すことが行われてきている。
特開2003−37137号公報
Then, when nickel plating or gold plating is applied to the wiring for bonding to a semiconductor element, the first conductor is dissolved and removed by etching to form the wiring, and then the nickel plating is applied to the upper and side surfaces of the wiring. It has been practiced to apply gold plating thereon.
JP 2003-37137 A

近年、COF配線基板に設けられる配線に対して一層の微細化が求められるようになってきた。また、配線の断面形状に対してもより正しい矩形であることが求められるようになってきた。これに伴い、前記ニッケルめっきと金めっきに関しても、配線の上面のみに施すことが求められるようになってきた。というのは、ニッケルめっきは配線上面の金めっきがワイヤボンディング、フリップ接続等により銅製の配線へ拡散するのを防止し、ICとの接合時の配線硬度を保つためのもので、配線側面には不要だからである。配線側面までニッケルめっきすることは、不要なニッケルを消費し、過度なニッケルめっきにより配線の屈曲性を損ない、ニッケルめっきの厚みのバラツキが配線幅の寸法のバラツキを大きくするからである。   In recent years, further miniaturization has been required for the wiring provided on the COF wiring board. Further, it has been demanded that the cross-sectional shape of the wiring is a more accurate rectangle. As a result, the nickel plating and the gold plating have been required to be applied only to the upper surface of the wiring. This is because nickel plating prevents the gold plating on the upper surface of the wiring from diffusing into the copper wiring due to wire bonding, flip connection, etc., and keeps the wiring hardness when bonded to the IC. Because it is unnecessary. This is because nickel plating to the side surface of the wiring consumes unnecessary nickel, impairs the flexibility of the wiring due to excessive nickel plating, and the variation in the thickness of the nickel plating increases the variation in the width of the wiring.

しかし、ニッケルめっきを配線の側面には施さず上面のみに施すには、ニッケルめっき時に配線側面をカバーするなどの策が必要であるが、求められる高密度化、微細化をかなえつつこれを行うのは容易でなく、たとえ実施できたとしても大幅なコスト高となるなどの課題があった。   However, in order to apply nickel plating only to the upper surface and not to the side of the wiring, it is necessary to take measures such as covering the side of the wiring during nickel plating, but this is done while achieving the required high density and miniaturization. However, it was not easy, and even if it could be implemented, there was a problem such as a significant increase in cost.

本発明は、上記の課題を解決するためなされたものであり、その目的とするところは、銅配線にニッケルめっきが施されたCOF配線基板において、配線の側面にニッケルめっき層を有さないCOF配線基板とその製造方法を提供することにある。   The present invention has been made to solve the above-described problems, and the object of the present invention is to provide a COF wiring board in which nickel plating is applied to a copper wiring, and a COF having no nickel plating layer on the side surface of the wiring. It is to provide a wiring board and a manufacturing method thereof.

上記課題を解決すべく本願発明者は種々の検討を行った結果、配線形成用めっきレジストを除去する前にニッケルめっきを施せば、前記課題を解決できることを見出し本発明に至った。
すなわち、本発明によるCOF用配線基板は、絶縁性フィルムの表面にシード層が設けられ、このシード層の上に導電層が設けられた基材を用いて、アディティブ法又はセミアディティブ法により配線パターンが設けられたCOF用配線基板であって、配線パターンを構成する各配線の側面にニッケルめっき層を有さないことを特徴とする。
As a result of various studies by the inventors of the present invention to solve the above-mentioned problems, the present inventors have found that the above-mentioned problems can be solved by performing nickel plating before removing the wiring forming plating resist.
That is, the wiring board for COF according to the present invention has a wiring pattern by an additive method or a semi-additive method using a base material in which a seed layer is provided on the surface of an insulating film and a conductive layer is provided on the seed layer. The COF wiring board is provided with a nickel plating layer on the side surface of each wiring constituting the wiring pattern.

そして、本発明によるCOF配線基板の製造方法は、前記基材の表面にレジスト層を設け、所定の配線パターンを有するマスクを用いてレジスト層を露光し、現像して開口部が配線パターンとなるめっき用マスクを得、次いで、電気銅めっき法により配線パターンを形成し、次いで、めっき用マスクを除去することなく、ニッケルめっきを施し、その後めっき用マスクを除去し、配線に金メッキを施すようにしたものである。   Then, in the method for manufacturing a COF wiring board according to the present invention, a resist layer is provided on the surface of the substrate, the resist layer is exposed using a mask having a predetermined wiring pattern, and developed to form a wiring pattern. A plating mask is obtained, and then a wiring pattern is formed by an electrolytic copper plating method. Next, nickel plating is performed without removing the plating mask, and then the plating mask is removed and the wiring is plated with gold. It is what.

そして、本発明によれば、上記ニッケルめっきは、好ましくは、電解ニッケルめっき及び/又は無電解ニッケルめっきである。   According to the present invention, the nickel plating is preferably electrolytic nickel plating and / or electroless nickel plating.

本発明によれば、配線形成用の感光性レジストをニッケルめっきの側面めっき防止用にも使うことで、何ら特別な工程を加えることなく、容易に精度よく配線上面だけにニッケルめっきを施すことができる。これにより、配線幅の寸法精度は、ニッケルめっきの厚みのバラツキに全く影響されない。また、硬度の高いニッケルめっきを配線全体には施さないので、配線の屈曲性もより良好となり、ニッケル自体の使用量も減らすことができる。その結果、配線部分に高精度なニッケル金めっきの施された、より安価なCOF基板の製造が容易となる。   According to the present invention, by using the photosensitive resist for forming the wiring also for the side plating prevention of the nickel plating, it is possible to easily apply the nickel plating only to the upper surface of the wiring without adding any special process. it can. Thereby, the dimensional accuracy of the wiring width is not affected at all by the variation in the thickness of the nickel plating. Further, since the nickel plating with high hardness is not applied to the entire wiring, the flexibility of the wiring becomes better and the amount of nickel itself can be reduced. As a result, it is easy to manufacture a cheaper COF substrate in which the wiring portion is subjected to highly accurate nickel gold plating.

以下、本発明による配線基板の製造方法の一実施例を図1を用いて説明する。
先ず、図1(1)に示すように、絶縁性フィルム上にスパッタ法にてシード層を形成する。絶縁性フィルムとしては、ポリイミドフィルムやポリアミドフィルムが使用でき、ポリイミドとしては、東レデュポン社製のカプトン、宇部興産製のユーピレックス、カネカ製のアピカルなど一般的なポリイミドフィルムが使用可能である。シード層の材質としては、ニッケル−クロム合金等の如き絶縁性フィルムとの密着性が良好で、耐食性などに優れたものが選択される。次に図1(2)に示すように、シード層の表面全面に銅などの導電層を形成する。
An embodiment of a method for manufacturing a wiring board according to the present invention will be described below with reference to FIG.
First, as shown in FIG. 1A, a seed layer is formed on an insulating film by a sputtering method. As the insulating film, a polyimide film or a polyamide film can be used, and as the polyimide, a general polyimide film such as Kapton manufactured by Toray DuPont, Upilex manufactured by Ube Industries, or Apical manufactured by Kaneka can be used. As the material for the seed layer, a material having good adhesion to an insulating film such as a nickel-chromium alloy and excellent corrosion resistance is selected. Next, as shown in FIG. 1B, a conductive layer such as copper is formed on the entire surface of the seed layer.

次に、図1(3)に示すように、形成された導電層上に、感光性ドライフィルムレジストあるいは感光性液状レジストで所定のパターンを形成する。この際、最終COF基板の配線部にあたる部分のレジストが除去され開口されるようにパターンを形成する。その配線パターン開口部に、図1(4)に示すように、絶縁性フィルム端部の導電層を通じて通電し、銅めっきにて配線を形成する。さらに、図1(5)に示すように、この配線上に所定の厚みのニッケルめっきを電解めっきあるいは無電解めっきにて施す。ニッケルめっきの厚みとしては、0.1〜1.0μm程度が望ましいが、後のシード層除去時にニッケルが溶解する場合は、あらかじめ所定の厚みより、その溶解分だけ厚みを厚くめっきをしておく。   Next, as shown in FIG. 1 (3), a predetermined pattern is formed on the formed conductive layer with a photosensitive dry film resist or a photosensitive liquid resist. At this time, the pattern is formed so that the resist corresponding to the wiring portion of the final COF substrate is removed and opened. As shown in FIG. 1 (4), the wiring pattern opening is energized through the conductive layer at the end of the insulating film, and wiring is formed by copper plating. Further, as shown in FIG. 1 (5), nickel plating having a predetermined thickness is applied to the wiring by electrolytic plating or electroless plating. The thickness of the nickel plating is preferably about 0.1 to 1.0 μm. However, when nickel is dissolved at the time of removing the seed layer later, the thickness is plated in advance by the dissolved amount from the predetermined thickness. .

その後、図1(6)に示すように、感光性レジストを水酸化ナトリウム溶液などにより除去する。レジスト除去後、図1(7)に示すように、銅または銅合金からなる導電層を除去する。次に、図1(8)に示すように、シード層を溶解除去することにより、所定のニッケルめっき付き配線パターンが形成される。   Thereafter, as shown in FIG. 1 (6), the photosensitive resist is removed with a sodium hydroxide solution or the like. After removing the resist, the conductive layer made of copper or copper alloy is removed as shown in FIG. Next, as shown in FIG. 1 (8), a predetermined wiring pattern with nickel plating is formed by dissolving and removing the seed layer.

その後、図1(9)に示すように、配線の全面に電解あるいは無電解めっきにて金めっきを施し、最後に、図1(10)に示すように、所定部分にソルダーレジストをコートして、COF基板を完成する。ソルダーレジストのコートは、金めっき工程の前に行ってもよい。ソルダーレジストとしては、日本ポリテック社製のNPR−3300などが使用できる。   Thereafter, as shown in FIG. 1 (9), the entire surface of the wiring is plated with gold by electrolysis or electroless plating. Finally, as shown in FIG. 1 (10), a solder resist is coated on a predetermined portion. Complete the COF substrate. The solder resist coating may be performed before the gold plating step. As a solder resist, NPR-3300 manufactured by Nippon Polytech Co., Ltd. can be used.

図2は上記の如く形成された配線の拡大断面を、図3は従来法により形成された配線の拡大断面を夫々示しているが、これらの図から明らかなように、本発明方法により形成された配線には、ニッケルめっき層は配線上面にしか施されていない。   2 shows an enlarged cross section of the wiring formed as described above, and FIG. 3 shows an enlarged cross section of the wiring formed by the conventional method. As is apparent from these drawings, the wiring is formed by the method of the present invention. On the other hand, the nickel plating layer is applied only to the upper surface of the wiring.

本発明による配線基板の製造方法の一実施例を示す工程図である。It is process drawing which shows one Example of the manufacturing method of the wiring board by this invention. 本発明方法により形成された配線の拡大断面図である。It is an expanded sectional view of the wiring formed by the method of the present invention. 従来方法により形成された配線の拡大断面図である。It is an expanded sectional view of the wiring formed by the conventional method.

符号の説明Explanation of symbols

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Claims (3)

絶縁性フィルムの表面にシード層と導電層とを順次積層してなる基材を用いて、アディティブ法又はセミアディティブ法により配線パターンを形成してなるCOF用配線基板において、前記配線パターンを構成する各配線の側面にニッケルめっき層を有さないことを特徴とするCOF配線基板。   A wiring board for COF, in which a wiring pattern is formed by an additive method or a semi-additive method using a base material obtained by sequentially laminating a seed layer and a conductive layer on the surface of an insulating film, constitutes the wiring pattern. A COF wiring board having no nickel plating layer on the side surface of each wiring. 絶縁性フィルムの表面にシード層と導電層とレジスト層とを順次積層してなる基材を準備し、所定の配線パターンを有するマスクを用いて前記レジスト層を露光し現像して得られる開口部が配線パターンとなるめっき用マスクを得、次いで、電気銅めっき法により配線パターンを形成し、次いで、めっき用マスクを除去することなくニッケルめっきを施し、その後めっき用マスクを除去し、配線に金メッキを施すことを特徴とするCOF配線基板の製造方法。   An opening obtained by preparing a base material in which a seed layer, a conductive layer, and a resist layer are sequentially laminated on the surface of an insulating film, and exposing and developing the resist layer using a mask having a predetermined wiring pattern Obtain a plating mask that becomes a wiring pattern, then form a wiring pattern by electrolytic copper plating, then apply nickel plating without removing the plating mask, and then remove the plating mask and gold-plat the wiring The manufacturing method of the COF wiring board characterized by performing these. 前記ニッケルめっきが電解ニッケルめっき及び/又は無電解ニッケルめっきである請求項2に記載のCOF配線基板の製造方法。   The method for producing a COF wiring board according to claim 2, wherein the nickel plating is electrolytic nickel plating and / or electroless nickel plating.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111584436A (en) * 2020-05-27 2020-08-25 上海天马微电子有限公司 Chip on film and method for manufacturing the same
WO2020213133A1 (en) * 2019-04-18 2020-10-22 パナソニック・タワージャズセミコンダクター株式会社 Semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59106181A (en) * 1982-12-10 1984-06-19 東洋紙業株式会社 Method of producing printed circuit board
JP2001068828A (en) * 1999-08-27 2001-03-16 Ngk Spark Plug Co Ltd Wiring board and its manufacture
JP2002026172A (en) * 2000-07-07 2002-01-25 Nec Kansai Ltd Flexible wiring board and its manufacturing method
JP2003037206A (en) * 2001-07-24 2003-02-07 Sony Corp Electronic component mounting board and method of manufacturing the same
JP2003037137A (en) * 2001-07-23 2003-02-07 Hitachi Cable Ltd Method of manufacturing wiring substrate and wiring substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59106181A (en) * 1982-12-10 1984-06-19 東洋紙業株式会社 Method of producing printed circuit board
JP2001068828A (en) * 1999-08-27 2001-03-16 Ngk Spark Plug Co Ltd Wiring board and its manufacture
JP2002026172A (en) * 2000-07-07 2002-01-25 Nec Kansai Ltd Flexible wiring board and its manufacturing method
JP2003037137A (en) * 2001-07-23 2003-02-07 Hitachi Cable Ltd Method of manufacturing wiring substrate and wiring substrate
JP2003037206A (en) * 2001-07-24 2003-02-07 Sony Corp Electronic component mounting board and method of manufacturing the same

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WO2020213133A1 (en) * 2019-04-18 2020-10-22 パナソニック・タワージャズセミコンダクター株式会社 Semiconductor device
CN111584436A (en) * 2020-05-27 2020-08-25 上海天马微电子有限公司 Chip on film and method for manufacturing the same

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