JP2004146757A - Wiring board and method for manufacturing the wiring board - Google Patents

Wiring board and method for manufacturing the wiring board Download PDF

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Publication number
JP2004146757A
JP2004146757A JP2002348621A JP2002348621A JP2004146757A JP 2004146757 A JP2004146757 A JP 2004146757A JP 2002348621 A JP2002348621 A JP 2002348621A JP 2002348621 A JP2002348621 A JP 2002348621A JP 2004146757 A JP2004146757 A JP 2004146757A
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Japan
Prior art keywords
conductor
main surface
frame
area
product
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JP2002348621A
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JP4051273B2 (en
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Hatsuo Ohashi
大橋　初夫
Kenichi Yamanouchi
山之内　健一
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board capable of enhancing the uniformity of the thickness of the main surface conductive layer and the back surface conductive surface in the wiring board which comprises a product part and a frame part, and a method for manufacturing the wiring board. <P>SOLUTION: In a wiring board 101, a conductor area rate in the main surface first frame conductive part 130 is equal to the conductor area rate of the main surface product conductive part 127, and the conductor area rate of the back surface first frame conductive part 150 is equal to the conductor area rate of the back surface product conductive part 147. Further, since the conductor area rate of the main surface second frame conductive part 131 is greater than the conductor area rate of the back surface product conductive part 147, a conductor area ratio of the back surface side third conductive layer 145 to the main surface side third conductive layer 125 is smaller than the conductor area ratio of the back surface product conductive layer 147 to the main surface product conductive part 127. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、製品部とこの周囲を取り囲む枠部とからなる配線基板及び配線基板の製造方法に関し、特に、主面側と裏面側にそれぞれ導体層が形成された配線基板及び配線基板の製造方法に関する。
【０００２】
【従来の技術】
従来より、製品部とこの周囲を取り囲む枠部とから構成された配線基板が知られている。
例えば、図７に主面９０２側から見た平面図、図８に裏面９０３側から見た平面図を示す配線基板９０１が挙げられる。この配線基板９０１は、コア基板の両面に複数の導体層と絶縁層が交互に積層された多層配線基板であり、略矩形の略板形状をなす。配線基板９０１の平面視略中央には、個々の製品９０５Ｓが複数（７×６＝４２個）繋がった製品部９０５が形成され、この周囲には、後に廃棄される枠部９０７が形成されている。
【０００３】
配線基板９０１の主面９０２側には、図７に概略を示すように、主面導体層９１１が形成されている。この主面導体層９１１は、製品部９０５に形成された主面製品導体部９１３と、枠部９０７に形成された主面枠導体部９１５とからなる。主面製品導体部９１３は、図９に製品部９０５を構成する個々の製品９０５Ｓの主面９０２側から見た平面図を示すように、複数の配線９１３Ｈやパッド９１３Ｐを有するが、その導体面積は比較的小さい。一方、主面枠導体部９１５は、図７に示すように、枠部９０７の略全面に略ベタ状に形成されている。
【０００４】
他方、配線基板９０１の裏面９０３側には、図８に概略を示すように、裏面導体層９３１が形成されている。この裏面導体層９３１は、製品部９０５に形成された裏面製品導体部９３３と、枠部９０７に形成された裏面枠導体部９３５とからなる。裏面製品導体部９３３は、図１０に個々の製品９０５Ｓの裏面９０３側から見た平面図を示すように、略格子状に並んだ多数のパッド９３３Ｐを有するが、その導体面積は、主面製品導体部９１３に比して著しく広い。一方、裏面枠導体部９３５は、図８に示すように、主面枠導体部９１５と同様、枠部９０７の略全面に略ベタ状に形成されている。
なお、このような技術に関連する文献として、例えば、特許文献１が挙げられる。
【０００５】
【特許文献１】
特許第３１７２５０９号公報
【０００６】
【発明が解決しようとする課題】
しかしながら、主面側導体層９１１と裏面側導体層９３１は電解メッキを利用して一緒に形成されるが、主面製品導体部９１３の導体面積が、裏面製品導体部９３３の導体面積よりも小さいために、主面製品導体部９１３の導体層が薄く形成され、裏面製品導体部９３３の導体層がそれよりも厚く形成される傾向にある。これは、メッキ面積が狭いと、電流の流れが悪いためメッキが形成されにくく、メッキ面積が広いと、電流の流れが良いためメッキが形成されやすいことに起因すると考えられる。
【０００７】
また、主面製品導体部９１３のうち主面枠導体部９１５に近い部分（外側部分）は、導体層が薄く形成され、主面製品導体部９１３の中央部分は、導体層がそれよりも厚く形成される傾向にある。これは、主面枠導体部９１５のメッキ面積率は主面製品導体部９１３のメッキ面積率よりも大きいため、主面枠導体部９１５の導体層が主面製品導体部９１３の導体層よりも厚く形成されやすいが、そのとき、主面枠導体部９１５の形成にメッキが多く必要とされるため、主面製品導体部９１３のうち主面枠導体部９１５に近い部分では、メッキが形成されにくくなることに起因すると考えられる。同様な理由から、裏面製品導体部９３３のうち裏面枠導体部９３５に近い部分（外側部分）は、導体層が薄く形成され、主面製品導体部９３３の中央部分は、導体層がそれよりも厚く形成される傾向にある。
このように主面製品導体部９１３と裏面製品導体部９３３で導体層の厚みが異なったり、各導体部内で導体層の厚みに均一性がないと、配線基板９０１の信頼性に劣ることとなる。
【０００８】
本発明は、かかる現状に鑑みてなされたものであって、製品部と枠部とからなる配線基板について、主面導体層と裏面導体層の厚みの均一性を向上させることができる配線基板及び配線基板の製造方法を提供することを目的とする。
【０００９】
【課題を解決するための手段、作用及び効果】
その解決手段は、主面と裏面を有し、製品部とこの製品部の周囲を取り囲む枠部とからなり、上記主面側に形成された主面導体層であって、上記製品部に形成された主面製品導体部と上記枠部に形成された主面枠導体部とからなる主面導体層と、上記裏面側に形成された裏面導体層であって、上記製品部に形成された裏面製品導体部と上記枠部に形成された裏面枠導体部とからなる裏面導体層と、を備え、上記主面製品導体部の導体面積が、上記裏面製品導体部の導体面積よりも小さい配線基板であって、上記主面枠導体部は、上記主面製品導体部を取り囲む主面第１枠導体部と、この主面第１枠導体部よりも外側に位置する主面第２枠導体部とを有し、上記裏面枠導体部は、上記裏面製品導体部を取り囲む裏面第１枠導体部を有し、上記主面第１枠導体部が形成された領域全体の面積に占める上記主面第１枠導体部の導体面積の面積率が、上記製品部の面積に占める上記主面製品導体部の導体面積の面積率と同一とされ、上記裏面第１枠導体部が形成された領域全体の面積に占める上記裏面第１枠導体部の導体面積の面積率が、上記製品部の面積に占める上記裏面製品導体部の導体面積の面積率と同一とされ、上記主面第２枠導体部が形成された領域全体の面積に占める上記主面第２枠導体部の導体面積の面積率が、上記製品部の面積に占める上記裏面製品導体部の導体面積の面積率よりも大きくされることにより、上記主面導体層の導体面積に対する上記裏面導体層の導体面積の割合が、上記主面製品導体部の導体面積に対する上記裏面製品導体部の導体面積の割合よりも小さくされている配線基板である。
【００１０】
本発明は、製品部に形成された主面製品導体部と枠部に形成された主面枠導体部とからなる主面導体層と、製品部に形成された裏面製品導体部と枠部に形成された裏面枠導体部とからなる裏面導体層とを有し、主面製品導体部の導体面積が、裏面製品導体部の導体面積よりも小さい配線基板に適用される。このような配線基板は、上述したように、主面導体層及び裏面導体層の厚みが不均一になりやすいからである。
【００１１】
本発明の配線基板は、主面枠導体部が、主面製品導体部を取り囲む主面第１枠導体部と、この主面第１枠導体部よりも外側に位置する主面第２枠導体部とを有し、一方、裏面枠導体部は、裏面製品導体部を取り囲む裏面第１枠導体部を有する。そして、主面第１枠導体部が形成された領域全体の面積に占める主面第１枠導体部の導体面積の面積率（以下、主面第１枠導体部の導体面積率とも言う。）が、製品部の面積に占める主面製品導体部の導体面積の面積率（以下、主面製品導体部の導体面積率とも言う。）と同一とされている。また、裏面第１枠導体部が形成された領域全体の面積に占める裏面第１枠導体部の導体面積の面積率（以下、裏面第１枠導体部の導体面積率とも言う。）が、製品部の面積に占める裏面製品導体部の導体面積の面積率（以下、裏面製品導体部の導体面積率とも言う。）と同一とされている。
【００１２】
このように、主面製品導体部を取り囲む主面第１枠導体部の導体面積率が、主面製品導体部の導体面積率と同一であれば、主面製品導体部の形成に必要とされる単位面積あたりのメッキ量と、主面第１枠導体部の形成に必要とされる単位面積あたりのメッキ量とがほぼ同じになる。このため、主面製品導体部のうち、主面枠導体部に近い部分（外側部分）とそこから離れた中央部分との間で、従来にみられた導体層の厚みの不均一は生じにくくなり、主面製品導体部の全体にわたり厚みの均一性を向上させることができる。
同様に、裏面製品導体部を取り囲む裏面第１枠導体部の導体面積率が、裏面製品導体部の導体面積率と同一であれば、裏面製品導体部の形成に必要とされる単位面積あたりのメッキ量と、裏面第１枠導体部の形成に必要とされる単位面積あたりのメッキ量とがほぼ同じになる。このため、裏面製品導体部のうち、裏面枠導体部に近い部分とそこから離れた中央部分との間で、従来にみられた導体層の厚みの不均一は生じにくくなり、裏面製品導体部の全体にわたり厚みの均一性を向上させることができる。
【００１３】
さらに、本発明の配線基板では、主面第２枠導体部が形成された領域全体の面積に占める主面第２枠導体部の導体面積の面積率（以下、主面第２枠導体部の導体面積率とも言う。）が、上記の裏面製品導体部の導体面積率よりも大きくされることにより、主面導体層の導体面積に対する裏面導体層の導体面積の割合が、主面製品導体部の導体面積に対する裏面製品導体部の導体面積の割合よりも小さくされている。
【００１４】
このようにすれば、主面導体層の導体面積と裏面導体層の導体面積との差が、従来の配線基板よりも小さくなる。このため、主面導体層と裏面導体層との間で（主面製品導体部と裏面製品導体部との間で）、従来にみられた導体層の厚みの不均一は生じにくくなり、主面導導体層と裏面導体層（主面製品導体部と裏面製品導体部）の厚みの均一性を向上させることができる。
【００１５】
さらに、上記の配線基板であって、前記主面製品導体部の導体面積に対する前記裏面製品導体部の導体面積の割合が、３以上である配線基板において、前記主面導体層の導体面積に対する前記裏面導体層の導体面積の割合が、２以下とされている配線基板とするのが好ましい。
【００１６】
主面製品導体部の導体面積に対する裏面製品導体部の導体面積の割合が、３以上である配線基板では、主面導体層と裏面導体層との間で（主面製品導体部と裏面製品導体部との間で）、特に、導体層の厚みに不均一が生じやすい。
そこで、上述した発明を適用するのが好ましいが、その際、本発明では、主面導体層の導体面積に対する裏面導体層の導体面積の割合を、２以下と小さくしている。このため、主面導体層と裏面導体層との間で（主面製品導体部と裏面製品導体部との間で）、導体層の厚みの均一性をより向上させることができる。
【００１７】
さらに、上記のいずれかに記載の配線基板であって、前記主面枠導体部は、上記配線基板の周縁をなす主面第３枠導体部を有し、前記裏面枠導体部は、上記配線基板の周縁をなす裏面第２枠導体部を有し、上記主面第３枠導体部が形成された領域全体の面積に占める上記主面第３枠導体部の導体面積の面積率、及び、上記裏面第２枠導体部が形成された領域全体の面積に占める上記裏面第２枠導体部の導体面積の面積率は、いずれも１００％とされている配線基板とすると良い。
【００１８】
本発明では、主面枠導体部は、主面第１，第２枠導体部の他、配線基板の周縁をなす主面第３枠導体部を有し、また、裏面枠導体部は、裏面第１枠導体部の他、配線基板の周縁をなす裏面第２枠導体部を有する。そして、主面第３枠導体部が形成された領域全体の面積に占める上記主面第３枠導体部の導体面積の面積率（以下、主面第３枠導体部の導体面積率とも言う。）、及び、裏面第２枠導体部が形成された領域全体の面積に占める裏面第２枠導体部の導体面積の面積率（以下、裏面第２枠導体部の導体面積率とも言う。）は、いずれも１００％とされている。
このように、配線基板の周縁部をなす導体層をベタ状とすれば、主面導体層及び裏面導体層を形成する際、電解メッキを施しやすくなる。即ち、電解メッキを施すための電極を、周縁部をなすベタ状導体層に確実に接触させて、電流を流すことができるので、主面側及び裏面側に電解メッキを確実に形成することができる。従って、主面導体層及び裏面導体層の厚みの均一性をより向上させることができる。
【００１９】
さらに、上記のいずれかに記載の配線基板であって、前記主面第１枠導体部及び前記裏面第１枠導体部は、いずれも多数の孔が形成されたメッシュ状の導体層からなる配線基板とすると良い。
【００２０】
上述した発明においては、主面第１枠導体部の導体面積率は、主面製品導体部の導体面積率と同一であればよく、また、裏面第１枠導体部の導体面積率は、裏面製品導体部の導体面積率と同一であればよいので、主面第１枠導体部及び裏面第１枠導体部をどのような形状（パターン）としてもよい。例えば、主面第１枠導体部等の形状を、主面製品導体部等の配線等のパターンと同一のパターンとすることができる。
しかし、主面製品導体部や裏面製品導体部のパターンは、場所により粗密の差がある場合もあるため、主面第１枠導体部や裏面第１枠導体部のパターンをこのような偏った形状とすると、主面製品導体部及び裏面製品導体部の導体層の厚みに不均一が生じる可能性もある。
これに対し、本発明では、主面第１枠導体部及び前記裏面第１枠導体部を、多数の孔が形成されたメッシュ状の導体層としているので、導体層に場所による粗密の差がない。このため、主面製品導体部及び裏面製品導体部の導体層の厚みの均一性をより向上させることができる。
【００２１】
また、他の解決手段は、主面と裏面を有し、製品部とこの製品部の周囲を取り囲む枠部とからなり、上記主面側に形成された主面導体層であって、上記製品部に形成された主面製品導体部と上記枠部に形成された主面枠導体部とからなる主面導体層と、上記裏面側に形成された裏面導体層であって、上記製品部に形成された裏面製品導体部と上記枠部に形成された裏面枠導体部とからなる裏面導体層と、を備え、上記主面製品導体部の導体面積が、上記裏面製品導体部の導体面積よりも小さい配線基板の製造方法であって、基板本体の上記主面側に、上記主面導体層に対応した所定パターンの主面メッキレジスト層を形成すると共に、上記基板本体の上記裏面側に、上記裏面導体層に対応した所定パターンの裏面メッキレジスト層を形成するメッキレジスト層形成工程であって、上記主面メッキレジスト層は、上記製品部に形成する主面製品レジスト部と上記枠部に形成する主面枠レジスト部とからなり、上記裏面メッキレジスト層は、上記製品部に形成する裏面製品レジスト部と上記枠部に形成する裏面枠レジスト部とからなり、上記主面枠レジスト部は、上記主面製品レジスト部を取り囲む主面第１枠レジスト部と、この主面第１枠レジスト部よりも外側に位置する主面第２枠レジスト部とを有し、上記裏面枠レジスト部は、上記裏面製品レジスト部を取り囲む裏面第１枠レジスト部を有し、上記主面第１枠レジスト部が形成された領域全体の面積に占める上記基板本体の露出部の露出割合が、上記製品部の面積に占める上記基板本体の主面側の露出部の露出割合と同一とされ、上記裏面第１枠レジスト部が形成された領域全体の面積に占める上記基板本体の露出部の露出割合が、上記製品部の面積に占める上記基板本体の裏面側の露出部の露出割合と同一とされ、上記主面第２枠レジスト部が形成された領域全体の面積に占める上記基板本体の露出部の露出割合が、上記製品部の面積に占める上記基板本体の裏面側の露出部の露出割合よりも大きくされることにより、上記基板本体の主面側の露出面積に対する上記基板本体の裏面側の露出面積の割合が、上記基板本体の製品部における主面側の露出面積に対する上記基板本体の製品部における裏面側の露出面積の割合よりも小さくされているメッキレジスト層形成工程と、上記メッキレジスト層形成工程後の上記基板本体に電解メッキを施し、上記基板本体の主面側の露出部に上記主面導体層に対応した電解メッキ層を形成すると共に、上記基板本体の裏面側の露出部に上記裏面導体層に対応した電解メッキ層を形成する電解メッキ工程と、を備える配線基板の製造方法である。
【００２２】
本発明は、製品部に形成された主面製品導体部と枠部に形成された主面枠導体部とからなる主面導体層と、製品部に形成された裏面製品導体部と枠部に形成された裏面枠導体部とからなる裏面導体層とを有し、主面製品導体部の導体面積が、裏面製品導体部の導体面積よりも小さい配線基板の製造に適用される。このような配線基板は、上述したように、主面導体層及び裏面導体層の厚みが不均一になりやすいからである。
【００２３】
本発明の製造方法は、メッキレジスト層形成工程と電解メッキ工程を備える。このうちメッキレジスト層形成工程では、基板本体の主面側に、主面導体層に対応した所定パターンの主面メッキレジスト層を形成すると共に、基板本体の裏面側に、裏面導体層に対応した所定パターンの裏面メッキレジスト層を形成する。具体的には、主面メッキレジスト層は、製品部に形成する主面製品レジスト部と枠部に形成する主面枠レジスト部とからなり、裏面メッキレジスト層は、製品部に形成する裏面製品レジスト部と枠部に形成する裏面枠レジスト部とからなる。このうち主面枠レジスト部は、主面製品レジスト部を取り囲む主面第１枠レジスト部と、これよりも外側に位置する主面第２枠レジスト部とを有し、裏面枠レジスト部は、裏面製品レジスト部を取り囲む裏面第１枠レジスト部を有する。そして、主面第１枠レジスト部が形成された領域全体の面積に占める基板本体の露出部の露出割合（以下、主面第１枠レジスト部における露出割合とも言う。）が、製品部の面積に占める基板本体の主面側の露出部の露出割合（以下、主面製品レジスト部における露出割合とも言う。）と同一とされている。また、裏面第１枠レジスト部が形成された領域全体の面積に占める基板本体の露出部の露出割合（以下、裏面第１枠レジスト部における露出割合とも言う。）が、製品部の面積に占める基板本体の裏面側の露出部の露出割合（以下、裏面製品レジスト部における露出割合とも言う。）と同一とされている。
【００２４】
このように、主面製品レジスト部を取り囲む主面第１枠レジスト部における露出割合が、主面製品レジスト部における露出割合と同一であれば、電解メッキ工程において、主面製品レジスト部において必要とされる単位面積あたりのメッキ量と、主面第１枠レジスト部において必要とされる単位面積あたりのメッキ量とがほぼ同じになる。このため、主面製品レジスト部のうち、主面枠レジスト部に近い部分（外側部分）とそこから離れた中央部分との間で、電解メッキ層の厚みに不均一が生じにくくなり、主面製品導体部の全体にわたり厚みの均一性を向上させることができる。
同様に、裏面製品レジスト部を取り囲む裏面第１枠レジスト部における露出割合が、裏面製品レジスト部における露出割合と同一であれば、電解メッキ工程において、裏面製品レジスト部において必要とされる単位面積あたりのメッキ量と、裏面第１枠レジスト部において必要とされる単位面積あたりのメッキ量とがほぼ同じになる。このため、裏面製品レジスト部のうち、裏面枠レジスト部に近い部分（外側部分）とそこから離れた中央部分との間で、電解メッキ層の厚みに不均一が生じにくくなり、裏面製品導体部の製品部分の全体にわたり厚みの均一性を向上させることができる。
【００２５】
さらに、本製造方法のメッキレジスト層形成工程では、主面第２枠レジスト部が形成された領域全体の面積に占める基板本体の露出部の露出割合（以下、主面第２枠レジスト部における露出割合とも言う。）が、上記の製品レジスト部における露出割合よりも大きくされることにより、基板本体の主面側の露出面積に対する基板本体の裏面側の露出面積の割合が、基板本体の製品部における主面側の露出面積に対する基板本体の製品部における裏面側の露出面積の割合よりも小さくされている。
【００２６】
このようにすれば、主面メッキレジスト層における基板本体の露出面積と裏面メッキレジスト層における基板本体の露出面積との差が、従来よりも小さくなる。このため、電解メッキ工程において、主面側と裏面側との間で、従来のようなメッキ層の厚みの不均一は生じにくくなり、主面導導体層と裏面導体層の厚みの均一性を向上させることができる。
【００２７】
【発明の実施の形態】
（実施形態１）
以下、本発明の実施の形態を、図を参照しつつ説明する。
本実施形態の配線基板１０１について、図１に主面１０２側から見た平面図を、図２に裏面１０３側から見た平面図を、図３に周縁付近の部分縦断面図を示す。なお、図１は主面側ソルダーレジスト層１１５がない状態を、図２は裏面側ソルダーレジスト層１１８がない状態を示している。
この配線基板１０１は、図１及び図２に示すように、平面視略矩形の略板形状をなす。配線基板１０１の平面視略中央には、個々の製品１０５Ｓが複数（７×６＝４２個）繋がった製品部１０５が形成され、この周囲には、後に廃棄される枠部１０７が形成されている。
【００２８】
配線基板１０１の内部についてみると、図３に示すように、この配線基板１０１は、その中心にガラス−エポキシ樹脂からなるコア基板１１１を備える。なお、図３中の破線は、製品部１０５と枠部１０７の境界を示す。コア基板１１１の主面１０２側には、エポキシ樹脂等からなる主面側第１絶縁層１１３、主面側第２絶縁層１１４、及び、主面側ソルダーレジスト層１１５が積層されている。一方、裏面１０３側にも、エポキシ樹脂等からなる主面側第１絶縁層１１６、裏面側第２絶縁層１１７、及び、裏面側ソルダーレジスト層１１８が積層されている。
【００２９】
また、配線基板１０１のうち、コア基板１１１の主面１０２側の表面には、Ｃｕからなる主面側第１導体層１２１が形成され、主面側第１絶縁層１１３の表面には、Ｃｕからなる主面側第２導体層１２３が形成され、さらに、主面側第２絶縁層１１４の表面には、Ｃｕからなる主面側第３導体層１２５が形成されている。同様に、コア基板１１１の裏面１０３側の表面には、Ｃｕからなる裏面側第１導体層１４１が形成され、裏面側第１絶縁層１１６の表面には、Ｃｕからなる裏面側第２導体層１４３が形成され、裏面側第２絶縁層１１７の表面には、Ｃｕからなる裏面側第３導体層１４５が形成されている。
【００３０】
さらに、配線基板１０１のうち、コア基板１１１には、層間接続のため、これを貫通するＣｕからなる略筒状のスルーホール導体１６１が形成されている。また、層間接続のため、主面側第１絶縁層１１３には、これを貫通するＣｕからなる主面側第１ビア導体１６３が形成され、主面側第２絶縁層１１４には、これを貫通するＣｕからなる主面側第２ビア導体１６５が形成されている。同様に、裏面側第１絶縁層１１６には、層間接続のため、これを貫通するＣｕからなる裏面側第１ビア導体１６７が形成され、裏面側第２絶縁層１１７には、これを貫通するＣｕからなる裏面側第２ビア導体１６９が形成されている。
【００３１】
上記のうち、主面側第３導体層１２５について詳述すると、この主面側第３導体層１２５は、製品部１０５に形成された主面製品導体部１２７と、枠部１０７に形成された主面枠導体部１２９とからなる。主面製品導体部１２７は、図４に製品部１０５を構成する個々の製品１０５Ｓの主面１０２側から見た平面図を示すように、複数の配線１２７Ｈやパッド１２７Ｐを有するが、その導体面積は比較的狭い。具体的には、製品部１０５全体の面積に占める主面製品導体部１２７の導体面積の面積率は、約５％である。なお、図４は主面側ソルダーレジスト層１１５がない状態を示している。
【００３２】
一方、主面枠導体部１２９は、図１に示すように、主面製品導体部１２７を取り囲む主面第１枠導体部１３０と、この主面第１枠導体部１３０よりも外側に位置しこれを取り囲む主面第２枠導体部１３１とを有し、さらに、この主面第２枠導体部１３１を取り囲み配線基板１０１の周縁をなす主面第３枠導体部１３２を有する。
これらの導体部のうち主面第１枠導体部１３０は、図示しない多数の円形状の孔が形成されたメッシュ状の導体層からなる。主面第１枠導体部１３０が形成された領域全体の面積に占める主面第１枠導体部１３０の導体面積の面積率は、約５％である。従って、上述の主面製品導体部１２７の導体面積率と同一にされている。
【００３３】
また、主面第２枠導体部１３１も、図示しない多数の円形状の孔が形成されたメッシュ状導体層からなる。主面第２枠導体部１３１が形成された領域全体の面積に占める主面第２枠導体部１３１の導体面積の面積率は、約９０％である。従って、後述する裏面製品導体部１４７の導体面積率（約８０％）よりも大きくされている。
また、主面第３枠導体部１３２は、ベタ状に形成されている。即ち、主面第３枠導体部１３２が形成された領域全体の面積に占める主面第３枠導体部１３２の導体面積の面積率は、１００％である。
なお、配線基板１０１の面積に占める主面側第３導体層１２５全体の導体面積の面積率は、約３０％である。
【００３４】
次に、裏面側第３導体層１４５について詳述すると、この裏面側第３導体層１４５は、製品部１０５に形成された裏面製品導体部１４７と、枠部１０７に形成された裏面枠導体部１４９とからなる。裏面製品導体部１４７は、図５に製品部１０５を構成する個々の製品１０５Ｓの裏面１０３側から見た平面図を示すように、略格子状に並んだ多数のパッド１４７Ｐを有するが、その導体面積は、主面製品導体部１２７の導体面積と比べてかなり広い。具体的には、製品部１０５の面積に占める裏面製品導体部１４７の導体面積の面積率は、約８０％である。なお、図５は裏面側ソルダーレジスト層１１８がない状態を示している。
【００３５】
一方、裏面枠導体部１４９は、図２に示すように、裏面製品導体部１４７を取り囲む裏面第１枠導体部１５０を有し、さらに、この裏面第１枠導体部１５０を取り囲み配線基板１０１の周縁をなす裏面第２枠導体部１５１を有する。
このうち裏面第１枠導体部１５０は、図示しない多数の円形状の孔が形成されたメッシュ状導体層からなる。裏面第１枠導体部１５０が形成された領域全体の面積に占める裏面第１枠導体部１５０の導体面積の面積率は、約８０％である。従って、上述の裏面製品導体部１４７の導体面積率と同一にされている。
【００３６】
また、裏面第２枠導体部１５１は、ベタ状に形成されている。即ち、裏面第２枠導体部１５１が形成された領域全体の面積に占める裏面第２枠導体部１５１の導体面積の面積率は、１００％である。
なお、配線基板１０１の面積に占める裏面側第３導体層１４５全体の導体面積の面積率は、約８５％である。
【００３７】
従って、この配線基板１０１では、主面第２枠導体部１３１の導体面積率が、裏面製品導体部１４７の導体面積率よりも大きくされることにより、主面側第３導体層１２５の導体面積に対する裏面側第３導体層１４５の導体面積の割合が、主面製品導体部１２７の導体面積に対する裏面製品導体部１４７の導体面積の割合よりも小さくされている。
【００３８】
このような配線基板１０１は、主面製品導体部１２７を取り囲む主面第１枠導体部１３０の導体面積率が、主面製品導体部１２７の導体面積率と同一（約５％）であるので、主面製品導体部１２７の形成に必要とされる単位面積あたりのメッキ量と、主面第１枠導体部１３０の形成に必要とされる単位面積あたりのメッキ量とがほぼ同じになる。このため、主面製品導体部１２７のうち、主面枠導体部１２９に近い部分とそこから離れた中央部分との間で、従来にみられた導体層の厚みの不均一は生じにくくなり、主面製品導体部１２７の全体にわたり厚みの均一性を向上させることができる。
同様に、裏面製品導体部１４７を取り囲む裏面第１枠導体部１５０の導体面積率が、裏面製品導体部１４７の導体面積率と同一（約８０％）であるので、裏面製品導体部１４７の形成に必要とされる単位面積あたりのメッキ量と、裏面第１枠導体部１５０の形成に必要とされる単位面積あたりのメッキ量とがほぼ同じになる。このため、裏面製品導体部１４７のうち、裏面枠導体部１４９に近い部分とそこから離れた中央部分との間で、従来にみられた導体層の厚みの不均一は生じにくくなり、裏面製品導体部１４７の全体にわたり厚みの均一性を向上させることができる。
【００３９】
また、主面第２枠導体部１３１の導体面積率を裏面製品導体部１４７の導体面積率よりも大きくして、主面側第３導体層１２５の導体面積に対する裏面側第３導体層１４５の導体面積の割合を、主面製品導体部１２７の導体面積に対する裏面製品導体部１４７の導体面積の割合よりも小さくしてるので、主面側第３導体層１２５の導体面積と裏面側第３導体層１４５の導体面積との差が、従来の配線基板よりも小さくなる。このため、主面側第３導体層１２５と裏面側第３導体層１４５との間で、従来にみられた導体層の厚みの不均一は生じにくくなり、主面側第３導体層（主面導体層）１２５及び裏面側第３導体層（裏面導体層）１４５の厚みの均一性を向上させることができる。
【００４０】
また、本実施形態では、配線基板１０１の周縁部をなす主面第３枠導体部１３２の導体面積率と裏面第２枠導体部１５１の導体面積率を、いずれも１００％としている。このため、主面側第３導体層１２５及び裏面側第３導体層１４５を形成する際、電解メッキを施しやすくなる。即ち、電解メッキを施すための電極を、周縁部をなすベタ状導体層に確実に接触させ、電流を流すことができるので、電解メッキを確実に形成することができる。従って、主面側第３導体層１２５及び裏面側第３導体層１４５の厚みの均一性をより向上させることができる。
【００４１】
また、本実施形態では、主面第１枠導体部１３０及び裏面第１枠導体部１５０を、多数の孔が形成されたメッシュ状の導体層としているので、これらの導体部には、場所による粗密の差がない。このため、主面製品導体部１２７及び裏面製品導体部１４７の導体層の厚みの均一性をより向上させることができる。
【００４２】
次いで、上記配線基板１０１の製造方法について説明する。
まず、コア基板１１１の両面に銅箔を張り付けた両面銅張コア基板を用意する。そして、ドリルやレーザ等によって、スルーホール導体１６１を形成するためのスルーホールを所定の位置に形成する。
次に、コア基板１１１にＣｕ無電解メッキを施し、銅箔上及びスルーホールの内周面に無電解メッキ層を形成する。さらに、Ｃｕ電解メッキを施して、無電解メッキ層上に電解メッキ層を形成する。これにより、銅箔上にベタ状のメッキ層が形成され、スルーホールの内周面に略筒状のスルーホール導体１６１が形成される。
【００４３】
その後、スルーホール導体１６１内に樹脂ペーストを印刷充填し、加熱して半硬化させる。そして、コア基板１１１から膨出した余分な樹脂を研磨除去し、さらに、加熱硬化させて、樹脂充填体を形成する。さらに、Ｃｕ無電解メッキとＣｕ電解メッキを行い、スルーホール導体１６１上に蓋メッキ層を形成する。
その後、コア基板１１１の両面に所定パターンのエッチングレジスト層を形成し、このレジスト層から露出するメッキ層及び銅箔をエッチング除去する。これにより、コア基板１１１上に主面側第１導体層１２１と裏面側第１導体層１４１が形成される。
【００４４】
次に、コア基板１１１上に、エポキシ樹脂等からなる半硬化の主面側第１絶縁層を形成し、主面側第１ビア導体１６３を形成するためのビアホールに対応した所定パターンを有するマスクを用いて露光しさらに現像する。その後、さらに加熱処理し硬化させて、ビアホールを有する主面側第１絶縁層１１３を形成する。またこれと共に、裏面側第１ビア導体１６７を形成するためのビアホールを有する裏面側第１絶縁層１１６も形成する。
【００４５】
次に、Ｃｕ無電解メッキを施して、主面側第１絶縁層１１３上及びそのビアホール内並びに裏面側第１絶縁層１１６上及びそのビアホール内に無電解メッキ層を形成する。その後、両面の無電解メッキ層上に所定パターンのメッキレジスト層をそれぞれ形成する。そして、Ｃｕ電解メッキを施して、メッキレジスト層から露出した無電解メッキ層上に電解メッキを形成する。その後、メッキレジスト層を除去し、さらに、これにより露出した無電解メッキ層をソフトエッチングにより除去する。これにより、主面側第１ビア導体１６３及び裏面側第１ビア導体１６７が形成されると共に、所定パターンの主面側第２導体層１２３及び裏面側第２導体層１４３が形成される。
【００４６】
次に、主面側第１絶縁層１１３上に、エポキシ樹脂等からなる半硬化の主面側第２絶縁層を形成し、主面側第２ビア導体１６５を形成するためのビアホールに対応した所定パターンを有するマスクを用いて露光しさらに現像する。その後、さらに加熱処理し硬化させて、ビアホールを有する主面側第２絶縁層１１４を形成する。またこれと共に、裏面側第２ビア導体１６９を形成するためのビアホールを有する裏面側第２絶縁層１１７も形成する。
【００４７】
次に、Ｃｕ無電解メッキを施して、主面側第２絶縁層１１４上及びそのビアホール内並びに裏面側第２絶縁層１１７上及びそのビアホール内に無電解メッキ層を形成する。
そして、メッキレジスト層形成工程において、図６に示すように、この基板本体１８１の主面側に、主面側第３導体層１２５に対応した所定パターンの主面メッキレジスト層１８２を形成すると共に、裏面側に、裏面側第３導体層１４５に対応した所定パターンの裏面メッキレジスト層１９２を形成する。
【００４８】
具体的には、主面メッキレジスト層１８２は、製品部１０５に形成する主面製品レジスト部１８３と、枠部１０７に形成する主面枠レジスト部１８４とからなり、裏面メッキレジスト層１９２も、製品部１０５に形成する裏面製品レジスト部１９３と、枠部１０７に形成する裏面枠レジスト部１９４とからなる。このうち、主面枠レジスト部１８４は、主面製品レジスト部１８３を取り囲む主面第１枠レジスト部１８５と、この主面第１枠レジスト部１８５よりも外側に位置しこれを取り囲む主面第２枠レジスト部１８６からなる。また、裏面枠レジスト部１９４は、裏面製品レジスト部を取り囲む裏面第１枠レジスト部１９５からなる。
【００４９】
そして、主面第１枠レジスト部１８５が形成された領域全体の面積に占める基板本体１８１の露出部の露出割合が、製品部１０５の面積に占める基板本体１８１の主面側の露出部の露出割合と同一とされる。また、裏面第１枠レジスト部１９５が形成された領域全体の面積に占める基板本体１８１の露出部の露出割合が、製品部１０５の面積に占める基板本体１１１の裏面側の露出部の露出割合と同一とされる。
さらに、主面第２枠レジスト部１８６が形成された領域全体の面積に占める基板本体１８１の露出部の露出割合が、製品部１０５の面積に占める基板本体１１の裏面側の露出部の露出割合よりも大きくされることにより、基板本体１１１の主面側の露出面積に対する基板本体１１１の裏面側の露出面積の割合が、基板本体１１１の製品部１０５における主面側の露出面積に対する基板本体１１１の製品部１０５における裏面側の露出面積の割合よりも小さくされる。
【００５０】
次に、電解メッキ工程において、上記基板本体１８１にＣｕ電解メッキを施し、基板本体１８１の主面側の露出部に主面側第３導体層１２５に対応した電解メッキ層を形成すると共に、基板本体１８１の裏面側の露出部に裏面側第３導体層１４５に対応した電解メッキ層を形成する。
その後、主面メッキレジスト層１８２及び裏面メッキレジスト層１９２を除去し、さらに、これにより露出した無電解メッキ層をソフトエッチングにより除去する。これにより、主面側第２ビア導体１６５及び裏面側第２ビア導体１６９が形成されると共に、所定パターンの主面側第３導体層１２５及び裏面側第３導体層１４５が形成される。
【００５１】
次に、主面側第２絶縁層１１４上に、エポキシ樹脂等からなる半硬化の主面側ソルダーレジスト層を形成し、所定パターンを有するマスクを用いて露光しさらに現像する。その後、さらに加熱処理し硬化させて、所定パターンの主面側ソルダーレジスト層１１５を形成する。またこれと共に、所定パターンの裏面側ソルダーレジスト層１１８を形成する。
以上のようにして、配線基板１０１が完成する。
【００５２】
このような製造方法によれば、主面製品レジスト部１８３を取り囲む主面第１枠レジスト部１８５における露出割合が、主面製品レジスト部１８３における露出割合と同一であるので、電解メッキ工程で、主面製品レジスト部１８３において必要とされる単位面積あたりのメッキ量と、主面第１枠レジスト部１８５において必要とされる単位面積あたりのメッキ量とがほぼ同じになる。このため、主面製品レジスト部１８３のうち、主面枠レジスト部１８４に近い部分とそこから離れた中央部分との間で、電解メッキ層の厚みに不均一が生じにくくなり、主面製品導体部１２７の全体にわたり厚みの均一性を向上させることができる。
同様に、裏面製品レジスト部１９３を取り囲む裏面第１枠レジスト部１９５における露出割合が、裏面製品レジスト部１９３における露出割合と同一であるので、電解メッキ工程において、裏面製品レジスト部１９３において必要とされる単位面積あたりのメッキ量と、裏面第１枠レジスト部１９５において必要とされる単位面積あたりのメッキ量とがほぼ同じになる。このため、裏面製品レジスト部１９３のうち、裏面枠レジスト部１９５に近い部分とそこから離れた中央部分との間で、電解メッキ層の厚みに不均一が生じにくくなり、裏面製品導体部１４７の全体にわたり厚みの均一性を向上させることができる。
【００５３】
また、主面第２枠レジスト部１８６における露出割合を裏面製品レジスト部１９３における露出割合よりも大きくして、基板本体１８１の主面側の露出面積に対する基板本体１８１の裏面側の露出面積の割合が、基板本体１８１の製品部１０５における主面側の露出面積に対する基板本体１８１の製品部１０５における裏面側の露出面積の割合よりも小さくしている。このため、主面メッキレジスト層１８２における露出面積と裏面メッキレジスト層１９２における露出面積との差が、従来よりも小さくなる。従って、電解メッキ工程において、主面側第３導体層１２５と裏面側第３導体層１４５との間で、従来のようなメッキ層の厚みの不均一は生じにくくなり、主面側第３導体層１２５と裏面側第３導体層１４５の厚みの均一性を向上させることができる。
【００５４】
（実施形態２）
次いで、第２の実施の形態について説明する。なお、上記実施形態１と同様な部分の説明は、省略または簡略化する。
本実施形態の配線基板は、上記実施形態１の配線基板１０１と同様な構成をなす。
【００５５】
本実施形態では、まず、主面側第３導体層１２５について説明すると、製品部１０５全体の面積に占める主面製品導体部１２７の導体面積の面積率は、約３．３％である。
主面第１枠導体部１３０は、多数の矩形状の孔（１９６７μｍ×１９６７μｍ）が形成されたメッシュ状の導体層からなる。主面第１枠導体部１３０が形成された領域全体の面積に占める主面第１枠導体部１３０の導体面積の面積率は、約３．３％である。従って、本実施形態でも、上述の主面製品導体部１２７の導体面積率と同一にされている。
【００５６】
また、主面第２枠導体部１３１も、多数の矩形状の孔（９００μｍ×９００μｍ）が形成されたメッシュ状導体層からなる。主面第２枠導体部１３１が形成された領域全体の面積に占める主面第２枠導体部１３１の導体面積の面積率は、約８０％である。従って、後述する裏面製品導体部１４７の導体面積率（約５０％）よりも大きくされている。
また、主面第３枠導体部１３２は、上記実施形態１と同様に、ベタ状に形成されている。即ち、主面第３枠導体部１３２が形成された領域全体の面積に占める主面第３枠導体部１３２の導体面積の面積率は、１００％である。
なお、配線基板１０１の面積に占める主面側第３導体層１２５全体の導体面積の面積率は、約３８％である。
【００５７】
次に、裏面側第３導体層１４５について説明すると、製品部１０５の面積に占める裏面製品導体部１４７の導体面積の面積率は、約５０％である。従って、主面製品導体部１２７の導体面積に対する裏面製品導体部１４７の導体面積の割合は、約１５倍である。
裏面第１枠導体部１５０は、多数の矩形状の孔（１５００μｍ×１５００μｍ）が形成されたメッシュ状導体層からなる。裏面第１枠導体部１５０が形成された領域全体の面積に占める裏面第１枠導体部１５０の導体面積の面積率は、約５０％である。従って、本実施形態でも、上述の裏面製品導体部１４７の導体面積率と同一にされている。
【００５８】
また、裏面第２枠導体部１５１は、上記実施形態１と同様に、ベタ状に形成されている。即ち、裏面第２枠導体部１５１が形成された領域全体の面積に占める裏面第２枠導体部１５１の導体面積の面積率は、１００％である。
なお、配線基板１０１の面積に占める裏面側第３導体層１４５全体の導体面積の面積率は、約３８％である。従って、主面側第３導体層１２５の導体面積に対する裏面側第３導体層１４５の導体面積の割合は、約１倍である。
【００５９】
よって、本実施形態の配線基板も、主面第２枠導体部１３１の導体面積率（約８０％）が、裏面製品導体部１４７の導体面積率（約５０％）よりも大きくされることにより、主面側第３導体層１２５の導体面積に対する裏面側第３導体層１４５の導体面積の割合（約１倍）が、主面製品導体部１２７の導体面積に対する裏面製品導体部１４７の導体面積の割合（約１５倍）よりも小さくされている。
【００６０】
このような配線基板も、主面製品導体部１２７を取り囲む主面第１枠導体部１３０の導体面積率が、主面製品導体部１２７の導体面積率と同一（約３．３％）であるので、主面製品導体部１２７の形成に必要とされる単位面積あたりのメッキ量と、主面第１枠導体部１３０の形成に必要とされる単位面積あたりのメッキ量とがほぼ同じになる。このため、主面製品導体部１２７のうち、主面枠導体部１２９に近い部分とそこから離れた中央部分との間で、従来にみられた導体層の厚みの不均一は生じにくくなり、主面製品導体部１２７の全体にわたり厚みの均一性を向上させることができる。
同様に、裏面製品導体部１４７を取り囲む裏面第１枠導体部１５０の導体面積率が、裏面製品導体部１４７の導体面積率と同一（約５０％）であるので、裏面製品導体部１４７の形成に必要とされる単位面積あたりのメッキ量と、裏面第１枠導体部１５０の形成に必要とされる単位面積あたりのメッキ量とがほぼ同じになる。このため、裏面製品導体部１４７のうち、裏面枠導体部１４９に近い部分とそこから離れた中央部分との間で、従来にみられた導体層の厚みの不均一は生じにくくなり、裏面製品導体部１４７の全体にわたり厚みの均一性を向上させることができる。
【００６１】
また、主面第２枠導体部１３１の導体面積率（約８０％）を裏面製品導体部１４７の導体面積率（約５０％）よりも大きくして、主面側第３導体層１２５の導体面積に対する裏面側第３導体層１４５の導体面積の割合（約１倍）を、主面製品導体部１２７の導体面積に対する裏面製品導体部１４７の導体面積の割合（約１５倍）よりも小さくしてるので、主面側第３導体層１２５の導体面積と裏面側第３導体層１４５の導体面積との差が、従来の配線基板よりも小さくなる。このため、主面側第３導体層１２５と裏面側第３導体層１４５との間で、従来にみられた導体層の厚みの不均一は生じにくくなり、主面側第３導体層（主面導体層）１２５及び裏面側第３導体層（裏面導体層）１４５の厚みの均一性を向上させることができる。
【００６２】
また、配線基板の周縁部をなす主面第３枠導体部１３２の導体面積率と裏面第２枠導体部１５１の導体面積率を、いずれも１００％としている。このため、主面側第３導体層１２５及び裏面側第３導体層１４５を形成する際、電解メッキを施しやすくなる。即ち、電解メッキを施すための電極を、周縁部をなすベタ状導体層に確実に接触させ、電流を流すことができるので、電解メッキを確実に形成することができる。従って、主面側第３導体層１２５及び裏面側第３導体層１４５の厚みの均一性をより向上させることができる。
【００６３】
また、主面第１枠導体部１３０及び裏面第１枠導体部１５０を、多数の孔が形成されたメッシュ状の導体層としているので、これらの導体部には、場所による粗密の差がない。このため、主面製品導体部１２７及び裏面製品導体部１４７の導体層の厚みの均一性をより向上させることができる。
【００６４】
さらに、本実施形態においては、主面製品導体部１２７の導体面積に対する裏面製品導体部１４７の導体面積の割合（約１５倍）が、３以上であるため、主面側第３導体層１２５と裏面側第３導体層１４５との間で、特に、導体層の厚みに不均一が生じやすい。しかし、主面側第３導体層１２５の導体面積に対する裏面側第３導体層１２５の導体面積の割合（約１倍）を、２以下と小さくしている。このため、主面側第３導体層１２５と裏面側第３導体層１４５との間で、導体層の厚みの均一性をより向上させることができる。
【００６５】
なお、本実施形態の配線基板は、上記実施形態１の配線基板１０１と同様にして製造することができる。
従って、このような製造方法によれば、主面製品レジスト部１８３を取り囲む主面第１枠レジスト部１８５における露出割合が、主面製品レジスト部１８３における露出割合と同一であるので、電解メッキ工程で、主面製品レジスト部１８３において必要とされる単位面積あたりのメッキ量と、主面第１枠レジスト部１８５において必要とされる単位面積あたりのメッキ量とがほぼ同じになる。このため、主面製品レジスト部１８３のうち、主面枠レジスト部１８４に近い部分とそこから離れた中央部分との間で、電解メッキ層の厚みに不均一が生じにくくなり、主面製品導体部１２７の全体にわたり厚みの均一性を向上させることができる。
同様に、裏面製品レジスト部１９３を取り囲む裏面第１枠レジスト部１９５における露出割合が、裏面製品レジスト部１９３における露出割合と同一であるので、電解メッキ工程において、裏面製品レジスト部１９３において必要とされる単位面積あたりのメッキ量と、裏面第１枠レジスト部１９５において必要とされる単位面積あたりのメッキ量とがほぼ同じになる。このため、裏面製品レジスト部１９３のうち、裏面枠レジスト部１９５に近い部分とそこから離れた中央部分との間で、電解メッキ層の厚みに不均一が生じにくくなり、裏面製品導体部１４７の全体にわたり厚みの均一性を向上させることができる。
【００６６】
また、主面第２枠レジスト部１８６における露出割合を裏面製品レジスト部１９３における露出割合よりも大きくして、基板本体１８１の主面側の露出面積に対する基板本体１８１の裏面側の露出面積の割合が、基板本体１８１の製品部１０５における主面側の露出面積に対する基板本体１８１の製品部１０５における裏面側の露出面積の割合よりも小さくしている。このため、主面メッキレジスト層１８２における露出面積と裏面メッキレジスト層１９２における露出面積との差が、従来よりも小さくなる。従って、電解メッキ工程において、主面側第３導体層１２５と裏面側第３導体層１４５との間で、従来のようなメッキ層の厚みの不均一は生じにくくなり、主面側第３導体層１２５と裏面側第３導体層１４５の厚みの均一性を向上させることができる。
【００６７】
以上において、本発明を実施形態に即して説明したが、本発明は上記各実施形態１，２に限定されるものではなく、その要旨を逸脱しない範囲で、適宜変更して適用できることはいうまでもない。
例えば、上記実施形態１では、主面第１枠導体層１３０及び裏面第１枠導体層１５０を、円形状の孔を形成してメッシュ状とし、上記実施形態２では、主面第１枠導体層１３０及び裏面第１枠導体層１５０を、矩形状の孔を形成してメッシュ状としているが、この孔の形状は、円形や矩形である必要はない。例えば、楕円形状、多角形状等とすることもできる。このようにしても、全体として導体層がメッシュ状に形成されていれば、上述の効果を得ることができる。
【００６８】
また、上記実施形態１，２では、主面第２枠導体部１３１は、主面第１枠導体部１３０を取り囲む口字形状とされているが、主面第１枠導体部１３０の外側に位置するものであれば、どのような形状（パターン）とすることもできる。
また、上記実施形態１，２では、コア基板１１１の両面に３層の導体層と３層の絶縁層を交互に形成した多層配線基板を示したが、さらに多層の配線基板とすることもできる。
【００６９】
また、上記実施形態１，２では、配線基板１０１の最も主面１０２側に位置する主面側第３導体層１２５と、最も裏面１０３側に位置する裏面側第３導体層１４５について、本発明を適用したが、内部の導体層についても適用することができる。例えば、主面側第２導体層１２３と主面側第２導体層１４３において、その主面製品導体部の導体面積がその裏面製品導体部の導体面積よりも小さい場合には、本発明を適用することができる。
【図面の簡単な説明】
【図１】実施形態に係る配線基板の主面側から見た平面図である。
【図２】実施形態に係る配線基板の裏面側から見た平面図である。
【図３】実施形態に係る配線基板のうち周縁付近を示す部分縦断面図である。
【図４】実施形態に係る配線基板のうち、個々の製品についての主面側から見た平面図である。
【図５】実施形態に係る配線基板のうち、個々の製品についての裏面側から見た平面図である。
【図６】実施形態に係る配線基板の製造方法に関し、主面側第２絶縁層及び裏面側第２絶縁層を有する基板本体に、主面メッキレジスト層及び裏面メッキレジスト層を形成した様子を示す説明図である。
【図７】従来技術に係る配線基板の主面側から見た平面図である。
【図８】従来技術に係る配線基板の裏面側から見た平面図である。
【図９】従来技術に係る配線基板のうち、個々の製品についての主面側から見た平面図である。
【図１０】従来技術に係る配線基板のうち、個々の製品についての裏面側から見た平面図である。
【符号の説明】
１０１　　　配線基板
１０２　　　主面
１０３　　　　　　裏面
１０５　　　製品部
１０７　　　枠部
１２１　　　主面側第１導体層
１２３　　　主面側第２導体層
１２５　　　主面側第３導体層
１２７　　　主面製品導体部
１２９　　　主面枠導体部
１３０　　　主面第１枠導体部
１３１　　　主面第２枠導体部
１３２　　　主面第３枠導体部
１４１　　　裏面側第１導体層
１４３　　　裏面側第２導体層
１４５　　　裏面側第３導体層
１４７　　　裏面製品導体部
１４９　　　裏面枠導体部
１５０　　　裏面第１枠導体部
１５１　　　裏面第２枠導体部[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a wiring board comprising a product part and a frame part surrounding the product part, and a method of manufacturing the wiring board, and more particularly, to a wiring board having a conductor layer formed on a main surface side and a back surface side, respectively, and a method of manufacturing the wiring board About.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there has been known a wiring board including a product part and a frame part surrounding the product part.
For example, FIG. 7 shows a wiring board 901 shown in a plan view from the main surface 902 side, and FIG. This wiring board 901 is a multilayer wiring board in which a plurality of conductor layers and insulating layers are alternately laminated on both surfaces of a core substrate, and has a substantially rectangular and substantially plate shape. A product section 905, in which a plurality of (7 × 6 = 42) individual products 905S are connected, is formed substantially at the center of the wiring board 901 in a plan view, and a frame section 907 to be discarded later is formed around the product section 905. I have.
[0003]
On the main surface 902 side of the wiring board 901, a main surface conductor layer 911 is formed as schematically shown in FIG. The main surface conductor layer 911 includes a main surface product conductor portion 913 formed on the product portion 905 and a main surface frame conductor portion 915 formed on the frame portion 907. The main surface product conductor portion 913 has a plurality of wirings 913H and pads 913P as shown in FIG. 9 as viewed from the main surface 902 side of each product 905S constituting the product portion 905. Is relatively small. On the other hand, as shown in FIG. 7, the main surface frame conductor 915 is formed in a substantially solid shape on substantially the entire surface of the frame 907.
[0004]
On the other hand, on the back surface 903 side of the wiring substrate 901, a back surface conductor layer 931 is formed as schematically shown in FIG. The back surface conductor layer 931 includes a back surface product conductor portion 933 formed on the product portion 905 and a back surface frame conductor portion 935 formed on the frame portion 907. As shown in a plan view of the back product conductor 933 viewed from the back surface 903 side of each product 905S in FIG. 10, the back product conductor 933 has a large number of pads 933P arranged in a substantially lattice shape. It is significantly wider than the conductor 913. On the other hand, as shown in FIG. 8, the back surface frame conductor 935 is formed substantially solidly over substantially the entire surface of the frame 907, similarly to the main surface frame conductor 915.
As a document related to such a technique, for example, Patent Document 1 is cited.
[0005]
[Patent Document 1]
Japanese Patent No. 3172509
[0006]
[Problems to be solved by the invention]
However, the main-surface-side conductor layer 911 and the rear-surface-side conductor layer 931 are formed together by using electrolytic plating. However, the conductor area of the main-surface product conductor 913 is smaller than the conductor area of the rear-surface product conductor 933. Therefore, the conductor layer of the main surface product conductor portion 913 tends to be formed thinner, and the conductor layer of the back surface product conductor portion 933 tends to be formed thicker. This is considered to be caused by the fact that if the plating area is small, the current flow is poor and plating is difficult to be formed, and if the plating area is large, the current flow is good and the plating is easily formed.
[0007]
In addition, a portion (outside portion) of the main surface product conductor portion 913 close to the main surface frame conductor portion 915 has a thinner conductor layer, and a central portion of the main surface product conductor portion 913 has a thicker conductor layer. Tends to form. This is because the plating area ratio of the main surface frame conductor portion 915 is larger than the plating area ratio of the main surface product conductor portion 913, so that the conductor layer of the main surface frame conductor portion 915 is larger than the conductor layer of the main surface product conductor portion 913. Although it is easy to be formed thickly, at that time, a large amount of plating is required for forming the main surface frame conductor portion 915. Therefore, plating is formed in a portion of the main surface product conductor portion 913 that is close to the main surface frame conductor portion 915. This is considered to be due to the difficulty. For the same reason, a portion (outside portion) of the back product conductor portion 933 close to the back frame conductor portion 935 has a thinner conductive layer, and a central portion of the main surface product conductor portion 933 has a conductor layer larger than that. It tends to be formed thick.
If the thickness of the conductor layer is different between the main surface product conductor portion 913 and the back surface product conductor portion 933, or if the thickness of the conductor layer is not uniform in each conductor portion, the reliability of the wiring board 901 is inferior. .
[0008]
The present invention has been made in view of the current situation, and relates to a wiring board including a product part and a frame part, and a wiring board capable of improving the uniformity of the thickness of the main surface conductor layer and the back surface conductor layer. An object of the present invention is to provide a method for manufacturing a wiring board.
[0009]
Means for Solving the Problems, Functions and Effects
The solution is a main surface conductor layer formed on the main surface side, comprising a product portion and a frame portion surrounding the periphery of the product portion, having a main surface and a back surface. A main surface conductor layer composed of a main surface product conductor portion and a main surface frame conductor portion formed on the frame portion, and a back surface conductor layer formed on the back surface side, formed on the product portion. A back conductor layer comprising a back product conductor and a back frame conductor formed in the frame, wherein the conductor area of the main product conductor is smaller than the conductor area of the back product conductor; The main surface frame conductor is a main surface first frame conductor surrounding the main surface product conductor, and a main surface second frame conductor located outside the main surface first frame conductor. And the back frame conductor has a back first frame conductor surrounding the back product conductor, and The area ratio of the conductor area of the main surface first frame conductor to the area of the entire area where the first frame conductor is formed is the area ratio of the conductor area of the main surface product conductor to the area of the product part. And the area ratio of the conductor area of the backside first frame conductor to the area of the entire region in which the backside first frame conductor is formed is the ratio of the backside product conductor to the area of the product part. The area ratio of the conductor area of the main surface second frame conductor to the area of the entire area where the main surface second frame conductor is formed is the same as the area ratio of the conductor area. The ratio of the conductor area of the back surface conductor layer to the conductor area of the main surface conductor layer is set to be larger than the area ratio of the conductor area of the back surface product conductor portion occupied, with respect to the conductor area of the main surface product conductor portion. Smaller than the conductor area ratio of the back product conductor A wiring substrate being.
[0010]
The present invention relates to a main surface conductor layer including a main surface product conductor portion formed in a product portion and a main surface frame conductor portion formed in a frame portion, and a back surface product conductor portion and a frame portion formed in a product portion. The present invention is applied to a wiring board having a back surface conductor layer composed of a formed back frame conductor portion and a conductor area of the main surface product conductor portion being smaller than a conductor area of the back surface product conductor portion. This is because in such a wiring board, as described above, the thicknesses of the main surface conductor layer and the rear surface conductor layer tend to be non-uniform.
[0011]
In the wiring board according to the present invention, the main surface frame conductor portion surrounds the main surface product conductor portion, and the main surface second frame conductor located outside the main surface first frame conductor portion. The back frame conductor has a back first frame conductor surrounding the back product conductor. Then, the area ratio of the conductor area of the main surface first frame conductor to the entire area in which the main surface first frame conductor is formed (hereinafter also referred to as the conductor area ratio of the main surface first frame conductor). Is the same as the area ratio of the conductor area of the main surface product conductor portion to the product area (hereinafter, also referred to as the conductor area ratio of the main surface product conductor portion). Also, the area ratio of the conductor area of the backside first frame conductor to the entire area in which the backside first frame conductor is formed (hereinafter, also referred to as the conductor area ratio of the backside first frame conductor) is a product. It is the same as the area ratio of the conductor area of the back product conductor portion to the area of the portion (hereinafter, also referred to as the conductor area ratio of the back product conductor portion).
[0012]
As described above, if the conductor area ratio of the main surface first frame conductor surrounding the main surface product conductor is the same as the conductor area ratio of the main surface product conductor, it is necessary to form the main surface product conductor. The amount of plating per unit area is substantially the same as the amount of plating per unit area required for forming the main surface first frame conductor. For this reason, in the main surface product conductor portion, the nonuniformity of the thickness of the conductor layer, which is conventionally observed, is unlikely to occur between a portion (outside portion) close to the main surface frame conductor portion and a central portion away therefrom. Thus, the uniformity of the thickness over the entire main surface product conductor can be improved.
Similarly, if the conductor area ratio of the back surface first frame conductor portion surrounding the back surface product conductor portion is the same as the conductor area ratio of the back surface product conductor portion, the unit area per unit area required for formation of the back surface product conductor portion is obtained. The amount of plating and the amount of plating per unit area required for forming the backside first frame conductor portion are substantially the same. For this reason, in the back product conductor portion, between the portion near the back frame conductor portion and the central portion distant from the back frame conductor portion, the uneven thickness of the conductor layer which is conventionally observed is less likely to occur, and the back product conductor portion Can improve the uniformity of the thickness over the entire area.
[0013]
Furthermore, in the wiring board of the present invention, the area ratio of the conductor area of the main surface second frame conductor to the entire area of the region where the main surface second frame conductor is formed (hereinafter, the area ratio of the main surface second frame conductor) The conductor area ratio is also made larger than the conductor area ratio of the back surface conductor portion, so that the ratio of the conductor area of the back surface conductor layer to the conductor area of the main surface conductor layer is reduced. Is smaller than the ratio of the conductor area of the back product conductor to the conductor area.
[0014]
With this configuration, the difference between the conductor area of the main surface conductor layer and the conductor area of the back surface conductor layer is smaller than that of a conventional wiring board. For this reason, unevenness in the thickness of the conductor layer, which has been conventionally observed, is less likely to occur between the main surface conductor layer and the back surface conductor layer (between the main surface product conductor portion and the back surface product conductor portion). The thickness uniformity of the surface conductor layer and the back surface conductor layer (the main surface product conductor portion and the back surface product conductor portion) can be improved.
[0015]
Further, in the above wiring board, in the wiring board wherein the ratio of the conductor area of the back surface product conductor portion to the conductor area of the main surface product conductor portion is 3 or more, It is preferable to use a wiring board in which the ratio of the conductor area of the back conductor layer is 2 or less.
[0016]
In a wiring board in which the ratio of the conductor area of the back product conductor portion to the conductor area of the main product conductor portion is 3 or more, between the main surface conductor layer and the back surface conductor layer (the main product conductor portion and the back product conductor). In particular, the thickness of the conductor layer is likely to be uneven.
Therefore, it is preferable to apply the above-described invention. In this case, in the present invention, the ratio of the conductor area of the back surface conductor layer to the conductor area of the main surface conductor layer is reduced to 2 or less. Therefore, the uniformity of the thickness of the conductor layer can be further improved between the main surface conductor layer and the back surface conductor layer (between the main surface product conductor portion and the back surface product conductor portion).
[0017]
Furthermore, in the wiring board according to any one of the above, the main surface frame conductor portion has a main surface third frame conductor portion that forms a periphery of the wiring substrate, and the back surface frame conductor portion includes the wiring member. An area ratio of the conductor area of the main surface third frame conductor to the entire area in which the main surface third frame conductor is formed, and a back surface second frame conductor forming the periphery of the substrate; The wiring board may be such that the area ratio of the conductor area of the rear surface second frame conductor portion to the entire area of the region where the rear surface second frame conductor portion is formed is 100%.
[0018]
In the present invention, the main surface frame conductor has a main surface third frame conductor forming the periphery of the wiring board in addition to the main surface first and second frame conductors. In addition to the first frame conductor, the second frame conductor on the back surface that forms the periphery of the wiring board is provided. Then, the area ratio of the conductor area of the main surface third frame conductor to the entire area in which the main surface third frame conductor is formed (hereinafter, also referred to as the conductor area ratio of the main surface third frame conductor). ), And the area ratio of the conductor area of the backside second frame conductor to the entire area of the region where the backside second frame conductor is formed (hereinafter also referred to as the conductor area ratio of the backside second frame conductor). , And 100%.
If the conductor layer forming the peripheral portion of the wiring board is solid as described above, it becomes easier to perform electrolytic plating when forming the main surface conductor layer and the back surface conductor layer. That is, the electrode for applying the electrolytic plating is reliably brought into contact with the solid conductor layer forming the peripheral portion, and the current can be flowed, so that the electrolytic plating can be surely formed on the main surface side and the back surface side. it can. Therefore, the uniformity of the thickness of the main surface conductor layer and the back surface conductor layer can be further improved.
[0019]
Further, in the wiring board according to any one of the above, the main surface first frame conductor portion and the back surface first frame conductor portion are each formed of a mesh-shaped conductor layer having a large number of holes formed therein. It is good to use it as a substrate.
[0020]
In the above-described invention, the conductor area ratio of the main surface first frame conductor portion may be the same as the conductor area ratio of the main surface product conductor portion. The main surface first frame conductor portion and the back surface first frame conductor portion may have any shape (pattern) as long as it is the same as the conductor area ratio of the product conductor portion. For example, the shape of the main surface first frame conductor and the like can be the same pattern as the wiring and other patterns of the main surface product conductor and the like.
However, since the pattern of the main surface product conductor portion and the back surface product conductor portion may vary in density depending on the location, the pattern of the main surface first frame conductor portion and the back surface first frame conductor portion is biased in such a manner. When the shape is used, the thickness of the conductor layer of the main surface product conductor portion and the back surface product conductor portion may be uneven.
On the other hand, in the present invention, the main surface first frame conductor portion and the back surface first frame conductor portion are formed of a mesh-shaped conductor layer in which a large number of holes are formed. Absent. For this reason, the uniformity of the thickness of the conductor layer of the main surface product conductor portion and the back surface product conductor portion can be further improved.
[0021]
Further, another solution is a main surface conductor layer formed on the main surface side, having a main surface and a back surface, including a product portion and a frame portion surrounding the periphery of the product portion. A main surface conductor layer formed of a main surface product conductor portion formed in the portion and a main surface frame conductor portion formed in the frame portion, and a back surface conductor layer formed on the back surface side; A back conductor layer comprising a formed back product conductor portion and a back frame conductor portion formed in the frame portion, wherein the conductor area of the main surface product conductor portion is larger than the conductor area of the back product conductor portion. A method of manufacturing a small wiring board, and on the main surface side of the substrate body, while forming a main surface plating resist layer of a predetermined pattern corresponding to the main surface conductor layer, on the back surface side of the substrate body, Form a back plating resist layer of a predetermined pattern corresponding to the back conductor layer In the step of forming a resist layer, the main surface plating resist layer is composed of a main surface product resist portion formed on the product portion and a main surface frame resist portion formed on the frame portion, and the back surface plating resist layer is A back surface resist portion formed on the product portion and a back frame resist portion formed on the frame portion, wherein the main surface frame resist portion is a main surface first frame resist portion surrounding the main surface product resist portion; A main surface second frame resist portion located outside of the main surface first frame resist portion, and the back frame resist portion has a back first frame resist portion surrounding the back product resist portion; The exposure ratio of the exposed portion of the substrate main body to the area of the entire region where the main surface first frame resist portion is formed is the same as the exposure ratio of the exposed portion of the main surface side of the substrate main body to the area of the product portion. Be the same The exposed ratio of the exposed portion of the substrate main body to the entire area of the region where the back side first frame resist portion is formed is the same as the exposed ratio of the exposed portion of the rear surface side of the substrate main body to the area of the product portion. The exposed ratio of the exposed portion of the substrate main body to the area of the entire region where the main surface second frame resist portion is formed is the exposed ratio of the exposed portion on the back surface side of the substrate main body to the area of the product portion. By being made larger, the ratio of the exposed area of the back surface side of the substrate body to the exposed area of the main surface side of the substrate body is different from the exposed area of the main surface side in the product portion of the substrate body. A plating resist layer forming step that is smaller than a ratio of an exposed area on the back side in the product part, and electrolytic plating is performed on the substrate body after the plating resist layer forming step, and a main surface side of the substrate body is formed. Forming an electrolytic plating layer corresponding to the main surface conductor layer on the exposed portion of the substrate, and forming an electrolytic plating layer corresponding to the back surface conductor layer on the exposed portion on the back surface side of the substrate body. This is a method for manufacturing a wiring board.
[0022]
The present invention relates to a main surface conductor layer including a main surface product conductor portion formed in a product portion and a main surface frame conductor portion formed in a frame portion, and a back surface product conductor portion and a frame portion formed in a product portion. The present invention is applied to the manufacture of a wiring board having a back surface conductor layer composed of a formed back frame conductor portion and a conductor area of the main surface product conductor portion being smaller than a conductor area of the back surface product conductor portion. This is because in such a wiring board, as described above, the thicknesses of the main surface conductor layer and the rear surface conductor layer tend to be non-uniform.
[0023]
The manufacturing method of the present invention includes a plating resist layer forming step and an electrolytic plating step. In the plating resist layer forming step, a main surface plating resist layer having a predetermined pattern corresponding to the main surface conductor layer was formed on the main surface side of the substrate body, and on the back surface side of the substrate body, the back surface conductor layer was formed. A back plating resist layer having a predetermined pattern is formed. Specifically, the main surface plating resist layer is composed of a main surface product resist portion formed on the product portion and a main surface frame resist portion formed on the frame portion, and the back surface plating resist layer is formed on the back surface product resist formed on the product portion. It consists of a resist part and a back frame resist part formed on the frame part. The main surface frame resist portion has a main surface first frame resist portion surrounding the main surface product resist portion, and a main surface second frame resist portion located outside the main surface resist portion. A backside first frame resist section surrounding the backside product resist section is provided. The exposure ratio of the exposed portion of the substrate body to the entire area where the main surface first frame resist portion is formed (hereinafter, also referred to as the exposure ratio of the main surface first frame resist portion) is the area of the product portion. Of the exposed portion on the main surface side of the substrate main body (hereinafter, also referred to as the exposure ratio in the main surface product resist portion). In addition, the exposure ratio of the exposed portion of the substrate body in the entire area of the region where the back surface first frame resist portion is formed (hereinafter, also referred to as the exposure ratio in the back surface first frame resist portion) occupies the product area. The exposure ratio of the exposed portion on the back surface side of the substrate body (hereinafter, also referred to as the exposure ratio in the back product resist portion) is the same.
[0024]
As described above, if the exposure ratio in the main surface first frame resist portion surrounding the main surface product resist portion is the same as the exposure ratio in the main surface product resist portion, it is necessary in the electrolytic plating process to perform the main surface product resist portion. And the amount of plating per unit area required in the main surface first frame resist portion is substantially the same. Therefore, the thickness of the electrolytic plating layer is less likely to be uneven between a portion (outside portion) close to the main surface frame resist portion and a central portion away from the main surface frame resist portion in the main surface product resist portion. The uniformity of the thickness over the entire product conductor can be improved.
Similarly, if the exposure ratio in the backside first frame resist portion surrounding the backside product resist portion is the same as the exposure ratio in the backside product resist portion, in the electrolytic plating step, the per unit area required in the backside product resist portion And the amount of plating per unit area required in the backside first frame resist portion is substantially the same. For this reason, the thickness of the electrolytic plating layer is less likely to be uneven between a portion (outside portion) close to the back frame resist portion and a central portion away therefrom in the back product resist portion, and the back product conductor portion Can improve the uniformity of the thickness over the entire product part.
[0025]
Furthermore, in the plating resist layer forming step of the present manufacturing method, the exposure ratio of the exposed portion of the substrate main body to the entire area of the region where the main surface second frame resist portion is formed (hereinafter, the exposure ratio in the main surface second frame resist portion) Is also larger than the above-mentioned exposure ratio in the product resist portion, so that the ratio of the exposed area on the back surface side of the substrate main body to the exposed area on the main surface side of the substrate main body becomes larger. Is smaller than the ratio of the exposed area on the back surface side of the product portion of the substrate body to the exposed area on the main surface side.
[0026]
By doing so, the difference between the exposed area of the substrate main body in the plating resist layer on the main surface and the exposed area of the substrate main body in the plating resist layer on the back surface becomes smaller than before. Therefore, in the electroplating step, the thickness of the plating layer is unlikely to be uneven between the main surface side and the back surface side as in the related art, and the uniformity of the thickness of the main surface conductor layer and the back surface conductor layer is reduced. Can be improved.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a plan view of the wiring substrate 101 of the present embodiment as viewed from the main surface 102 side, FIG. 2 is a plan view of the wiring substrate 101 viewed from the back surface 103 side, and FIG. FIG. 1 shows a state without the solder resist layer 115 on the main surface side, and FIG. 2 shows a state without the solder resist layer 118 on the rear surface side.
As shown in FIGS. 1 and 2, the wiring board 101 has a substantially plate shape that is substantially rectangular in plan view. A product portion 105 in which a plurality of (7 × 6 = 42) individual products 105S are connected is formed substantially at the center of the wiring board 101 in a plan view, and a frame portion 107 to be discarded later is formed around the product portion 105. I have.
[0028]
Referring to the inside of the wiring board 101, as shown in FIG. 3, the wiring board 101 includes a core substrate 111 made of glass-epoxy resin at the center thereof. Note that a broken line in FIG. 3 indicates a boundary between the product unit 105 and the frame unit 107. On the main surface 102 side of the core substrate 111, a main surface side first insulating layer 113, a main surface side second insulating layer 114, and a main surface side solder resist layer 115 made of epoxy resin or the like are laminated. On the other hand, also on the back surface 103 side, a main surface side first insulating layer 116 made of epoxy resin or the like, a back surface side second insulating layer 117, and a back surface side solder resist layer 118 are laminated.
[0029]
In the wiring substrate 101, the main surface side first conductor layer 121 made of Cu is formed on the surface of the core substrate 111 on the main surface 102 side, and Cu surface is formed on the surface of the main surface side first insulating layer 113. The main surface side second conductor layer 123 made of Cu is formed. Further, on the surface of the main surface side second insulating layer 114, a main surface side third conductor layer 125 made of Cu is formed. Similarly, a back-side first conductor layer 141 made of Cu is formed on the surface of the core substrate 111 on the back side 103 side, and a back-side second conductor layer made of Cu is formed on the surface of the back side first insulating layer 116. 143 is formed, and a back-side third conductor layer 145 made of Cu is formed on the surface of the back-side second insulating layer 117.
[0030]
Further, in the core substrate 111 of the wiring substrate 101, a substantially cylindrical through-hole conductor 161 made of Cu penetrating therethrough is formed for interlayer connection. For interlayer connection, a main surface side first via conductor 163 made of Cu penetrating through the main surface side first insulating layer 113 and a main surface side second insulating layer 114 A main surface side second via conductor 165 made of Cu penetrating is formed. Similarly, a back-side first via conductor 167 made of Cu penetrating the back-side first insulating layer 116 for interlayer connection, and the back-side second insulating layer 117 penetrates the same. A back side second via conductor 169 made of Cu is formed.
[0031]
The main surface side third conductor layer 125 will be described in detail. The main surface side third conductor layer 125 is formed on the main surface product conductor portion 127 formed on the product portion 105 and the frame portion 107. And a main surface frame conductor portion 129. The main surface product conductor portion 127 has a plurality of wirings 127H and pads 127P as shown in FIG. 4 which is a plan view of the individual products 105S constituting the product portion 105 as viewed from the main surface 102 side. Is relatively narrow. Specifically, the area ratio of the conductor area of the main surface product conductor portion 127 to the entire area of the product portion 105 is about 5%. FIG. 4 shows a state where the main surface side solder resist layer 115 is not present.
[0032]
On the other hand, as shown in FIG. 1, the main surface frame conductor 129 is located outside the main surface first frame conductor 130 surrounding the main surface product conductor 127 and the main surface first frame conductor 130. And a main surface third frame conductor portion 132 surrounding the main surface second frame conductor portion 131 and forming a peripheral edge of the wiring board 101.
Among these conductors, the main surface first frame conductor 130 is formed of a mesh-shaped conductor layer in which a large number of circular holes (not shown) are formed. The area ratio of the conductor area of the main surface first frame conductor portion 130 to the entire area of the region where the main surface first frame conductor portion 130 is formed is about 5%. Therefore, the conductor area ratio of the main surface product conductor portion 127 is the same as the above.
[0033]
Also, the main surface second frame conductor portion 131 is also formed of a mesh-shaped conductor layer in which a large number of circular holes (not shown) are formed. The area ratio of the conductor area of the main surface second frame conductor portion 131 to the entire area of the region where the main surface second frame conductor portion 131 is formed is about 90%. Therefore, the conductor area ratio (about 80%) of the back product conductor portion 147 described later is set to be larger.
Further, the main surface third frame conductor 132 is formed in a solid shape. That is, the area ratio of the conductor area of the main surface third frame conductor 132 to the entire area of the region where the main surface third frame conductor 132 is formed is 100%.
The area ratio of the conductor area of the entirety of the main surface side third conductor layer 125 to the area of the wiring board 101 is about 30%.
[0034]
Next, the back side third conductor layer 145 will be described in detail. The back side third conductor layer 145 includes a back side product conductor 147 formed on the product part 105 and a back side frame conductor formed on the frame 107. 149. The back product conductor 147 has a large number of pads 147P arranged in a substantially lattice shape as shown in FIG. 5 which is a plan view of the individual product 105S constituting the product 105 as viewed from the back 103 side. The area is considerably larger than the conductor area of the main surface product conductor portion 127. Specifically, the area ratio of the conductor area of the back product conductor 147 to the area of the product part 105 is about 80%. FIG. 5 shows a state without the back side solder resist layer 118.
[0035]
On the other hand, as shown in FIG. 2, the back frame conductor 149 has a back first frame conductor 150 surrounding the back product conductor 147, and further, surrounds the back first frame conductor 150, and It has a back surface second frame conductor portion 151 that forms the periphery.
The first frame conductor 150 on the back side is formed of a mesh-shaped conductor layer in which a large number of circular holes (not shown) are formed. The area ratio of the conductor area of the rear surface first frame conductor portion 150 to the entire area of the region where the rear surface first frame conductor portion 150 is formed is about 80%. Therefore, the conductor area ratio of the back product conductor 147 is the same as the above.
[0036]
In addition, the back surface second frame conductor 151 is formed in a solid shape. That is, the area ratio of the conductor area of the rear surface second frame conductor portion 151 to the entire area of the region where the rear surface second frame conductor portion 151 is formed is 100%.
The area ratio of the conductor area of the entire back surface side third conductor layer 145 to the area of the wiring board 101 is about 85%.
[0037]
Accordingly, in this wiring board 101, the conductor area ratio of the second main frame conductor portion 131 is made larger than the conductor area ratio of the rear product conductor portion 147, so that the conductor area ratio of the third main conductor layer 125 on the main surface side is increased. Is smaller than the ratio of the conductor area of the back product conductor 147 to the conductor area of the main product conductor 127.
[0038]
In such a wiring board 101, the conductor area ratio of the main surface first frame conductor portion 130 surrounding the main surface product conductor portion 127 is the same as the conductor area ratio of the main surface product conductor portion 127 (about 5%). Therefore, the plating amount per unit area required for forming the main surface product conductor portion 127 and the plating amount per unit area required for forming the main surface first frame conductor portion 130 are substantially the same. For this reason, in the main surface product conductor portion 127, the unevenness of the thickness of the conductor layer, which is conventionally observed, is less likely to occur between a portion near the main surface frame conductor portion 129 and a central portion away therefrom, The uniformity of the thickness over the entire main surface product conductor portion 127 can be improved.
Similarly, since the conductor area ratio of the back first frame conductor portion 150 surrounding the back product conductor portion 147 is the same as the conductor area ratio of the back product conductor portion 147 (about 80%), the formation of the back product conductor portion 147 is performed. And the amount of plating per unit area required for forming the back surface first frame conductor 150 is substantially the same. Therefore, in the back product conductor 147, the unevenness of the thickness of the conductor layer, which is conventionally observed, is less likely to occur between the portion near the back frame conductor 149 and the central portion away therefrom. Thickness uniformity can be improved over the entirety of the conductor portion 147.
[0039]
Further, the conductor area ratio of the second main frame conductor portion 131 is made larger than the conductor area ratio of the rear product conductor portion 147 so that the rear surface third conductor layer 145 has a larger conductor area than the main surface third conductor layer 125. Since the ratio of the conductor area is smaller than the ratio of the conductor area of the back product conductor portion 147 to the conductor area of the main product conductor portion 127, the conductor area of the main surface side third conductor layer 125 and the back surface third conductor The difference from the conductor area of the layer 145 is smaller than that of the conventional wiring board. For this reason, the nonuniformity of the thickness of the conductor layer, which is conventionally observed, between the main surface side third conductor layer 125 and the back surface side third conductor layer 145 is less likely to occur, and the main surface side third conductor layer (main The thickness uniformity of the (surface conductor layer) 125 and the back surface side third conductor layer (back surface conductor layer) 145 can be improved.
[0040]
Further, in the present embodiment, the conductor area ratio of the main surface third frame conductor portion 132 and the conductor area ratio of the back surface second frame conductor portion 151 which constitute the peripheral portion of the wiring board 101 are both 100%. For this reason, when forming the main surface side third conductor layer 125 and the back surface side third conductor layer 145, it becomes easy to perform electrolytic plating. That is, the electrode for applying the electrolytic plating can be reliably brought into contact with the solid conductor layer forming the peripheral portion, and the current can flow, so that the electrolytic plating can be surely formed. Therefore, the uniformity of the thickness of the main surface side third conductor layer 125 and the rear surface side third conductor layer 145 can be further improved.
[0041]
Further, in the present embodiment, the main surface first frame conductor portion 130 and the back surface first frame conductor portion 150 are mesh-shaped conductor layers in which a large number of holes are formed. There is no difference in density. Therefore, the uniformity of the thickness of the conductor layers of the main surface product conductor portion 127 and the back surface product conductor portion 147 can be further improved.
[0042]
Next, a method for manufacturing the wiring board 101 will be described.
First, a double-sided copper-clad core substrate in which copper foil is adhered to both surfaces of the core substrate 111 is prepared. Then, a through hole for forming the through hole conductor 161 is formed at a predetermined position by a drill, a laser, or the like.
Next, Cu electroless plating is performed on the core substrate 111 to form an electroless plating layer on the copper foil and on the inner peripheral surface of the through hole. Further, Cu electrolytic plating is performed to form an electrolytic plating layer on the electroless plating layer. As a result, a solid plating layer is formed on the copper foil, and a substantially cylindrical through-hole conductor 161 is formed on the inner peripheral surface of the through-hole.
[0043]
Thereafter, a resin paste is printed and filled in the through-hole conductor 161 and is heated and semi-cured. Then, the excess resin swelling from the core substrate 111 is polished and removed, and further heated and cured to form a resin filler. Further, Cu electroless plating and Cu electrolytic plating are performed to form a cover plating layer on the through-hole conductor 161.
Thereafter, an etching resist layer having a predetermined pattern is formed on both surfaces of the core substrate 111, and the plating layer and the copper foil exposed from the resist layer are removed by etching. As a result, the main surface side first conductor layer 121 and the back surface side first conductor layer 141 are formed on the core substrate 111.
[0044]
Next, a semi-cured main surface side first insulating layer made of epoxy resin or the like is formed on the core substrate 111, and a mask having a predetermined pattern corresponding to a via hole for forming the main surface side first via conductor 163 is formed. Exposure is carried out using, and further developed. After that, the resultant is further heated and cured to form the main surface side first insulating layer 113 having via holes. At the same time, the backside first insulating layer 116 having a via hole for forming the backside first via conductor 167 is also formed.
[0045]
Next, an electroless plating layer is formed on the main surface side first insulating layer 113 and its via hole, and on the back surface side first insulating layer 116 and its via hole by performing Cu electroless plating. Thereafter, a plating resist layer having a predetermined pattern is formed on each of the electroless plating layers on both sides. Then, Cu electrolytic plating is performed to form electrolytic plating on the electroless plating layer exposed from the plating resist layer. Thereafter, the plating resist layer is removed, and the exposed electroless plating layer is removed by soft etching. As a result, the main surface side first via conductor 163 and the back surface side first via conductor 167 are formed, and the main surface side second conductor layer 123 and the back surface side second conductor layer 143 having a predetermined pattern are formed.
[0046]
Next, a semi-cured main surface side second insulating layer made of epoxy resin or the like is formed on the main surface side first insulating layer 113, and corresponds to a via hole for forming the main surface side second via conductor 165. Exposure is performed using a mask having a predetermined pattern, and further development is performed. Thereafter, the substrate is further heated and cured to form the main surface side second insulating layer 114 having via holes. At the same time, a back side second insulating layer 117 having a via hole for forming the back side second via conductor 169 is also formed.
[0047]
Next, an electroless plating layer is formed on the main surface side second insulating layer 114 and its via hole, and on the back surface side second insulating layer 117 and its via hole by performing Cu electroless plating.
Then, in the plating resist layer forming step, as shown in FIG. 6, a main surface plating resist layer 182 having a predetermined pattern corresponding to the main surface side third conductor layer 125 is formed on the main surface side of the substrate main body 181. Then, a back surface plating resist layer 192 having a predetermined pattern corresponding to the back surface side third conductor layer 145 is formed on the back surface side.
[0048]
Specifically, the main surface plating resist layer 182 includes a main surface product resist portion 183 formed in the product portion 105 and a main surface frame resist portion 184 formed in the frame portion 107. It comprises a back product resist 193 formed on the product part 105 and a back frame resist 194 formed on the frame 107. Among these, the main surface frame resist portion 184 is a main surface first frame resist portion 185 surrounding the main surface product resist portion 183, and the main surface first resist portion 185 located outside and surrounding the main surface first frame resist portion 185. It consists of a two-frame resist section 186. The back frame resist portion 194 includes a back first frame resist portion 195 surrounding the back product resist portion.
[0049]
The ratio of the exposed portion of the substrate main body 181 to the area of the entire region where the main surface first frame resist portion 185 is formed is the ratio of the exposed portion of the main surface side of the substrate main body 181 to the area of the product portion 105. The same as the ratio. Further, the ratio of the exposed portion of the substrate main body 181 to the area of the entire region in which the back surface first frame resist portion 195 is formed is equal to the ratio of the exposed portion of the back surface side of the substrate main body 111 to the area of the product portion 105. It is the same.
Furthermore, the exposure ratio of the exposed portion of the substrate main body 181 to the entire area of the region where the main surface second frame resist portion 186 is formed is the exposure ratio of the exposed portion on the back surface side of the substrate main body 11 to the area of the product portion 105. The ratio of the exposed area on the back surface side of the substrate main body 111 to the exposed area on the main surface side of the substrate main body 111 is larger than the exposed area on the main surface side of the product part 105 of the substrate main body 111 by the substrate main body 111. Is smaller than the ratio of the exposed area on the back surface side of the product section 105.
[0050]
Next, in the electrolytic plating step, Cu electrolytic plating is performed on the substrate main body 181 to form an electrolytic plating layer corresponding to the main surface side third conductor layer 125 on an exposed portion on the main surface side of the substrate main body 181. An electrolytic plating layer corresponding to the back side third conductor layer 145 is formed on the exposed portion on the back side of the main body 181.
After that, the main surface plating resist layer 182 and the back surface plating resist layer 192 are removed, and the exposed electroless plating layer is removed by soft etching. As a result, the main surface side second via conductor 165 and the back surface side second via conductor 169 are formed, and the main surface side third conductor layer 125 and the back surface side third conductor layer 145 having a predetermined pattern are formed.
[0051]
Next, a semi-cured main surface side solder resist layer made of an epoxy resin or the like is formed on the main surface side second insulating layer 114, exposed using a mask having a predetermined pattern, and further developed. Thereafter, the resultant is further heated and cured to form a solder resist layer 115 having a predetermined pattern on the main surface side. At the same time, a back side solder resist layer 118 having a predetermined pattern is formed.
As described above, the wiring board 101 is completed.
[0052]
According to such a manufacturing method, the exposure ratio in the main surface first frame resist portion 185 surrounding the main surface product resist portion 183 is the same as the exposure ratio in the main surface product resist portion 183. The plating amount per unit area required in the main surface product resist portion 183 and the plating amount per unit area required in the main surface first frame resist portion 185 are substantially the same. For this reason, the thickness of the electrolytic plating layer is less likely to be uneven between the portion of the main surface product resist portion 183 near the main surface frame resist portion 184 and the central portion away therefrom, and the main surface product conductor The uniformity of the thickness over the entire portion 127 can be improved.
Similarly, since the exposure ratio in the back surface first frame resist portion 195 surrounding the back product resist portion 193 is the same as the exposure ratio in the back product resist portion 193, the exposure ratio is required in the back product resist portion 193 in the electrolytic plating process. The amount of plating per unit area is approximately the same as the amount of plating per unit area required in the backside first frame resist portion 195. For this reason, the thickness of the electrolytic plating layer is less likely to be uneven between the portion near the back frame resist portion 195 and the central portion remote from the back frame resist portion 195 in the back product resist portion 193, and The uniformity of thickness can be improved over the whole.
[0053]
Further, the exposure ratio of the main surface second frame resist portion 186 is made larger than the exposure ratio of the back surface product resist portion 193, and the ratio of the exposed area of the back surface side of the substrate main body 181 to the exposed area of the main surface side of the substrate main body 181 is increased. However, the ratio of the exposed area on the back surface side of the product part 105 of the substrate main body 181 to the exposed area on the main surface side of the product part 105 of the substrate main body 181 is made smaller. For this reason, the difference between the exposed area in the main surface plating resist layer 182 and the exposed area in the back surface plating resist layer 192 becomes smaller than before. Therefore, in the electroplating step, the thickness of the plating layer is unlikely to be uneven between the main surface side third conductor layer 125 and the back surface side third conductor layer 145 as in the prior art, and the main surface side third conductor layer The uniformity of the thickness of the layer 125 and the back surface side third conductor layer 145 can be improved.
[0054]
(Embodiment 2)
Next, a second embodiment will be described. The description of the same parts as in the first embodiment will be omitted or simplified.
The wiring board of this embodiment has the same configuration as the wiring board 101 of the first embodiment.
[0055]
In the present embodiment, first, the main surface side third conductor layer 125 will be described. The area ratio of the conductor area of the main surface product conductor portion 127 to the entire area of the product portion 105 is about 3.3%.
The main surface first frame conductor portion 130 is formed of a mesh-shaped conductor layer in which a large number of rectangular holes (1967 μm × 1967 μm) are formed. The area ratio of the conductor area of the main surface first frame conductor portion 130 to the entire area where the main surface first frame conductor portion 130 is formed is about 3.3%. Therefore, also in the present embodiment, the conductor area ratio of the above-described main surface product conductor portion 127 is made the same.
[0056]
Also, the main surface second frame conductor portion 131 is also formed of a mesh-shaped conductor layer in which a large number of rectangular holes (900 μm × 900 μm) are formed. The area ratio of the conductor area of the main surface second frame conductor portion 131 to the entire area where the main surface second frame conductor portion 131 is formed is about 80%. Therefore, it is set to be larger than the conductor area ratio (about 50%) of the back product conductor portion 147 described later.
Further, the main surface third frame conductor portion 132 is formed in a solid shape as in the first embodiment. That is, the area ratio of the conductor area of the main surface third frame conductor 132 to the entire area of the region where the main surface third frame conductor 132 is formed is 100%.
The area ratio of the conductor area of the entire main-surface-side third conductor layer 125 to the area of the wiring board 101 is about 38%.
[0057]
Next, the back side third conductor layer 145 will be described. The area ratio of the conductor area of the back side product conductor portion 147 to the area of the product portion 105 is about 50%. Therefore, the ratio of the conductor area of the back product conductor 147 to the conductor area of the main product conductor 127 is about 15 times.
The back side first frame conductor portion 150 is formed of a mesh-shaped conductor layer in which a large number of rectangular holes (1500 μm × 1500 μm) are formed. The area ratio of the conductor area of the rear surface first frame conductor portion 150 to the entire area of the region where the rear surface first frame conductor portion 150 is formed is about 50%. Therefore, also in the present embodiment, the conductor area ratio of the back product conductor 147 is the same as the above.
[0058]
Further, the back surface second frame conductor portion 151 is formed in a solid shape similarly to the first embodiment. That is, the area ratio of the conductor area of the rear surface second frame conductor portion 151 to the entire area of the region where the rear surface second frame conductor portion 151 is formed is 100%.
The area ratio of the conductor area of the entire back side third conductor layer 145 to the area of the wiring board 101 is about 38%. Accordingly, the ratio of the conductor area of the back surface side third conductor layer 145 to the conductor area of the main surface side third conductor layer 125 is about one time.
[0059]
Therefore, also in the wiring board of the present embodiment, the conductor area ratio (about 80%) of the main surface second frame conductor 131 is made larger than the conductor area ratio (about 50%) of the back product conductor 147. The ratio of the conductor area of the back surface side third conductor layer 145 to the conductor area of the main surface side third conductor layer 125 (about 1) is the conductor area of the back surface product conductor portion 147 to the conductor area of the main surface product conductor portion 127. (About 15 times).
[0060]
In such a wiring board as well, the conductor area ratio of the main surface first frame conductor portion 130 surrounding the main surface product conductor portion 127 is the same as the conductor area ratio of the main surface product conductor portion 127 (about 3.3%). Therefore, the plating amount per unit area required for forming the main surface product conductor portion 127 and the plating amount per unit area required for forming the main surface first frame conductor portion 130 are substantially the same. . For this reason, in the main surface product conductor portion 127, the unevenness of the thickness of the conductor layer, which is conventionally observed, is less likely to occur between a portion near the main surface frame conductor portion 129 and a central portion away therefrom, The uniformity of the thickness over the entire main surface product conductor portion 127 can be improved.
Similarly, since the conductor area ratio of the back first frame conductor portion 150 surrounding the back product conductor portion 147 is the same as the conductor area ratio of the back product conductor portion 147 (about 50%), the formation of the back product conductor portion 147 is performed. And the amount of plating per unit area required for forming the back surface first frame conductor 150 is substantially the same. Therefore, in the back product conductor 147, the unevenness of the thickness of the conductor layer, which is conventionally observed, is less likely to occur between the portion near the back frame conductor 149 and the central portion away therefrom. Thickness uniformity can be improved over the entirety of the conductor portion 147.
[0061]
Further, the conductor area ratio (about 80%) of the second main frame conductor portion 131 is made larger than the conductor area ratio (about 50%) of the back product conductor portion 147, and the conductor of the third conductor layer 125 on the main surface side is made larger. The ratio of the conductor area of the back surface side third conductor layer 145 to the area (about 1 time) is made smaller than the ratio of the conductor area of the back surface product conductor portion 147 to the conductor area of the main surface product conductor portion 127 (about 15 times). Therefore, the difference between the conductor area of the third conductor layer 125 on the main surface side and the conductor area of the third conductor layer 145 on the back surface is smaller than that of the conventional wiring board. For this reason, the nonuniformity of the thickness of the conductor layer, which is conventionally observed, between the main surface side third conductor layer 125 and the back surface side third conductor layer 145 is less likely to occur, and the main surface side third conductor layer (main The thickness uniformity of the (surface conductor layer) 125 and the back surface side third conductor layer (back surface conductor layer) 145 can be improved.
[0062]
In addition, the conductor area ratio of the main surface third frame conductor portion 132 and the rear surface second frame conductor portion 151 which constitute the peripheral portion of the wiring board is 100%. For this reason, when forming the main surface side third conductor layer 125 and the back surface side third conductor layer 145, it becomes easy to perform electrolytic plating. That is, the electrode for applying the electrolytic plating can be reliably brought into contact with the solid conductor layer forming the peripheral portion, and the current can flow, so that the electrolytic plating can be surely formed. Therefore, the uniformity of the thickness of the main surface side third conductor layer 125 and the rear surface side third conductor layer 145 can be further improved.
[0063]
In addition, since the main surface first frame conductor portion 130 and the back surface first frame conductor portion 150 are formed of a mesh-shaped conductor layer in which a large number of holes are formed, there is no difference in density between these conductor portions. . Therefore, the uniformity of the thickness of the conductor layers of the main surface product conductor portion 127 and the back surface product conductor portion 147 can be further improved.
[0064]
Furthermore, in the present embodiment, the ratio (approximately 15 times) of the conductor area of the back product conductor 147 to the conductor area of the main product conductor 127 is 3 or more. In particular, the thickness of the conductor layer is likely to be non-uniform with the back side third conductor layer 145. However, the ratio of the conductor area of the back surface side third conductor layer 125 to the conductor area of the main surface side third conductor layer 125 (about 1 time) is reduced to 2 or less. Therefore, the uniformity of the thickness of the conductor layer between the third conductor layer 125 on the main surface side and the third conductor layer 145 on the rear surface can be further improved.
[0065]
The wiring board according to the present embodiment can be manufactured in the same manner as the wiring board 101 according to the first embodiment.
Therefore, according to such a manufacturing method, the exposure ratio in the main surface first frame resist portion 185 surrounding the main surface product resist portion 183 is the same as the exposure ratio in the main surface product resist portion 183. Thus, the plating amount per unit area required in the main surface product resist portion 183 and the plating amount per unit area required in the main surface first frame resist portion 185 become substantially the same. For this reason, the thickness of the electrolytic plating layer is less likely to be uneven between the portion of the main surface product resist portion 183 near the main surface frame resist portion 184 and the central portion away therefrom, and the main surface product conductor The uniformity of the thickness over the entire portion 127 can be improved.
Similarly, since the exposure ratio in the back surface first frame resist portion 195 surrounding the back product resist portion 193 is the same as the exposure ratio in the back product resist portion 193, the exposure ratio is required in the back product resist portion 193 in the electrolytic plating process. The amount of plating per unit area is approximately the same as the amount of plating per unit area required in the backside first frame resist portion 195. For this reason, the thickness of the electrolytic plating layer is less likely to be uneven between the portion near the back frame resist portion 195 and the central portion remote from the back frame resist portion 195 in the back product resist portion 193, and The uniformity of thickness can be improved over the whole.
[0066]
Further, the exposure ratio of the main surface second frame resist portion 186 is made larger than the exposure ratio of the back surface product resist portion 193, and the ratio of the exposed area of the back surface side of the substrate main body 181 to the exposed area of the main surface side of the substrate main body 181 is increased. However, the ratio of the exposed area on the back surface side of the product part 105 of the substrate main body 181 to the exposed area on the main surface side of the product part 105 of the substrate main body 181 is made smaller. For this reason, the difference between the exposed area in the main surface plating resist layer 182 and the exposed area in the back surface plating resist layer 192 becomes smaller than before. Therefore, in the electroplating step, the thickness of the plating layer is unlikely to be uneven between the main surface side third conductor layer 125 and the back surface side third conductor layer 145 as in the prior art, and the main surface side third conductor layer The uniformity of the thickness of the layer 125 and the back surface side third conductor layer 145 can be improved.
[0067]
In the above, the present invention has been described in accordance with the embodiments. However, the present invention is not limited to each of the first and second embodiments, and it can be said that the present invention can be appropriately modified and applied without departing from the gist thereof. Not even.
For example, in the first embodiment, the main surface first frame conductor layer 130 and the back surface first frame conductor layer 150 are formed in a mesh shape by forming circular holes, and in the second embodiment, the main surface first frame conductor Although the layer 130 and the back surface first frame conductor layer 150 are formed in a mesh shape by forming a rectangular hole, the shape of the hole need not be circular or rectangular. For example, the shape may be an elliptical shape, a polygonal shape, or the like. Even in this case, the above-described effects can be obtained as long as the conductor layer is formed in a mesh shape as a whole.
[0068]
Further, in the first and second embodiments, the main surface second frame conductor portion 131 has a square shape surrounding the main surface first frame conductor portion 130, but is outside the main surface first frame conductor portion 130. Any shape (pattern) can be used as long as it is located.
In the first and second embodiments, the multilayer wiring board in which three conductor layers and three insulating layers are alternately formed on both surfaces of the core substrate 111 is shown. However, a multilayer wiring board may be used. .
[0069]
Further, in the first and second embodiments, the present invention relates to the main surface side third conductor layer 125 located closest to the main surface 102 of the wiring board 101 and the back surface side third conductor layer 145 located closest to the back surface 103. However, the present invention can also be applied to the internal conductor layer. For example, in the main surface side second conductor layer 123 and the main surface side second conductor layer 143, when the conductor area of the main surface product conductor is smaller than the conductor area of the rear surface product conductor, the present invention is applied. can do.
[Brief description of the drawings]
FIG. 1 is a plan view seen from a main surface side of a wiring board according to an embodiment.
FIG. 2 is a plan view of the wiring substrate according to the embodiment as viewed from the back surface side.
FIG. 3 is a partial longitudinal sectional view showing the vicinity of a peripheral edge of the wiring board according to the embodiment;
FIG. 4 is a plan view of an individual product of the wiring board according to the embodiment as viewed from the main surface side.
FIG. 5 is a plan view of an individual product of the wiring board according to the embodiment as viewed from the back surface side.
FIG. 6 relates to a method of manufacturing a wiring board according to an embodiment, and shows a state where a main surface plating resist layer and a back surface plating resist layer are formed on a substrate body having a main surface side second insulating layer and a back surface second insulating layer. FIG.
FIG. 7 is a plan view seen from a main surface side of a wiring board according to a conventional technique.
FIG. 8 is a plan view of a wiring substrate according to the related art as viewed from the back surface side.
FIG. 9 is a plan view of an individual product of a wiring board according to the related art, viewed from the main surface side.
FIG. 10 is a plan view of an individual product of a wiring board according to the related art, viewed from the back surface side.
[Explanation of symbols]
101 Wiring board
102 main surface
103 back
105 Product Department
107 Frame
121 Main surface side first conductor layer
123 Main surface side second conductor layer
125 Main surface side third conductor layer
127 Main surface product conductor
129 Main surface frame conductor
130 Main surface first frame conductor
131 Main surface second frame conductor
132 Main surface third frame conductor
141 back side first conductor layer
143 Back Side Second Conductive Layer
145 back surface side third conductor layer
147 Back product conductor
149 Back frame conductor
150 Back side first frame conductor
151 back surface second frame conductor

Claims (5)

主面と裏面を有し、製品部とこの製品部の周囲を取り囲む枠部とからなり、
上記主面側に形成された主面導体層であって、上記製品部に形成された主面製品導体部と上記枠部に形成された主面枠導体部とからなる主面導体層と、
上記裏面側に形成された裏面導体層であって、上記製品部に形成された裏面製品導体部と上記枠部に形成された裏面枠導体部とからなる裏面導体層と、
を備え、
上記主面製品導体部の導体面積が、上記裏面製品導体部の導体面積よりも小さい
配線基板であって、
上記主面枠導体部は、上記主面製品導体部を取り囲む主面第１枠導体部と、この主面第１枠導体部よりも外側に位置する主面第２枠導体部とを有し、
上記裏面枠導体部は、上記裏面製品導体部を取り囲む裏面第１枠導体部を有し、
上記主面第１枠導体部が形成された領域全体の面積に占める上記主面第１枠導体部の導体面積の面積率が、上記製品部の面積に占める上記主面製品導体部の導体面積の面積率と同一とされ、
上記裏面第１枠導体部が形成された領域全体の面積に占める上記裏面第１枠導体部の導体面積の面積率が、上記製品部の面積に占める上記裏面製品導体部の導体面積の面積率と同一とされ、
上記主面第２枠導体部が形成された領域全体の面積に占める上記主面第２枠導体部の導体面積の面積率が、上記製品部の面積に占める上記裏面製品導体部の導体面積の面積率よりも大きくされることにより、上記主面導体層の導体面積に対する上記裏面導体層の導体面積の割合が、上記主面製品導体部の導体面積に対する上記裏面製品導体部の導体面積の割合よりも小さくされている
配線基板。It has a main surface and a back surface, and consists of a product part and a frame part surrounding the periphery of this product part,
A main surface conductor layer formed on the main surface side, a main surface conductor layer including a main surface product conductor portion formed on the product portion and a main surface frame conductor portion formed on the frame portion,
A back conductor layer formed on the back surface side, a back conductor layer including a back product conductor portion formed on the product portion and a back frame conductor portion formed on the frame portion,
With
The conductor area of the main surface product conductor portion is a wiring board smaller than the conductor area of the back surface product conductor portion,
The main surface frame conductor has a main surface first frame conductor surrounding the main surface product conductor, and a main surface second frame conductor located outside the main surface first frame conductor. ,
The back frame conductor has a back first frame conductor surrounding the back product conductor,
The area ratio of the conductor area of the main surface first frame conductor to the area of the entire area where the main surface first frame conductor is formed is the conductor area of the main surface product conductor to the product area. Is the same as the area ratio of
The area ratio of the conductor area of the back surface first frame conductor to the area of the entire region where the back surface first frame conductor is formed is the area ratio of the conductor area of the back surface product conductor to the area of the product part. Is the same as
The area ratio of the conductor area of the main surface second frame conductor to the area of the entire region where the main surface second frame conductor is formed is the conductor area of the back product conductor to the area of the product part. By being made larger than the area ratio, the ratio of the conductor area of the back surface conductor layer to the conductor area of the main surface conductor layer is the ratio of the conductor area of the back surface product conductor portion to the conductor area of the main surface product conductor portion. Wiring board that is smaller than. 請求項１に記載の配線基板であって、
前記主面製品導体部の導体面積に対する前記裏面製品導体部の導体面積の割合が、３以上である配線基板において、
前記主面導体層の導体面積に対する前記裏面導体層の導体面積の割合が、２以下とされている
配線基板。The wiring board according to claim 1,
In a wiring board in which the ratio of the conductor area of the back product conductor to the conductor area of the main surface product conductor is 3 or more,
A wiring board, wherein a ratio of a conductor area of the back surface conductor layer to a conductor area of the main surface conductor layer is 2 or less. 請求項１または請求項２に記載の配線基板であって、
前記主面枠導体部は、上記配線基板の周縁をなす主面第３枠導体部を有し、
前記裏面枠導体部は、上記配線基板の周縁をなす裏面第２枠導体部を有し、
上記主面第３枠導体部が形成された領域全体の面積に占める上記主面第３枠導体部の導体面積の面積率、及び、上記裏面第２枠導体部が形成された領域全体の面積に占める上記裏面第２枠導体部の導体面積の面積率は、いずれも１００％とされている
配線基板。The wiring board according to claim 1 or 2, wherein
The main surface frame conductor has a main surface third frame conductor that forms a periphery of the wiring board,
The backside frame conductor has a backside second frame conductor that forms a periphery of the wiring board,
The area ratio of the conductor area of the third main frame conductor to the entire area where the third main frame conductor is formed, and the area of the entire area where the second rear frame conductor is formed The wiring board, wherein the area ratio of the conductor area of the second frame conductor portion on the back side to the whole is 100%. 請求項１〜請求項３のいずれか一項に記載の配線基板であって、
前記主面第１枠導体部及び前記裏面第１枠導体部は、いずれも多数の孔が形成されたメッシュ状の導体層からなる
配線基板。The wiring board according to any one of claims 1 to 3, wherein
The wiring substrate, wherein the main surface first frame conductor portion and the back surface first frame conductor portion are each formed of a mesh-shaped conductor layer in which a large number of holes are formed. 主面と裏面を有し、製品部とこの製品部の周囲を取り囲む枠部とからなり、
上記主面側に形成された主面導体層であって、上記製品部に形成された主面製品導体部と上記枠部に形成された主面枠導体部とからなる主面導体層と、
上記裏面側に形成された裏面導体層であって、上記製品部に形成された裏面製品導体部と上記枠部に形成された裏面枠導体部とからなる裏面導体層と、
を備え、
上記主面製品導体部の導体面積が、上記裏面製品導体部の導体面積よりも小さい
配線基板の製造方法であって、
基板本体の上記主面側に、上記主面導体層に対応した所定パターンの主面メッキレジスト層を形成すると共に、上記基板本体の上記裏面側に、上記裏面導体層に対応した所定パターンの裏面メッキレジスト層を形成するメッキレジスト層形成工程であって、
上記主面メッキレジスト層は、上記製品部に形成する主面製品レジスト部と上記枠部に形成する主面枠レジスト部とからなり、
上記裏面メッキレジスト層は、上記製品部に形成する裏面製品レジスト部と上記枠部に形成する裏面枠レジスト部とからなり、
上記主面枠レジスト部は、上記主面製品レジスト部を取り囲む主面第１枠レジスト部と、この主面第１枠レジスト部よりも外側に位置する主面第２枠レジスト部とを有し、
上記裏面枠レジスト部は、上記裏面製品レジスト部を取り囲む裏面第１枠レジスト部を有し、
上記主面第１枠レジスト部が形成された領域全体の面積に占める上記基板本体の露出部の露出割合が、上記製品部の面積に占める上記基板本体の主面側の露出部の露出割合と同一とされ、
上記裏面第１枠レジスト部が形成された領域全体の面積に占める上記基板本体の露出部の露出割合が、上記製品部の面積に占める上記基板本体の裏面側の露出部の露出割合と同一とされ、
上記主面第２枠レジスト部が形成された領域全体の面積に占める上記基板本体の露出部の露出割合が、上記製品部の面積に占める上記基板本体の裏面側の露出部の露出割合よりも大きくされることにより、上記基板本体の主面側の露出面積に対する上記基板本体の裏面側の露出面積の割合が、上記基板本体の製品部における主面側の露出面積に対する上記基板本体の製品部における裏面側の露出面積の割合よりも小さくされている
メッキレジスト層形成工程と、
上記メッキレジスト層形成工程後の上記基板本体に電解メッキを施し、上記基板本体の主面側の露出部に上記主面導体層に対応した電解メッキ層を形成すると共に、上記基板本体の裏面側の露出部に上記裏面導体層に対応した電解メッキ層を形成する電解メッキ工程と、
を備える配線基板の製造方法。It has a main surface and a back surface, and consists of a product part and a frame part surrounding the periphery of this product part,
A main surface conductor layer formed on the main surface side, a main surface conductor layer including a main surface product conductor portion formed on the product portion and a main surface frame conductor portion formed on the frame portion,
A back conductor layer formed on the back surface side, a back conductor layer including a back product conductor portion formed on the product portion and a back frame conductor portion formed on the frame portion,
With
A method for manufacturing a wiring board, wherein the conductor area of the main surface product conductor is smaller than the conductor area of the back surface product conductor,
A main surface plating resist layer having a predetermined pattern corresponding to the main surface conductor layer is formed on the main surface side of the substrate body, and a back surface of a predetermined pattern corresponding to the back surface conductor layer is formed on the back surface side of the substrate body. A plating resist layer forming step of forming a plating resist layer,
The main surface plating resist layer includes a main surface product resist portion formed in the product portion and a main surface frame resist portion formed in the frame portion,
The back plating resist layer is composed of a back product resist portion formed on the product portion and a back frame resist portion formed on the frame portion,
The main surface frame resist portion includes a main surface first frame resist portion surrounding the main surface product resist portion, and a main surface second frame resist portion located outside the main surface first frame resist portion. ,
The backside frame resist section has a backside first frame resist section surrounding the backside product resist section,
The exposure ratio of the exposed portion of the substrate main body to the area of the entire region where the main surface first frame resist portion is formed is the same as the exposure ratio of the exposed portion of the main surface side of the substrate main body to the area of the product portion. Are the same,
The exposed ratio of the exposed portion of the substrate main body to the entire area of the region where the back side first frame resist portion is formed is the same as the exposed ratio of the exposed portion of the rear surface side of the substrate main body to the area of the product portion. And
The exposure ratio of the exposed portion of the substrate main body to the area of the entire region where the main surface second frame resist portion is formed is larger than the exposure ratio of the exposed portion of the back surface side of the substrate main body to the area of the product portion. The ratio of the exposed area on the back surface side of the substrate main body to the exposed area on the main surface side of the substrate main body is increased, so that the product area of the substrate main body with respect to the exposed area on the main surface side of the product area of the substrate main body is increased. A plating resist layer forming step that is smaller than the ratio of the exposed area on the back side in
Electroplating is performed on the substrate body after the plating resist layer forming step, and an electrolytic plating layer corresponding to the main surface conductor layer is formed on an exposed portion on a main surface side of the substrate body, and a back surface side of the substrate body is formed. An electrolytic plating step of forming an electrolytic plating layer corresponding to the backside conductor layer on the exposed portion of,
The manufacturing method of the wiring board provided with.
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JP2007180212A (en) * 2005-12-27 2007-07-12 Ngk Spark Plug Co Ltd Manufacturing method and intermediate product of wiring board
JP2009290081A (en) * 2008-05-30 2009-12-10 Ngk Spark Plug Co Ltd Intermediate product of multilayer wiring board, and method of manufacturing multilayer wiring board
JP2012019027A (en) * 2010-07-07 2012-01-26 Ngk Spark Plug Co Ltd Intermediate product and manufacturing method of wiring board
JP2012049296A (en) * 2010-08-26 2012-03-08 Sharp Corp Mounting method for semiconductor light-emitting element
JP2013118418A (en) * 2009-08-31 2013-06-13 Samsung Electro-Mechanics Co Ltd Printed circuit board panel
WO2018211753A1 (en) * 2017-05-16 2018-11-22 住友電気工業株式会社 Printed wiring board base material and method for manufacturing printed wiring board
CN110073729A (en) * 2016-12-15 2019-07-30 凸版印刷株式会社 The manufacturing method of wiring substrate, multi-layered wiring board and wiring substrate

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007180212A (en) * 2005-12-27 2007-07-12 Ngk Spark Plug Co Ltd Manufacturing method and intermediate product of wiring board
JP2009290081A (en) * 2008-05-30 2009-12-10 Ngk Spark Plug Co Ltd Intermediate product of multilayer wiring board, and method of manufacturing multilayer wiring board
JP2013118418A (en) * 2009-08-31 2013-06-13 Samsung Electro-Mechanics Co Ltd Printed circuit board panel
JP2012019027A (en) * 2010-07-07 2012-01-26 Ngk Spark Plug Co Ltd Intermediate product and manufacturing method of wiring board
JP2012049296A (en) * 2010-08-26 2012-03-08 Sharp Corp Mounting method for semiconductor light-emitting element
US9048407B2 (en) 2010-08-26 2015-06-02 Sharp Kabushiki Kaisha Mounting method for semiconductor light emitter using resist with openings of different sizes
CN110073729A (en) * 2016-12-15 2019-07-30 凸版印刷株式会社 The manufacturing method of wiring substrate, multi-layered wiring board and wiring substrate
WO2018211753A1 (en) * 2017-05-16 2018-11-22 住友電気工業株式会社 Printed wiring board base material and method for manufacturing printed wiring board

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