JPH10270630A - Substrate for semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a fine multilayer wiring with high accuracy, easily form a thin structure, and allow high density wiring, by providing external connecting leads extending to the outside from a part between a first and second conductor circuits. SOLUTION: The substrate comprises a sheet-like metal-made lead frame 1, first conductor circuit 2 selectively formed on one surface of the lead frame 1, second conductor circuit 3 which is formed on the other surface of the frame 1 and electrically connected to the first circuit 2, protective layer 4 for protecting both circuits 2, 3, and external connecting leads 5 extending to the outside from a part between the conductor circuits 2, 3, which are formed from a conductor layer 6 and insulation layer 7 and mutually electrically connected through part of the frame 1. This forms a fine multilayered wiring with high accuracy and high density wiring in view of the structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device substrate having a printed wiring board formed on a lead frame by a build-up method, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, in a technique of forming a conductor layer as a wiring layer of a semiconductor device substrate, a plurality of insulating substrates having a conductor layer are previously laminated collectively via an adhesive, and thereafter, holes are formed by drilling. However, there is a method of performing through-hole plating. However, since this method uses a thin copper foil when forming a fine pattern, it has a problem of increasing cost. Also, since via holes are formed by drilling, there is a limit to miniaturization of via holes,
There is a problem that the reliability in the case of multilayering is inferior.

On the other hand, in recent years, a build-up method has been known as a method of manufacturing a semiconductor device substrate that can solve such a problem. The build-up method is a method capable of forming a fine multilayer wiring with high precision. Specifically, the build-up method is a technique in which conductor layers and insulating layers are sequentially and alternately formed on a support substrate.

Here, as a method for forming the conductor layer, plating, vapor deposition, sputtering and the like can be appropriately used. On the other hand, the method of forming the insulating layer is, for example, (a) a method of applying a photosensitive insulating resin and removing the resin in the via hole portion by exposure and development,
Alternatively, (b) a method of applying an insulating resin having no photosensitivity and removing the resin in the via hole portion by a method such as laser processing can be appropriately used.

[0005] As described above, the build-up method forms fine via holes by exposure and development or laser processing, so that the above-mentioned problem of drilling can be solved.
Fine multilayer wiring can be formed with high accuracy without increasing the cost. In addition, since the insulating layer is formed of an insulating resin that does not contain glass cloth, it is possible to form a thin insulating layer with high accuracy, and it is possible to reduce the thickness.

A substrate for a semiconductor device in which a print circuit portion is formed on a lead frame by using this type of build-up method is disclosed, for example, in Japanese Patent Laid-Open No. 3-136269. This publication discloses a form in which a printed circuit unit is built up on one surface of a lead frame. Also, although different from the build-up method,
Japanese Patent Publication No. 160784 discloses a form in which conductor layers are collectively formed on both surfaces of a lead frame which has been processed in advance.

[0007]

However, the semiconductor device substrate and the manufacturing method thereof as described above have the following problems.

First, the configuration disclosed in Japanese Patent Application Laid-Open No. 3-136269 is built up on one side, and has a problem that the capacity of the wiring is small and high-density wiring cannot be expected. In addition, since the printed circuit portion is present only on one side, there is a problem that warpage is likely to occur. Further, when a force is applied to the lead frame, there is a problem that the lead frame and the conductor layer (build-up layer) are easily peeled off. In particular, when the printed circuit portion and the lead frame are connected at the outer peripheral portion of the printed circuit portion in order to improve the wiring efficiency of the printed circuit portion, the connection area between the printed circuit portion and the lead frame is reduced, and thus the problem of peeling is caused. Is remarkable.

On the other hand, the form disclosed in Japanese Patent Laid-Open No. 3-160784 uses a lead frame which has been processed in advance. For this reason, force is applied at the time of lamination, the leads are likely to be deformed, there is a problem that the insulation between the leads is reduced, and the connection reliability with the printed circuit is lacking. Further, since the build-up method is not used, there is a problem that the advantage cannot be used.

The present invention has been made in consideration of the above-mentioned circumstances, takes advantage of the build-up method that fine multi-layered wiring can be formed with high precision and can be easily thinned, and high-density wiring is structurally possible. It is an object of the present invention to provide a semiconductor device substrate and a method of manufacturing the same which can be expected.

A second object of the present invention is to provide a highly reliable electrical connection between wirings on both surfaces of a lead frame, and furthermore, a semiconductor device which is hardly peeled off even when a force is applied to the lead frame. It is to provide a substrate and a method for manufacturing the same.

[0012]

The gist of the present invention relates to the structure and manufacturing method of a substrate for a semiconductor device, and in particular, at least two electrodes electrically connected to each other with a lead frame sandwiched from both sides by a build-up method. In the configuration having the conductor circuits of layers.

The printed circuit section (circuit area)
An insulating layer and a conductor layer formed by a build-up method, respectively. The lead frame is provided so as to extend outside the print circuit section. In the present specification, a region of the lead frame sandwiched between the conductor circuits of two layers is referred to as an internal lead frame, and a region located outside the internal lead frame and exposed to the outside is an external lead frame. The area where these internal and external lead frames are combined is called an external connection lead frame. Also,
The leadframe may be used in part for interconnection between conductor circuits on both sides.

Further, it is preferable that the external connection lead has a thin portion partially thinned by half etching in order to reduce stress applied to the connection portion between the lead and the printed circuit portion. Supplementally, the structure of the present invention has formed conductor circuits on both sides of the lead frame,
Compared with the conventional structure having a conductor circuit on only one surface, it has an advantage that peeling is less likely to occur. However, when force is applied to the lead frame, it cannot be guaranteed that peeling is complete. Therefore, it is preferable to provide the external connection lead with a stress relaxation function in this way from the viewpoint of improving the reliability regarding peeling.

Now, based on the gist of the present invention, specifically, the following means are taken.

The invention according to claim 1 is a first conductor circuit in which a lead frame and an insulating layer and a wiring layer formed by solidifying resin are alternately laminated on one surface of the lead frame. And a second conductive circuit electrically connected to the first conductive circuit, wherein an insulating layer and a wiring layer formed by solidifying resin are alternately laminated on the other surface of the lead frame. A semiconductor device substrate including an external connection lead formed to extend outward from a portion of the lead frame sandwiched between the first conductor circuit and the second conductor circuit. is there.

According to a second aspect of the present invention, in the semiconductor device substrate according to the first aspect, the first and second conductive circuits are electrically connected to each other via a part of a lead frame. It is a substrate for a connected semiconductor device.

Further, according to a third aspect of the present invention, in the semiconductor device substrate according to the first or second aspect, the first and second leads are used as the external connection leads.
Semiconductor substrate selectively half-etched at a position near the conductor circuit of FIG.

The invention corresponding to claim 4 is (A)
Selectively forming a resist on one surface of a sheet-like metal material having a circuit region, an internal lead region, and an external lead region sequentially on the outer peripheral side; and (B) forming a resist on one surface of the metal material. A step of selectively forming a stopper conductor layer including a layer serving as an etching stopper on the surface where the resist is not formed in the circuit area and the internal lead area; and (C) after forming the stopper conductor layer, the resist is removed. And (D) selectively forming an insulating layer on one surface of the metal material and on the stopper conductor layer in the circuit region and the internal lead region so as to partially expose the stopper layer. And (E) a step of selectively forming a conductor layer on the insulating layer and on the stopper conductor layer exposed by non-selection, and (F) an uppermost insulating layer and an uppermost conductor. A step of selectively forming an insulating layer so as to partially expose the conductor layer, and (G) selectively forming a conductor layer on the uppermost insulating layer and on the conductor layer exposed by non-selection. And (H) repeating (F) to (G) a predetermined number of times to form a first laminated structure of an insulating layer and a conductor layer in the circuit region and the internal lead region. (I) a step of removably forming a protective layer on the outermost surface of the first laminated structure, and (J) selectively etching the sheet-shaped metal material in the inner and outer lead regions to the outside. Forming a connecting lead and removing the metal material in the circuit region;
(K) selectively forming an insulating layer on the insulating layer and the stopper conductor layer exposed by removing the metal material so as to partially expose the stopper conductor layer;
(L) a step of selectively forming a conductive layer on the insulating layer and on the stopper conductive layer exposed by non-selection; and (M) forming a conductive layer on the uppermost insulating layer and the uppermost conductive layer. (N) selectively forming an insulating layer so as to partially expose, and (N) selectively forming a conductive layer on the uppermost insulating layer and the non-selectively exposed conductive layer; O)
Forming a second laminated structure of an insulating layer and a conductor layer in the circuit region by repeating the steps (M) to (N) up to a predetermined number of times.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device substrate according to the fourth aspect.
An insulating layer is used instead of the respective resists in the respective steps (A) and (B), the step (C) is omitted, and one surface of the metal material in the step (D) is replaced. A method for manufacturing a substrate for a semiconductor device using the insulating layer.

According to a sixth aspect of the invention, in the method of manufacturing a semiconductor device substrate according to the fourth aspect, in the step (J), the metal material of the circuit region, at least the stopper conductor layer, is formed. This is a method of manufacturing a semiconductor device substrate using the metal material instead of the respective stopper conductor layers in the respective steps (K) and (L), which are selectively removed so as not to be exposed.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device substrate according to the sixth aspect, wherein:
An insulating layer is used instead of the resist in each of the steps (A) and (B), the step (C) is omitted, and one surface of the metal material is replaced in the step (D). A method for manufacturing a substrate for a semiconductor device using the insulating layer.

The invention according to claim 8 is the method for manufacturing a substrate for a semiconductor device according to claim 6 or claim 7, wherein the step (A) is preceded by the step of A method for manufacturing a substrate for a semiconductor device, comprising a step of half-etching in advance a portion to be removed in the step (J).

Further, the invention according to claim 9 is the method for manufacturing a semiconductor device substrate according to any one of claims 4 to 8, wherein the external connection lead in the vicinity of the internal lead region is formed. A method of manufacturing a semiconductor device substrate, which includes a step of selectively performing half etching.

(Terms) Next, the technical terms (elements) used in the present invention as described above will be described. The sheet metal material is copper alloy, 42 alloy (42 wt% Ni, balance Fe)
An iron-Ni alloy represented by, for example, is used, and a copper alloy is particularly preferable because it has excellent thermal conductivity and low electric resistance.
The thickness is preferably about 0.1 mm to 0.15 mm.

As the resist, a dry film, a liquid resist or an electrodeposition resist which has been generally used conventionally can be used. In particular, when forming a fine conductor pattern, a liquid resist or an electrodeposition resist is desirable. In consideration of the compatibility between the conventional process using a dry film and the exposure original plate, a negative resist is preferable among these resists.

Here, for the dry film, for example, Liston (trade name, manufactured by DuPont), laminar (trade name, manufactured by Dynachem), Fotec (trade name, manufactured by Hitachi Chemical Co., Ltd.) and the like can be used.

As the liquid resist, for example, KPR (trade name, manufactured by Kodak), EPPR, PMER (trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.), AZ (trade name, manufactured by Hoechst Japan) and the like can be used. I have.

As the electrodeposition resist, Sonne (trade name, manufactured by Kansai Paint), oligo (trade name, manufactured by Nippon Petrochemical Co., Ltd.), Photo ED (trade name, manufactured by Nippon Paint) and the like can be used.

As a coating method, a method depending on the suitability of the resist, such as dipping, screen printing, spin coating, or the like, is used.

The stopper layer is made of a material which serves as an etching stopper layer when etching a metal material for forming leads. The material of the stopper layer should be a conductive material, has a strong adhesion, and serves as a stopper layer at the time of etching the metal material, and it is desirable that the forming process on the metal material is simple. It is appropriately selected in relation to the metal material and the etching solution. As a forming method, a method such as plating, vapor deposition, sputtering or coating can be appropriately used.

As the material of the stopper layer, for example, gold, platinum, nickel, palladium, solder, copper paste or the like can be appropriately used.

Gold is preferable because it has a high stopper effect against various kinds of etching solutions.

The solder can be easily formed by plating. When the metal material is a copper alloy, the copper alloy of the metal material is etched by etching with an alkaline etching solution containing copper ammonium complex ions as a main component, but the solder layer becomes a stopper layer.

The thickness TS of the stopper layer is defined as TE ≧ TS ≧ T, where TE is the thickness of the metal material to be etched, VA is the etching rate, and VB is the etching rate of the stopper layer.
It is preferable to set E × (VB / VA). It is not preferable to set the thickness of the stopper layer to be equal to or more than the thickness TE of the metal material to be etched because it takes time to form the stopper layer. Also, TS ≧ TE × (VB / VA)
If set to, the stopper layer remains even if it is locally over-etched due to variations in etching, so that there is no adverse effect.

The conductor circuit (conductor layer) is formed on the stopper layer.
It is formed by electrolytic Cu plating. The formation process of the conductor circuit is a conventional subtractive method, a semi-additive method,
Although a full additive method or the like can be applied, since there is a stopper layer, a conductive circuit can be easily formed by electrolytic Cu plating.

An example of the conventional subtractive method, semi-additive method, full additive method, etc. will be described.

In the subtractive method, a thin copper layer of about 0.2 μm is formed by electroless plating, sputtering, etc., and then electrolytic copper plating of about 10 μm is applied to the entire surface. Then, an etching resist such as a liquid resist is applied and dried, and then an etching pattern is formed by exposure and development, copper is etched, and then the resist is peeled off.

In the semi-additive method, a thin copper layer having a thickness of, for example, about 0.2 μm is formed by electroless plating, sputtering, or the like, and a plating resist such as a dry film is coated. Remove the resist. And 10 to the wiring pattern part
Electrolytic copper plating with a thickness of about 20 μm is applied. Further, after the resist is stripped, the thin copper layer is removed by etching.

In the full additive method, after applying a catalyst and forming a plating resist, a wiring pattern is formed by electroless plating on the wiring pattern portion.

In the step of forming external connection leads from a sheet-like metal material, the surface on which the conductor layer is formed is protected and etched. It should be noted that etching may be performed from one side, or only the conductor layer may be protected and etching may be performed from one side simultaneously.

On the other hand, as the step of forming the insulating layer, screen printing, curtain coating, or the like is used. The material of the insulating layer is preferably a photosensitive insulating resin from the viewpoint of ease of processing,
For example, Provicoat 5000 (trade name, manufactured by Nippon Paint Co., Ltd.) is preferably used.

As the insulating resin, an epoxy resin-based or acrylic resin-based insulating resin or the like can be used. It should be noted that a photosensitive resin is desirable because of the simplicity of the processing process, but is not particularly limited. For example, even a material having no photosensitivity can be formed into a desired shape by using a method such as excimer laser or plasma for processing.

As a method for protecting the conductive layer forming surface, there are a method of using a liquid resist, a dry film, and a tape individually, or a method of using them in combination.

The step of half-etching a sheet-like metal material in advance will also be described. Prior to the step (A), it is preferable to perform half-etching in advance on a portion of one surface of the sheet-shaped metal material, which is to be removed by etching later. Necessary portions such as external connection lead portions and connection portions between both surfaces are protected by resist, and exposed and removed portions can be half-etched. The half-etched portion may be entirely exposed, but for example, a resist may be provided intermittently. This preliminary half-etching process can reduce the amount of etching during the subsequent etching, and can reduce the amount of side etching. Therefore, a multi-pin lead frame that requires a particularly fine pitch can be formed with higher accuracy. Have.

The step of performing half-etching on the external connection lead will also be described.

In the step of forming external connection leads from a sheet-like metal material, a slit opening of a resist having a width smaller than a desired half-etching depth is formed in a portion to be subjected to half-etching. By doing
A desired half-etched shape can be formed in the same etching process. The half-etched shape can be controlled by adjusting the width of the resist opening. The half-etched portion for relaxing the stress may be formed, for example, in the half-etching process preceding the process (A), at the same time as the half-etched portion removed in the subsequent process.

The structure of the semiconductor device substrate may be a structure in which a single semiconductor chip is mounted or a structure in which a plurality of semiconductor chips are mounted. The print circuit section
Any number of layers required for wiring may be formed, and a power supply layer or a ground layer may be provided.

(Operation) Therefore, the invention corresponding to claim 1 has the advantages of the build-up method in which fine multi-layered wiring can be formed with high precision and thickness can be easily reduced by taking the above means. In addition to this, the conductor circuit on only one side is utilized, and in addition to this, by providing these conductor circuits on both sides of the lead frame, further densification is aimed at, so it is expected that high-density wiring is also expected in the structure it can.

Further, in the invention according to claim 2, since the electrical connection is made through a part of the lead frame and a part separated from the external connection lead, one surface of the lead frame is formed. The connection between the conductor circuit of the other side and the conductor circuit on the other surface can be made with a shallow via hole,
Electrical connection between wirings on both sides of the lead frame can be realized with high reliability.

Further, the invention according to claim 3 is characterized in that the external connection leads near the outside of the printed circuit portion are half-etched and formed to be thin, so that even when a force is applied to the lead frame, the half-etched portions are formed. The stress can be relaxed, and thus peeling can be made difficult.

According to the fourth aspect of the invention, a conductor circuit is formed on one surface of the metal material by a build-up method, the metal material is etched, and the conductor circuit is formed on the other surface by the build-up method. Claim 1 to form a circuit.
As in the case of the operation corresponding to (1), a semiconductor device substrate that can be expected to provide high-density wiring on the structure in addition to the advantage of the build-up method can be manufactured.

According to a fifth aspect of the present invention, in addition to the same effect as the fourth aspect, an insulating layer is directly formed selectively by replacing the lowermost layer of the first conductor circuit with a resist. Therefore, the manufacturing process can be simplified.

According to a sixth aspect of the present invention, in addition to the same function as the fourth aspect, the first and second conductor circuits are electrically connected to each other by a part of the lead frame. Therefore, similarly to the operation corresponding to claim 3, electrical connection between the wirings on both surfaces of the lead frame can be realized with high reliability.

Further, in the invention according to claim 7, in addition to the same operation as the operation according to claim 6, the lowermost layer of the first conductor circuit is replaced with a resist, and an insulating layer is directly formed. Therefore, the manufacturing process can be simplified.

Further, in the invention of claim 8, in addition to the same effect as the effect corresponding to claim 6 or claim 7, prior to the step (A), a step of half-etching the metal material portion to be removed later is performed. Etching the metal material to perform
When forming the external connection leads and the like, the etching amount can be small, and the side etching amount can be suppressed. Therefore, the processing accuracy of the external connection leads can be improved.

According to a ninth aspect of the present invention, in addition to the same function as that of any one of the fourth to eighth aspects, the vicinity of the external connection lead outside the print circuit portion is reduced.
Since the step of half-etching is included, it is possible to manufacture a substrate for a semiconductor device in which peeling does not easily occur between the printed circuit portion and the lead frame even when a force is applied to the lead frame.

[0058]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 2 is a plan view showing the configuration of the semiconductor device substrate according to the embodiment of the present invention, and FIG. 2 is a sectional view taken along the line II-II of FIG. This semiconductor device substrate includes a lead frame 1 formed of a sheet metal material, and a first laminated structure (conductor circuit) 2 selectively formed on one surface of the lead frame 1.
And a second laminated structure (conductor circuit) 3 which is electrically connected to the first laminated structure 2 and selectively formed on the other surface of the lead frame 1, and both laminated structures 2 and 3 A protective layer for protection; and an external connection lead formed to extend outward from a portion of the lead frame that is sandwiched between the first and second laminated structures. I have. Since the protective layer 4 is thin, as shown in FIG. 1, the lower conductor 6 is seen through. Here, the first and second laminated structures are formed of the conductor layer 6 and the insulating layer 7 and are electrically connected to each other via a part of the lead frame 1.

Next, a method of manufacturing such a semiconductor device substrate will be described.

0.15 mm as a sheet-like metal material
Thick copper alloy 11 is well cleaned. After the copper alloy 11 is dried, a tape 12 having resistance to a chemical solution used in the subsequent plating process, etching process and the like is attached to the other surface.

Then, a photosensitive dry film 13 (laminar; trade name:
Dynamism) is attached. In addition, dry film 1
For 3, for example, a layer having a thickness of about 20 to 50 μm can be applied, and a layer having a thickness larger than the thickness of the conductor layer in a later step is preferable.

Thereafter, the dry film 13 is exposed,
After development, as shown in FIG. 3A, the portion where the wiring pattern is formed is removed.

A gold layer (stopper layer) having a thickness of 0.5 μm is formed on the copper alloy 11 by electrolytic gold plating using the copper alloy 11 as an electrode.
14 are formed. Since the gold layer 14 serves as a stopper layer when the copper alloy 11 is etched, it has a thickness of about 0.1 to 5 μm so as not to have pinholes and to have sufficient etching resistance (to serve as a stopper layer). The thickness is preferably, and more preferably, about 0.3 μm to 1 μm.

Further, in order to increase the adhesion to the copper plating in the subsequent step and prevent gold from diffusing into copper, electrolytic nickel plating is applied to a thickness of 2 μm to form a nickel layer 15. Then, immersed in a copper sulfate plating solution,
Thick electrolytic copper plating is applied, as shown in FIG.
A copper layer 16 is formed on the nickel layer 15. Also, FIG.
As shown in (c), the dry film 13 and the tape 1
2 is peeled off, and the copper alloy 11 is exposed.

Further, as shown in FIG. 3 (d), a photosensitive insulating resin 7a (Provimer 52; trade name: manufactured by Nippon Ciba Geigy Co., Ltd.) serving as an insulating layer 7 is coated with a copper alloy 11 and a copper Applied on layer 16.

As shown in FIG. 3E, the insulating resin 7a of the via hole 17 having a hole diameter of 100 μm is exposed and developed.
Is removed, and an insulating layer 7 is formed. Electroless copper plating is performed on the entire surface so that necessary portions can be electrically connected in electrolytic copper plating in a later step.

A dry film is adhered to the circuit forming surface and the back surface of the copper alloy 11 and is exposed and developed.
As shown in, the dry film 18 remains in the inner and outer lead regions. It should be noted that the dry film 18 is left so as to slightly overlap the insulating layer 7 in order to prevent a gap from being formed between the insulating layer 7 and the dry film 18 due to processing accuracy. The dry film 18 prevents adhesion of the plating to the external lead region of the copper alloy 11 at the time of plating in the subsequent step, and a tape having acid resistance is attached as an alternative means or an auxiliary means of the dry film. You may.

As shown in FIG. 4B, electrolytic plating is applied to the circuit forming surface composed of the copper layer 16 and the insulating layer 7 to form a 15 μm thick copper layer 19 in the wiring pattern portion.

Thereafter, as shown in FIG. 4C, the dry film 18 overlapping the insulating layer 7 is peeled off.
Further, soft etching is applied to the entire surface to remove the copper layer formed by electroless plating except the wiring pattern portion.

Hereinafter, corresponding to the desired number of layers, the insulating resin is selectively formed, the dry film 18 is selectively attached, and the copper layer 19 is formed in the same manner as in the steps shown in FIGS. 3D to 4C. Steps such as selective formation and peeling of the dry film 18 are sequentially repeated to form a desired first laminated structure 2 as shown in FIG.

After the completion of the first laminated structure 2, as shown in FIG. 4 (e), a resin of the same material as the insulating resin is screen-printed as a protective layer 4 on the surface of the first laminated structure. Exposure and curing. This protective layer forming step is the same as the insulating layer forming step. Instead of removing the resin from the via hole 17, the resin in the portion that needs to be exposed, such as the semiconductor chip connection land 20, is selectively removed. Then, on the land 20 for connecting the semiconductor chip, nickel plating with a thickness of 2 μm,
Gold plating with a thickness of 0.3 μm is sequentially applied (not shown).

Further, as shown in FIG. 5A, a dry film 21 is attached on the first laminated structure 2 after the formation of the protective layer 4 and the lands 20 by plating, and the entire surface is exposed. Although the dry film 21 is peeled off in a later process,
In that case, it is formed again and the first laminated structure 2 is protected until the final step. As in the case of the dry film 21, a tape or a film resistant to the chemical solution used in the subsequent step may be used as an auxiliary means or may be entirely replaced with the dry film 21.

Further, a dry film is stuck on the copper alloy 11 on the opposite side of the first laminated structure 2, and by exposure and development using a mask, as shown in FIG. It is selectively formed. Further, by etching the copper alloy 11 using ferric chloride as an etching solution, the external connection lead 5 of the copper alloy 11 is formed, and a circular portion is formed on the connection portion with the first laminated structure 2 on the other surface. The copper alloy 11 remains in a columnar shape. Since the gold layer 14 serves as an etching stopper here, only the copper alloy 11 is etched.

The resist 22 is removed and the copper alloy 11 is washed. In addition, a photosensitive insulating resin is printed on the copper alloy 11 and the insulating layer 7 on the first laminated structure 2 side, exposed and developed to remove the resin on the copper alloy 11 for front and back connection,
The insulating layer 7 is selectively formed. In addition, FIG.
Similar to (a), as shown in FIG. 5 (c), the dry film 23 is selectively attached onto the external connection leads 5 so as to slightly overlap the insulating layer 7.

In the same manner as described above, the steps of selectively forming a copper layer, peeling off a dry film, selectively forming an insulating resin, selectively sticking a dry film, and selectively forming a copper layer are sequentially and repeatedly performed. As shown in FIG. 5D, a desired second laminated structure 3 is formed.

Thereafter, as described above, the second laminated structure 3
A protective layer 4 is selectively formed thereon so as to expose the semiconductor chip connecting lands 20. Similarly, nickel plating and gold plating are sequentially formed on the semiconductor chip connecting lands 20 to complete the semiconductor device substrate as shown in FIG.

Subsequently, in the semiconductor device substrate, as shown in FIG. 6, the semiconductor chip 24 mounted on the semiconductor chip mounting portion is connected to the semiconductor chip connecting land 20 via bonding wires 25, and Insulation resin 2
6, the semiconductor device is completed as shown in FIG.

The semiconductor device substrate and the semiconductor chip may be connected to each other by a bump, a conductive paste or the like instead of the bonding wire. The external connection leads 5 may be plated with solder or another metal that does not adversely affect the mounting of the semiconductor device, or may be subjected to a flux treatment or the like for preventing oxidation.

According to the above-described structure, the advantage of the build-up method that a fine multilayer wiring can be formed with high precision and can be easily reduced in thickness is utilized even with a single-sided conductor circuit alone. Since these conductor circuits are provided on both sides of the lead frame, the density is further increased, so that high-density wiring can be expected in terms of structure.

Further, since the electrical connection is made via a part of the lead frame and a part separated from the external connection lead, the conductor circuit on one surface of the lead frame and the conductor circuit on the other surface of the lead frame are connected. Connection between circuits can be performed by using shallow via holes, and electrical connection between wirings on both surfaces of the lead frame can be realized with high reliability.

(Second Embodiment) FIG. 8 shows a second embodiment of the present invention.
FIG. 8 is a cross-sectional view showing the configuration of the semiconductor device substrate according to the embodiment of the present invention. The same parts as those in FIGS.

That is, the present embodiment is a modification of the first embodiment, and the first and second laminated structures 2 and 3 are replaced by electrical connection via the lead frame 1 (copper alloy 11). The electrical connection is made through the conductor layer 6.
Further, in the semiconductor device substrate according to the present embodiment, the lowermost insulating layer 7 is formed by using a photosensitive insulating resin instead of the dry film 13.

Next, a method for manufacturing such a semiconductor device substrate will be described.

After drying the same copper alloy 11 as described above, FIG.
As shown in (a), one surface has a photosensitive insulating resin (Probima-52; trade name: Nippon Ciba-Geigy Co., Ltd.).
Is applied by a curtain coat, and by exposure and development, an insulating resin in a portion where a wiring pattern is formed is removed. Thereafter, the insulating layer 7 having a thickness of 50 μm is formed by baking.

Further, on the copper alloy 11 and the insulating layer 7 and the other surface, a dry film 18 (Photec; trade name: manufactured by Hitachi Chemical Co., Ltd.) is attached in the same manner as described above. The dry film is exposed and cured using a mask,
It is selectively left on the copper alloy 11 in a portion to be a lead later so as to slightly overlap the insulating layer 7.

Similarly to the above, by electrolytic gold plating, as shown in FIG.
As shown in (b), a 0.5 μm thick gold layer 14 as a stopper layer is formed on the copper alloy 11, a 2 μm thick nickel layer 15 is formed on the gold layer by electrolytic nickel plating, and electrolytic copper plating is performed. Thus, a copper layer 16 having a thickness of 15 μm is formed on the nickel layer.

As shown in FIG. 9C, the dry film 18 is peeled off, electroless plating is applied to the entire surface on which the circuit is formed, and the dry film 18 is formed in portions other than the wiring pattern portion. 15μ after electrolytic plating
A copper layer with a thickness of m is formed. Then, the dry film 18 is peeled off, and the copper layer formed by electroless plating other than the wiring pattern portion is removed by soft etching.

Thereafter, similarly to FIG. 4D described above, the first laminated structure 2 is formed by selectively forming an insulating resin, selectively attaching a dry film, and selectively forming a copper layer.

The first laminated structure 2 is the same as that shown in FIG.
As in (e), the protective layer 4 is selectively formed, and a dry film is attached on the entire surface, and the entire surface is exposed.

Next, on the side opposite to the first laminated structure 2,
The copper alloy 11 is washed and dried, and a dry film is attached. This dry film is exposed using a mask,
By the development, the resist 22 is formed into a shape corresponding to the external connection lead.

Thereafter, as shown in FIG. 9D, the copper alloy 11 is etched by ferric chloride to form the external connection lead 5. Note that, unlike the first embodiment, all the copper alloy 11 in the printed circuit portion is removed.
Then, the resist 22 is peeled off and the substrate is washed.
The dry film 21 on the first laminated structure 2 is also peeled off at the same time, so that it is re-formed.

Then, on the surface opposite to the first laminated structure 2,
The photosensitive insulating resin is printed, and the resin in the via portion for front and back connection is removed by exposure and development, and the insulating layer 7 is formed.

Thereafter, as described above, as shown in FIG. 10A, the dry film 23 is selectively attached so as to cover the external connection lead portions and the like. Further, similarly to the above, FIG.
The steps of selectively forming the copper layer 19 (conductor layer 6), peeling off the dry film, selectively forming the insulating resin, selectively sticking the dry film, and selectively forming the copper layer shown in (b) are sequentially repeated. , As shown in FIG.
The laminated structure 3 is formed.

Thereafter, as described above, a protective layer is selectively formed on the second laminated structure, and nickel plating and gold plating are sequentially formed on the semiconductor chip connecting lands on the first and second laminated structures. Thus, the semiconductor device substrate is completed.
Further, the semiconductor device is completed by connecting the semiconductor chips and sealing the entire resin as described above.

According to the above-described structure, in addition to the effects of the first embodiment, the lowermost layer of the first laminated structure 2 is replaced with a resist, and an insulating layer is directly formed selectively. Can be facilitated.

(Third Embodiment) Next, a third embodiment of the present invention will be described.
Embodiments will be described, but the same parts as those in FIGS. 1 to 10 will be denoted by the same reference numerals and detailed description thereof will be omitted, and only different parts will be described here.

That is, in the present embodiment, the structure shown in the first embodiment is formed by partially using the manufacturing method shown in the second embodiment.

Specifically, the structure shown in FIG. 1 and FIG.
It is manufactured by forming the lowermost insulating layer 7 using a photosensitive insulating resin instead of the dry film 13. Next, a method for manufacturing such a semiconductor device substrate will be described.

(Manufacturing Method) FIGS. 9A to 9C described above.
11A to 11C, the first laminated structure 2 is formed, and the protective layer 4 and the plating layer on the land 20 are formed by the same process as described above. In addition, as shown in FIG. 11D, a dry film 21 is adhered to the entire surface of the first laminated structure 2 to protect the first laminated structure 2 from a chemical in a later step.

On the other hand, on the surface opposite to the first laminated structure 2,
As shown in FIG. 11E, a dry film is adhered, and a resist 22 is selectively formed by exposure and development using a mask. Further, the copper alloy 11 is selectively etched, and the external connection leads 5 and the first laminated structure 2 are formed.
And a columnar copper alloy 11 connected to it.

Hereinafter, similar to the first embodiment described above,
Resist stripping, cleaning, selective formation of insulating layer shown in FIG. 12A, protection of leads by dry film, selective formation of copper layer, stripping of dry film, selective formation of insulating resin, selective sticking of dry film, copper The steps of selectively forming layers,..., Are sequentially and repeatedly performed, and a desired second laminated structure 3 is formed as shown in FIG.

Also, in the same manner as described above, the protective layer 4 is selectively formed on the second laminated structure 3 and the plating process is performed on the lands 20 to complete the semiconductor device substrate shown in FIG. Similarly, mounting of a semiconductor chip, resin sealing, etc.
Is completed.

According to the above-described structure, in addition to the effect of the first embodiment, the lowermost layer of the first laminated structure 2 is replaced with a resist and an insulating layer is selectively formed directly. Can be facilitated.

(Fourth Embodiment) FIG. 13 is a sectional view showing the structure of a semiconductor device substrate according to a fourth embodiment of the present invention. Detailed description thereof is omitted, and only different parts will be described here.

That is, the present embodiment is a modification of the first embodiment, and specifically, the portion of the external connection lead 5 near the printed circuit portion which is the base end portion is selectively half-etched. It is formed thinner than the other parts.

That is, the external connection lead 5 has a thin portion 5a formed to be thinner than other portions to relieve stress.

Next, the manufacturing method and operation of such a semiconductor device substrate will be described.

During the etching of the copper alloy 11, a part of the external connection lead 5 is formed in the vicinity of the outside of the printed circuit portion on the copper alloy 11 along the longitudinal direction as shown in the plan view of FIG. Each resist 22 is formed with a gap 31. The etching amount can be controlled in proportion to the size of the gap 31 of the resist 22.

By forming the gap 31 of the resist 22 corresponding to the amount of etching and performing etching, the copper alloy 11 is half-etched to a desired depth as shown in FIG. Can be formed. As shown in FIG. 16, by forming a resist gap 31 on both surfaces of the copper alloy 11 and then etching,
Half-etching may be performed on both surfaces of the copper alloy 11 to manufacture the semiconductor device substrate shown in FIG.

As described above, in the external connection lead 5, the thin-walled portion 5a is partially formed, so that even if stress is applied, the thin-walled portion 5a relaxes the stress, and the first and second laminated structures are formed. Separation between the lead frame 1 and the lead frame 1 is hardly caused. Therefore, defects relating to separation of the semiconductor device substrate and the semiconductor device can be reduced and reliability can be improved.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described.
Will be described.

The present embodiment is a modification of the manufacturing method of the first embodiment, and the structure of the finished product is the same as the structure shown in FIG.

Therefore, a method of manufacturing a semiconductor device substrate according to this embodiment will be described below.

Now, as shown in FIG. 18A, a dry film 13 is adhered to the entire surface of the other side of the copper alloy 11, and one of the surfaces of the copper alloy 11 is removed in a later step. On the region 32, a liquid resist 33 is selectively applied. The amount and shape of half etching are controlled by adjusting the coating width of the liquid resist 33.

As shown in FIG. 18B, half-etching is performed on the exposed copper alloy 11 to form a recess 11a having a depth of 90 μm in the copper alloy 11. FIG.
As shown in (c), the dry film 13 and the resist 33 are peeled off, and the copper alloy 11 having the recess 11a is obtained.

Similar to FIGS. 3 to 5, the laminated structures 2 and 3 of the semiconductor device substrate are formed as shown in FIGS. 18 (d) and 19 (a) to (e). So,
A semiconductor device substrate and a semiconductor device are formed.

According to such a manufacturing process, since the copper alloy 11 in the portion 32 to be removed is removed in advance by half etching, the metal material is etched to form the external connection lead 5 and the like. In addition, since the amount of etching can be reduced, the amount of side etching can be suppressed, so that the processing accuracy of the external connection lead can be improved.

(Other Embodiments) In the first embodiment, in addition to the device structure, manufacturing in which the first and second laminated structures 2 and 3 are electrically connected to each other via the copper alloy 11 Although the method has been described, the present invention is not limited to this, and similarly to the second embodiment, the first and second laminated structures 2 and 3 are electrically connected to each other directly without using the copper alloy 11. The present invention can be implemented in the same manner and the same effects can be obtained with the above-described configuration and manufacturing method.

Further, in the fifth embodiment, the case where the thin portion 5a is provided on the external connection lead 5 has been described with respect to the first embodiment. With respect to any of the above embodiments, even if the external connection lead 5 is provided with the thin portion 5a and the manufacturing method, the present invention can be similarly implemented and the same effect can be obtained.

Further, in each of the above-mentioned embodiments, the lead frame is formed after the completion of the first laminated structure, and finally the second frame is formed.
Although the example of the procedure for forming the laminated structure is given, the order is not limited to this order, the lead frame is formed after the formation of the first layer of the first laminated structure, and the first layer of the second laminated structure is formed. May be formed first, and a pair of layers on the front and back, such as a second layer and a third layer of the first and second laminated structures, may be simultaneously and sequentially formed. That is, in the case of this method, the second layer and the third layer can be simultaneously formed on both surfaces, so that the process can be shortened, and it is particularly suitable for one having a large number of conductor layers.

In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[0123]

As described above, according to the present invention, it is possible to form a fine multilayer wiring with high precision, and to take advantage of the build-up method that it can be easily thinned. An expected semiconductor device substrate and a method for manufacturing the same can be provided.

Further, it is possible to provide a semiconductor device substrate which can realize electrical connection between wirings on both surfaces of a lead frame with high reliability and which is hardly peeled even when a force is applied to the lead frame, and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of a semiconductor device substrate according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line II-II of FIG.

FIG. 3 is a manufacturing process diagram of the semiconductor device substrate according to the embodiment.

FIG. 4 is a manufacturing process diagram of the semiconductor device substrate according to the embodiment.

FIG. 5 is a manufacturing process diagram of the semiconductor device substrate according to the first embodiment;

FIG. 6 is a manufacturing process diagram of the semiconductor device in the embodiment.

FIG. 7 is a cross-sectional view showing a structure of a semiconductor device in the same embodiment.

FIG. 8 is a sectional view showing a configuration of a semiconductor device substrate according to a second embodiment of the present invention;

FIG. 9 is a manufacturing process diagram of the semiconductor device substrate according to the first embodiment;

FIG. 10 is a manufacturing process diagram of the semiconductor device substrate according to the embodiment.

FIG. 11 is a manufacturing process diagram of a semiconductor device substrate according to a third embodiment of the present invention.

FIG. 12 is a manufacturing process diagram of the semiconductor device substrate according to the embodiment.

FIG. 13 is a sectional view showing a structure of a semiconductor device substrate according to a fourth embodiment of the present invention.

FIG. 14 is a plan view for explaining the manufacturing process in the same embodiment.

FIG. 15 is a cross-sectional view for explaining the manufacturing process in the same embodiment.

FIG. 16 is a cross-sectional view for explaining a modified example of the manufacturing process in the same embodiment.

FIG. 17 is a cross-sectional view for explaining a modification of the semiconductor device substrate in the embodiment.

FIG. 18 is a manufacturing process diagram of a semiconductor device substrate according to a fifth embodiment of the present invention.

FIG. 19 is a manufacturing process diagram in the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Lead frame 2 ... 1st laminated structure 3 ... 2nd laminated structure 4 ... Protective layer 5 ... Lead for external connection 5a ... Thin part 6 ... Conductive layer 7 ... Insulating layer 11 ... Copper alloy 11a ... Concave 12 ... Tape DESCRIPTION OF SYMBOLS 13 ... Dry film 14 ... Gold layer 15 ... Nickel layer 16, 19 ... Copper layer 17 ... Via hole 7a, 26 ... Insulating resin 18, 21, 23 ... Dry film 20 ... Land 22 ... Resist 24 ... Semiconductor chip 25 ... Bonding wire 31 ... gap 32 ... removal area

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hidekatsu Sekine 1-5-1, Taito, Taito-ku, Tokyo Letterpress Printing Co., Ltd.

Claims (9)

[Claims] 1. A lead frame, a first conductor circuit in which an insulating layer and a wiring layer formed by solidifying a resin are sequentially laminated alternately on one surface of the lead frame, and the first conductor. A second conductive circuit electrically connected to a circuit, and an insulating layer and a wiring layer formed by solidifying a resin are alternately laminated on the other surface of the lead frame; and A substrate for a semiconductor device, comprising: an external connection lead formed to extend outward from a portion sandwiched between the first conductor circuit and the second conductor circuit. 2. The semiconductor device substrate according to claim 1, wherein the first and second conductor circuits are electrically connected to each other through a part of a lead frame. Substrate. 3. The semiconductor device substrate according to claim 1, wherein the external connection lead is selectively half-etched at a position near the first and second conductor circuits. A semiconductor device substrate characterized by the above. 4. A step of (A) selectively forming a resist on one surface of a sheet-shaped metal material having a circuit area, an internal lead area and an external lead area as outer peripheral sides in order.
(B) selectively forming, on one surface of the metal material, a stopper conductor layer including a layer serving as an etching stopper on a surface of the circuit region and the internal lead region where the resist is not formed; (D) removing the resist after forming the stopper conductor layer; and (D) forming the stopper layer on one surface of the metal material and on the stopper conductor layer in the circuit region and the internal lead region. (E) selectively forming an insulating layer so as to be partially exposed; and (E) selectively forming a conductive layer on the insulating layer and on a stopper conductive layer which is exposed by non-selection.
(F) a step of selectively forming an insulating layer on the uppermost insulating layer and the uppermost conductive layer so as to partially expose the conductive layer; and (G) on the uppermost insulating layer and A step of selectively forming a conductor layer on the conductor layer exposed by non-selection, and (H) the above (F) to (G) are repeated up to a predetermined number of times to form a first laminated structure of an insulating layer and a conductor layer. In the circuit region and the inner lead region, (I) forming a protective layer on the outermost surface of the first laminated structure in a removable manner, and (J) the inner and outer lead regions. Forming the external connection leads by selectively etching the sheet-shaped metal material and removing the metal material in the circuit region; and (K) removing the insulating layer exposed by the removal of the metal material; Place the stopper conductor layer on the stopper conductor layer. (L) a step of selectively forming an insulating layer so as to be selectively exposed, (L) a step of selectively forming a conductive layer on the insulating layer and on the stopper conductive layer exposed by non-selection, Selectively forming an insulating layer on the upper insulating layer and the uppermost conductive layer so as to partially expose the conductive layer; and (N) exposing the uppermost insulating layer and non-selectively. (O) repeating the above (M) to (N) a predetermined number of times to form a second laminated structure of an insulating layer and a conductive layer on the circuit region. And a step of forming the semiconductor device substrate. 5. The method for manufacturing a semiconductor device substrate according to claim 4, wherein an insulating layer is used instead of the resist in each of the steps (A) and (B), and the step (C) is performed. Is omitted, and the insulating layer is used in place of one surface of the metal material in the step (D), and a method for manufacturing a substrate for a semiconductor device. 6. The method for manufacturing a semiconductor device substrate according to claim 4, wherein the metal material in the circuit region is selectively removed in the step (J) so that at least the stopper conductor layer is not exposed. Wherein the metal material is used in place of the respective stopper conductor layers in each of the steps (K) and (L). 7. The method of manufacturing a substrate for a semiconductor device according to claim 6, wherein an insulating layer is used instead of each resist in each of the steps (A) and (B). Is omitted, and the insulating layer is used in place of one surface of the metal material in the step (D), and a method for manufacturing a substrate for a semiconductor device. 8. The method of manufacturing a semiconductor device substrate according to claim 6, wherein the metal material is removed in the step (J) prior to the step (A). A method of manufacturing a substrate for a semiconductor device, comprising a step of previously half-etching a portion to be formed. 9. The method of manufacturing a semiconductor device substrate according to claim 4, further comprising a step of selectively half-etching the external connection lead near the internal lead region. A method for manufacturing a substrate for a semiconductor device.