JP2003037137A - Method of manufacturing wiring substrate and wiring substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce short-circuit failure of conductor wiring in a method of manufacturing a wiring substrate, in which the conductor wiring is formed using an additive method. SOLUTION: In the method of manufacturing the wiring substrate, a thin film 201 made of first conductor is formed on the entire surface of an insulating substrate, second conductor 203 having a predetermined pattern is formed on the first conductor, and an area of the first conductor 201, where the second conductor 203 is not formed, is removed by etching processing to form the conductor wiring. A conductor that dissolves in solution to which the second conductor 203 is insoluble or hardly soluble is used as the first conductor 201.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a wiring board and a wiring board, and more particularly to a technique effective when applied to a fine wiring board manufactured using an additive method.

[0002]

2. Description of the Related Art Conventionally, semiconductor devices (packages) have been
Tape Carrier Packag manufactured using TAB (Tape Automated Bonding) technology
There is e).

The tape carrier package has a surface 1A of an insulating substrate 1 as shown in FIG. 11 (a), for example.
Further, it is manufactured using a wiring board (hereinafter referred to as a tape carrier) in which the conductor wiring 2 having a pattern corresponding to the external terminals (bonding pads) of the semiconductor chip to be mounted is repeatedly formed. The tape carrier uses a tape material, such as a polyimide tape, which is long in one direction as the insulating substrate 1. The insulating substrate 1 has an end portion along the long side direction for guiding or positioning during transportation. An opening (sprocket hole) 1C used is provided. Further, the insulating substrate 1 has, for example, FIG.
As shown in FIG. 3, an opening (device hole) 1D in a region where a semiconductor chip is mounted and an opening 1E for outer leads are provided, and the conductor wiring 2 projects into the openings 1D and 1E. .

Further, the conductor wiring 2 is mainly formed by an additive method, and as shown in FIG. 11B, for example, a first conductor 204 made of a nickel alloy is used as an underlayer to form an electrolytic layer. Second thickly formed copper plating
The conductor 203 is laminated. Here, FIG. 11B is a cross-sectional view taken along the line BB ′ of FIG.

In addition, as shown in FIG. 11A, a region of the conductor wiring 2 other than a portion connected to an external terminal of the semiconductor chip or a mounting substrate is covered with a solder protection film (solder resist) 3. As shown in FIG. 11 (b), a portion of the semiconductor chip, which is protected and is connected to the external terminals, is provided with a terminal plating 4 for the purpose of preventing oxidation or improving connectivity. ing. As the terminal plating 4, for example, there is one in which gold plating is formed with nickel plating as a base.

In the tape carrier, the insulating substrate 1
The above-mentioned conductor wiring 2 is mainly formed by using a semi-additive method, and the procedure will be briefly described. First, as shown in FIG. 12A, for example, as shown in FIG. A thin film of the first conductor 204, which serves as a base, is formed on the surface. At this time, in the first conductor 204,
Mainly nickel-copper (Ni-Cu) alloy or nickel
A nickel alloy such as a chromium (Ni-Cr) alloy is used, and is formed by sputtering to have a thickness of about 5 nm to 20 nm.

Besides the nickel alloy, for example, a thin film of copper or a copper alloy formed by sputtering is used for the first conductor 204.

Next, as shown in FIG. 12B, a resist (plating resist) 5 is formed on the first conductor (nickel alloy) 204 so that a portion for forming a conductor pattern is opened. The plating resist 5 is formed by a photographic method in which a pattern is exposed and developed using a photosensitive dry film, or a printing method in which resist ink is printed and cured using a screen plate.

Next, as shown in FIG. 13A, a second conductor 203 is formed on a portion of the first conductor (nickel alloy) 204 which is not covered with the plating resist 5. The second conductor 203 is mainly formed by electrolytic copper plating using the first conductor (nickel alloy) 204 as a cathode. At this time, although it is schematically shown in FIG. 13A for the sake of clarity, the actual thickness of the second conductor (electrolytic copper plating) 203 is the same as that of the first conductor (nickel alloy). It is formed to be sufficiently thicker than the thickness of 204, for example, about 10 μm.

Next, although not shown, for example, the first
The insulating substrate 1 is etched from the surface opposite to the surface on which the conductor (nickel alloy) 204 and the second conductor (electrolytic copper plating) 203 are formed, and the device hole 1D and the outer lead opening 1E are formed. . In the method of etching the insulating substrate 1, for example, when the plating resist 5 is formed, the openings 1D shown in FIG. 12A are formed on the surface opposite to the surface on which the plating resist 5 is formed. There are a method of forming an etching resist having an opening on 1E and etching with an etching solution such as an oxidizing agent, a method of laser etching using a carbon dioxide laser or an excimer laser, and the like.

Next, as shown in FIG. 13B, after removing the plating resist 5, unnecessary portions of the first conductor (nickel alloy) 204, in other words, the second conductor (electrolytic copper plating). A portion 204 in which 203 is not formed
When A is removed by the etching process, as shown in FIG. 14, electrically independent conductor wirings 2 are formed. In the etching treatment of the first conductor (nickel alloy) 204, for example, a ferric chloride solution obtained by dissolving ferric chloride (FeCl ₃ ) in water or cupric chloride (CuCl ₂ · 2H ₂ O) in water is used. And a suitable amount of hydrochloric acid added thereto is used as a cupric chloride solution as an etching solution.

At this time, the actual thickness of the first conductor (nickel alloy) 204 is much smaller than the thickness of the second conductor 203 and can be removed in a short time. In many cases, quick etching is performed without using an etching resist.

When the conductor wiring 2 on the insulating substrate 1 is formed by using the semi-additive method, the opening 1C, 1D, 1E is not limited to the above procedure, but is punched by a die in advance. After a thin film such as an electrolytic copper foil or a rolled copper foil is bonded as the first conductor 204 on the insulating substrate 1 on which the plating resist 5 as shown in FIG. 12B is formed, There is also a method of forming the second conductor (electrolytic copper plating) 203 on the copper foil.

After the conductor wiring 2 is formed on the insulating substrate 1 according to the procedure described above, as shown in FIG. 11A, the conductor wiring 2 includes the external terminals of the semiconductor chip and the mounting substrate. A solder protective film (solder resist) 3 is formed in a region other than a terminal portion connected to the conductor wiring 2
The terminal plating 4 as shown in FIG. 11B is formed on the surface of the portion (terminal portion) exposed from the solder protective film 3. For the terminal plating 4, for example, electroless gold plating is formed using electroless nickel plating as a base.

When a semiconductor device is manufactured using the tape carrier manufactured according to the above procedure, for example,
As shown in FIG. 15, the conductor wiring 2 of the insulating substrate 1
The surface 1A on which is provided and the external terminal 601 of the semiconductor chip 6 conveyed by the collet 8 are arranged to face each other for alignment, and bonding is performed from the opening (device hole) 1D provided in the insulating substrate 1. Tool 10
Is pressed to electrically connect the conductor wiring 2 and the external terminal 601 of the semiconductor chip. At this time, on the external terminal 601 of the semiconductor chip or on the conductor wiring 2
The bumps 7 made of solder, gold, or the like are provided on the upper side, and they are connected by thermocompression bonding using the bonding tool 10 or thermocompression bonding using ultrasonic waves.

The semiconductor chip 6 is attached to the tape carrier.
After mounting (mounting), as shown in FIG. 16, the sealing resin 11 such as an uncured epoxy resin is poured from the device hole 1D provided in the insulating substrate 1 to be cured, and the conductor wiring 2 and the connection portion between the external terminal 601 of the semiconductor chip is sealed.

Further, as a method of mounting the semiconductor chip 6 on the tape carrier, as shown in FIG. 16, a surface 1 of the insulating substrate 1 on which the conductor wiring 2 is formed is used.
In addition to the method of mounting on A, for example, as shown in FIG. 17, a surface 1 of the insulating substrate 1 on which the conductor wiring 2 is formed
There is also a method of mounting the semiconductor chip 6 in the device hole 1D of the insulating substrate 1 from the surface 1B side facing A.

With the recent miniaturization of semiconductor chips, high functionality, and miniaturization of semiconductor devices, miniaturization and high density of the conductor wiring 2 formed on the insulating substrate 1 have been advanced. I'm out. One of the tape carriers in which the conductor wiring 2 is miniaturized is a tape carrier used for a driver for driving the liquid crystal panel.

As shown in FIGS. 18 and 19, the tape carrier used for the driver for driving the liquid crystal panel includes a signal line 2A for operating power supply or data input of a driver chip (semiconductor chip) and the driver chip. A source signal line 2B for outputting the processed display data signal to each pixel of the liquid crystal panel is provided. Here, FIG.
9 is an enlarged plan view of the region L2 in FIG.

In recent years, the liquid crystal panel has been highly refined,
While the number of display pixels is increasing and the number of the source signal lines 2B provided on the tape carrier is increasing,
Miniaturization is also required, and the conductor pitch P1 of the source signal line 2B shown in FIG.
Is about 40 μm.

When the conductor pitch P1 and the conductor gap P2 of the conductor wiring 2 become narrower, as in the tape carrier used for the driver for driving the liquid crystal panel, as shown in FIG. Since it is difficult to form wiring that protrudes into the openings 1D and 1E, a COF (Chip On Film) method is used when mounting (mounting) a semiconductor chip on the tape carrier.

When the semiconductor chip 6 is mounted by the COF method, the tape carrier is, as shown in FIG.
When the device hole 1D is not provided in the insulating substrate 1 and the semiconductor chip 6 is mounted (mounted), first, the conductor wiring 2 of the insulating substrate 1 is formed as shown in FIG. The external terminals of the semiconductor chip 6 conveyed by the collet 8 are arranged face-to-face on the raised surface 1A for alignment. At this time, since the insulating substrate 1 does not have the device hole 1D and the alignment cannot be performed while directly observing, the insulating substrate 1 is located from the surface 1B side facing the surface 1A facing the semiconductor chip 6. The light 9 is irradiated to the substrate, and the image seen through the insulating substrate 1 is observed to align the conductor wiring 2 and the semiconductor chip 6.

Next, as shown in FIG. 21, the bonding tool 10 is pressed from the surface 1B of the insulating substrate 1 which faces the surface of the insulating substrate 1 facing the semiconductor chip 6, and the conductor is interposed with the bumps 7 interposed therebetween. The wiring 2 is connected to the external terminal 601 of the semiconductor chip.

After that, as shown in FIG. 22, a sealing resin 11 made of, for example, an uncured thermosetting resin is poured into the gap between the tape carrier and the semiconductor chip 6 to be cured, and the conductor wiring 2 And the connection portion of the external terminal 601 of the semiconductor chip is sealed.

When the semiconductor chip 6 is mounted by the COF method, as shown in FIG.
A material having a high transparency is used for the insulating substrate 1 in order to perform the alignment by the image seen through.

[0026]

However, in the method of manufacturing the wiring board (tape carrier) using the conventional additive method, it is sufficient to remove the unnecessary portion 204A of the first conductor 204 by etching. As shown in FIG. 23 (a), the second etching is not performed.
There is a problem that an etching residue 204A ′ is likely to occur in a region outside the conductor (electrolytic copper plating) 203. The etching residue 204A ′ of the first conductor 204 is a high density portion of the second conductor 203, that is, the insulating substrate 1
Since the number of conductor wirings 2 formed on the upper side is large, it is likely to occur in a dense portion. Therefore, for example, in a tape carrier having a very narrow conductor gap P2, such as the tape carrier used for the driver of the liquid crystal panel shown in FIGS. 18 and 19, the unnecessary portion 204A of the first conductor 204 is removed. Is likely to be insufficient, and as shown in FIG. 23 (b), the adjacent conductor wiring (second conductor 203) is connected to the first conductor 20.
Short-circuited due to the etching residue 204A 'of 4,
There was a problem that it became a defective product.

Particularly, when a nickel alloy such as a nickel-copper alloy or a nickel-chromium alloy is used as the first conductor 204, the ferric chloride solution or the cupric chloride solution is used as an etching solution. 23A and FIG. 23 because the etching rate of the first conductor (nickel alloy) 204 is slower than the etching rate of the second conductor (electrolytic copper plating) 202.
Etching residue 204 of the first conductor shown in (b)
There is a problem that A is more likely to occur.

Also, as a means for preventing the etching residue 204A 'of the first conductor 204, there is a method of lengthening the time taken for the etching treatment of the first conductor 204.
If the treatment time is lengthened, the surface of the second conductor 203 is also etched by that amount, so that the corners (edges) 203A of the second conductor 203 are rounded or the surface is flat as shown in FIG. There was a problem of getting worse. Since the flatness of the surface of the second conductor 203 is deteriorated, for example, the connectivity of the bump 7 when mounting a semiconductor chip is deteriorated.

An object of the present invention is to provide a technique capable of reducing a short circuit defect of the conductor wiring in a method of manufacturing a wiring board in which a conductor wiring is formed by using an additive method.

Another object of the present invention is to provide a method of manufacturing a wiring board in which conductor wiring is formed by using the additive method,
It is to provide a technique capable of improving the flatness of the surface of the conductor wiring.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0032]

The outline of the invention disclosed in the present application is as follows.

(1) A thin film made of a first conductor is formed on the entire surface of an insulating substrate, a second conductor having a predetermined pattern is formed on the first conductor, and the second conductor of the first conductor is formed. In a method of manufacturing a wiring board, wherein a conductor wiring is formed by removing an unetched portion by etching, a wiring using a conductor in which the second conductor is dissolved in a solution in which the second conductor is insoluble or hardly soluble It is a method of manufacturing a substrate.

According to the above-mentioned means (1), when the unnecessary portion of the first conductor is removed by the etching process, the second conductor can be etched using a solution which is hardly soluble or insoluble. Therefore, when the first conductor is etched, the second conductor is hardly etched. Therefore, it is possible to take a sufficient time for the etching treatment of the first conductor, reduce the etching residue of the first conductor, and reduce the short circuit defect between the conductor wirings.

Further, even if the time taken for the etching treatment of the first conductor is long, the second conductor is hardly etched, so that the flatness of the surface of the second conductor, in other words, the surface of the conductor wiring is poor. Can be prevented.

Further, when the first conductor is etched, the second conductor is hardly etched, so that the finer and higher density of the conductor wiring is advanced, and the first conductor is etched.
Even if the etching rate of the conductor is reduced, the first conductor can be etched with almost no etching of the second conductor, and the etching residue of the first conductor can be reduced.

Further, by reducing the etching residue of the first conductor, it is possible to reduce the short circuit defect due to the etching residue of the wiring board, so that the manufacturing yield of the wiring board is improved and the wiring board is improved. Manufacturing cost can be reduced.

In the means (1), the combination of the first conductor and the second conductor is the first conductor.
It is preferable to use chromium (Cr) as the conductor and copper (Cu) as the second conductor. At this time, for example, an aqueous potassium permanganate solution can be used as the etching solution that dissolves the chromium. Since the copper used as the second conductor is insoluble (poorly soluble) in the potassium permanganate aqueous solution, the second conductor (copper) is hardly etched.

When chromium is used as the first conductor, there is a method of forming a chromium thin film on the insulating substrate in the step of forming the first conductor, for example, by sputtering. However, since the chromium thin film is easily oxidized in air, it is preferable to form a copper thin film for oxidation prevention on the surface of the chromium thin film by sputtering immediately after forming the chromium thin film.

Also, chromium is used as the first conductor,
When a copper sputtered film is formed on the chromium thin film, electrolytic copper plating is formed as the second conductor on the first conductor layer. In the subsequent step of etching the first conductor, first, for example, the copper sputtered film is removed using a ferric chloride solution or a cupric chloride solution, and then the potassium permanganate aqueous solution is used to remove the copper sputtered film. Remove the chromium film. Since the surface of the second conductor is also etched when the copper sputtered film is removed, the thickness of the copper sputtered film can prevent the chromium thin film from being oxidized and the surface of the second conductor can be flat. It is necessary to make the thickness such that the property is not affected, and for example, it is preferably about 10 nm.

As the combination of the first conductor and the second conductor, various combinations other than the chromium and copper are conceivable. For example, as the first conductor, a metal or a conductive material that dissolves in an alkaline solution is used, and the second conductor is used.
By using a metal or a conductive material that is insoluble or hardly soluble in an alkaline solution as the conductor, the first
When the conductor is etched, the second conductor does not dissolve, which reduces the etching residue of the first conductor and prevents the flatness of the surface from being deteriorated.

(2) In the wiring board in which the conductor wiring having a predetermined pattern is provided on the surface of the insulating substrate, the conductor wiring is formed by laminating the second conductor with the first conductor as a base layer. Is a wiring board in which the second conductor is dissolved in a solution which is insoluble or hardly soluble.

According to the above-mentioned means (2), in the second conductor laminated on the first conductor, the second conductor is almost dissolved when the first conductor is dissolved (etched). Since the second conductor is not present, the flatness of the surface of the second conductor is good and the mountability of the semiconductor chip can be improved.

As a combination of the first conductor and the second conductor, chromium (Cr) is used for the first conductor,
It is preferable to use copper (Cu) for the second conductor. In this case, since the adhesion (adhesion) between the polyimide material mainly used as the insulating substrate and the chromium is very good, the conductor wiring is peeled off. It is possible to obtain a wiring board which is reduced and has high reliability.

Hereinafter, the present invention will be described in detail with reference to the drawings together with the embodiments (embodiments).

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals and their repeated description will be omitted.

[0047]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIGS. 1 and 2 are schematic views showing a schematic structure of a wiring board according to an embodiment of the present invention. FIG. 1 is a plan view of the entire wiring board, and FIG. 2A is an enlarged plan view of a region L2 of FIG. 1, and FIG. 2B is a sectional view taken along the line AA ′ of FIG.

In FIGS. 1, 2A and 2B, 1 is an insulating substrate, 1A is the surface of the insulating substrate (first main surface), 1C is an opening (sprocket hole), and 2 is a conductor. Wiring, 2A is an input signal line, 2B is a source signal line (output signal line), 201 is a first conductor (chromium sputtered film), 20
Reference numeral 2 is a first conductor protective film (copper sputtered film), 203 is a second conductor (electrolytic copper plating), 3 is a solder protective film (solder resist), 4 is terminal plating, and L1 is a chip mounting region.

In the wiring board of this embodiment, as shown in FIG. 1, a conductor wiring 2 having a predetermined pattern is provided on the surface 1A of an insulating substrate 1. In addition, the wiring board of the present embodiment,
It is used as a driver for driving liquid crystal panels.
As the conductor wiring 2, an input signal line 2A connected to an operation power supply terminal or a signal input terminal of a driver chip (semiconductor chip) mounted in the chip mounting area L1, and a display data signal is output to each display pixel of the liquid crystal panel. The source signal line 2B is provided.

The source signal lines 2B of the conductor wiring 2 are provided by the number corresponding to the number of display pixels of the liquid crystal panel, and as shown in FIGS. 1 and 2A. It is set up very closely. In the wiring board of the present embodiment, the conductor pitch P1 and the conductor gap P2 of the source signal line 2B shown in FIG. 2A are about 40 μm.

Further, as shown in FIG. 2B, the conductor wiring 2 provided on the wiring board of this embodiment has the first conductor protection film 202 and the second conductor protection film 202 and the second conductor protection film 202 formed on the first conductor 201 as a base. The conductors are sequentially laminated. In the wiring board of the present embodiment, the first conductor 201 is made of a chromium (Cr) sputtered film, the first conductor protection film 202 is made of a copper sputtered film, and the second conductor 203 is made of electrolytic copper plating. I shall. Further, in the cross-sectional view of FIG. 2B, the thickness of the conductor wiring 2 is shown differently in order to make it easier to understand, but in an actual wiring board, the first conductor (hereinafter, chromium sputtered film) is used. 201) has a thickness of about 20 nm (200 angstroms).
The conductor protection film (hereinafter referred to as a copper sputtered film) 202 has a thickness of about 10 nm (100 angstroms), and the second conductor (hereinafter referred to as electrolytic copper plating) 203 has a thickness of about 10 μm. I shall.

In addition, as shown in FIG. 1, a region of the conductor wiring 2 excluding an external terminal of the semiconductor chip and a terminal portion connected to the mounting substrate is covered with a solder protective film (solder resist) 3. The terminal portion that is protected and connected to the external terminals of the semiconductor chip is
As shown in (b), terminal plating 4 is provided to prevent oxidation or improve connectivity. As the terminal plating 4, for example, there is one in which gold plating is formed with nickel plating as a base.

In the wiring board, a tape material such as a polyimide tape which is long in one direction is used as the insulating board 1, and a conductor having a pattern as shown in FIG. 1 is formed over the entire area of the tape material. It is a tape carrier in which the wiring 2 is repeatedly provided, and an opening (sprocket hole) 1C used for guiding or positioning at the time of conveyance is provided at an end portion along the long side direction of the insulating substrate 1.

Further, in the wiring board (tape carrier) of this embodiment, the conductor gap P is formed like the source signal line 2B.
2 has a very narrow pattern, and the conventional TBGA
Like a wiring board used for (Tape Ball Grid Array) type packages, it is difficult to form a conductor wiring protruding into an opening such as a device hole, and it is expected that a semiconductor chip will be mounted by the COF method. It When a semiconductor chip is mounted by the COF method, alignment when mounting the semiconductor chip is performed by a transparent image of the insulating substrate 1. Therefore, a material having high transparency is used for the insulating substrate 1.

3 to 5 are schematic views for explaining the method for manufacturing the wiring board of this embodiment, and FIGS. 3 (a), 3 (b), 4 (a) and 4 ( b), FIG. 5 (a), and FIG. 5 (b) are respectively FIG. 2 (a) in each manufacturing process.
A cross-sectional view corresponding to the line AA ′ of FIG.

The method of manufacturing the wiring board of this embodiment will be described below with reference to FIGS.

First, on the entire first main surface 1A of the insulating substrate 1 which is in the form of a long tape in one direction, such as a polyimide tape,
As shown in FIG. 3A, chromium is sputtered to form, for example, a chromium sputtered film 20 having a thickness of about 20 nm.
1 is formed, the chromium sputtered film 201 is continuously formed.
Copper is sputtered thereon to form, for example, a copper sputtered film 202 having a thickness of about 10 nm. Here, the copper sputtered film 202 is formed to prevent oxidation of the chromium sputtered film 201.

Next, as shown in FIG.
As shown in (b), a resist (plating resist) 5 having an opening at a predetermined position is formed. In the wiring board of this embodiment, since the conductor wiring 2 is formed by using the semi-additive method, the plating resist 5 has an opening at the portion where the conductor wiring 2 is formed as shown in FIG. It is formed. At this time, the plating resist 5 is formed by a photographic method in which a photosensitive resist film is exposed and developed to form a pattern, or a printing method in which resist ink is printed and cured using a screen plate.

Next, electrolytic copper plating 203 is formed in the opening of the plating resist 5 by electrolytic plating using the chromium sputtered film 201 and the copper sputtered film 202 as cathodes, as shown in FIG. 4 (a). To do. At this time,
The thickness of the electrolytic copper plating 203 is made sufficiently thicker than the thickness of the chromium sputtered film 201 and the copper sputtered film 202, and is formed to be about 10 μm, for example.

Next, as shown in FIG. 4B, after removing the plating resist 5, an unnecessary portion of the copper sputtered film 202, in other words, the electrolytic copper plating 203 is formed by quick etching. Not part 2
02A is removed. At this time, the copper sputtered film 202
For etching, for example, ferric chloride solution in which ferric chloride (FeCl ₃ ) is dissolved in water or cupric chloride (CuCl 3
₂ · 2H ₂ O) was dissolved in water, using an appropriate amount of the cupric chloride solution that was added hydrochloric acid as an etching solution. At this time, the surface of the electrolytic copper plating 203 is also etched. At this time, the etching amount T1 of the electrolytic copper plating 203 is about the thickness T2 of the copper sputtered film 202, that is, about 10 nm. The amount is sufficiently smaller than the thickness of the copper plating 203 of 10 μm. Therefore, the state after etching the copper sputtered film 202 is as shown in FIG. 5A, and the electrolytic copper plating 203 is performed.
The edges are not rounded and the surface flatness is not bad.

Next, the chromium sputtered film 201 is subjected to etching treatment, and as shown in FIG. 5B, the insoluble portion 201A of the chromium sputtered film 201 is removed to form the conductor wiring 2. At this time, for etching the chromium sputtered film 201, for example, an aqueous potassium permanganate solution is used as an etching solution. The potassium permanganate aqueous solution used here is a solution that corrodes and dissolves chromium (Cr) but hardly dissolves copper (Cr), and the chromium sputtered film 201 was etched using the potassium permanganate aqueous solution. At times, the surface of the electrolytic copper plating 202 is hardly etched.
That is, since the chromium sputtered film 201 can be selectively etched, it is possible to sufficiently etch the chromium sputtered film 201,
It is possible to reduce the etching residue of the chromium sputtered film 201 and prevent a short circuit defect between the conductor wirings due to the etching residue of the base layer (chrome sputtered film) of the conductor wiring 2.

Further, in order to reduce the etching residue of the chromium sputtered film 201, the potassium permanganate aqueous solution is used as the etching solution even when the etching time of the chromium sputtered film 201 is long. The electrolytic copper plating 203 is hardly etched and prevents the surface flatness of the electrolytic copper plating 203 from being deteriorated.

By etching the chromium sputtered film 201, the conductor wiring 2 as shown in FIG. 5B is formed.
After forming, for example, after forming a solder protective film (solder resist) 3 in a region of the conductor wiring 2 excluding a terminal portion connected to an external terminal of a semiconductor chip or a mounting substrate,
A terminal plating 4 is formed on a portion of the conductor wiring 2 protruding from the solder resist 3, that is, a terminal portion connected to an external terminal of a semiconductor chip or a mounting substrate. At this time,
The solder resist 3 is formed by a printing method in which a resist ink is printed using a screen plate or a photographic method using a photosensitive dry film.
Is formed by, for example, electroless gold plating, electroless gold plating with electroless nickel plating as a base, tin plating, tin alloy plating, or the like.

Regarding the process of forming the solder resist 3 and the plating 4, the solder resist 3 is used.
In addition to the method of forming the terminal plating 4 on the exposed portion of the conductor wiring 2 after forming the conductor, the plating 4 is formed on the entire exposed surface of the conductor wiring 2, and then the solder resist 3 is formed on a predetermined area. There is a method of forming.

The wiring board (tape carrier) of this embodiment manufactured by the above procedure is mounted with a driver chip (semiconductor chip) by using the TAB technique, and is sealed at a predetermined portion with a resin, and then separated into individual pieces. As a result, a liquid crystal driver device (semiconductor device) is obtained.

6 to 10 are schematic views for explaining a method of manufacturing a semiconductor device using the wiring board of this embodiment. FIG. 6 is a plan view at the time of alignment, and FIG. 7 is a plan view. FIG. 8 is a sectional view taken along an arbitrary cutting line, FIG. 8 is an enlarged plan view of the region L2 in FIG. 6, FIG. 9 is a sectional view during bonding, and FIG. 10 is a sectional view during sealing.

A method of manufacturing a semiconductor device using the wiring board of this embodiment will be described below with reference to FIGS.

In the step of mounting (mounting) a semiconductor chip on the wiring board (tape carrier), TAB (Tape A
First, as shown in FIGS. 6, 7, and 8, the first main surface 1A of the insulating substrate 1 and the semiconductor chip 6 are faced to each other, and the terminal portion of the conductor wiring 2 is used. And the external terminals 601 of the semiconductor chip 6 are aligned. At this time, bumps 7 made of solder or gold are provided on the external terminals 601 of the semiconductor chip, and the bumps 7 are transported by the collet 8 as shown in FIG.

Further, in the wiring board of the present embodiment, the conductor gap is very narrow like the source signal line 2B and the semiconductor chip is mounted by the COF method. Therefore, as shown in FIG.
A second main surface 1B facing the first main surface 1A of the insulating substrate 1.
Light is radiated from the semiconductor substrate 1 and, as shown in FIG. 8, alignment is performed using the images of the conductor wiring 2 and the external terminals 601 of the semiconductor chip that are seen through the insulating substrate 1.

Next, as shown in FIG. 9, the insulating substrate 1
The bonding tool 10 is pressed from the second main surface 1B side to connect the conductor wiring 2 and the external terminal 601 of the semiconductor chip via the bump 7.

Thereafter, as shown in FIG. 10, a sealing resin 11 such as an uncured thermosetting resin is poured between the insulating substrate 1 and the semiconductor chip 6 to cure the sealing resin 11.
The connection between the conductor wiring 2 and the external terminal 601 of the semiconductor chip is sealed.

As described above, according to the wiring board of the present embodiment, when the conductor wiring 2 is formed on the insulating substrate 1 by using the semi-additive method, the first conductor 201 serving as a base is formed. After forming a chromium sputtered film and forming electrolytic copper plating as the second conductor 203 on the chromium sputtered film 201, the electrolytic copper plating 203 is an insoluble (slightly soluble) potassium permanganate aqueous solution as an etching solution. By etching the chromium sputtered film 201, only the chromium sputtered film 201 can be selectively etched. Therefore, without deteriorating the flatness of the surface of the electrolytic copper plating 203,
The chromium sputtered film 201 may be etched.

Even when the conductor wiring 2 is miniaturized and the etching rate of the chromium sputtered film 201 is reduced, the electrolytic copper plating 203 is insoluble (hardly soluble) in the potassium permanganate aqueous solution. The chromium sputtered film 201 can be etched over a sufficient time, and the etching residue can be reduced. Therefore, short-circuit defects between conductors due to the etching residue can be reduced. Further, by reducing the short-circuit defect between the conductors, the manufacturing yield of the wiring board can be improved, and the manufacturing cost of the wiring board can be reduced.

Further, by using as the first conductor 201 chromium which has good adhesiveness (adhesion) to the polyimide mainly used as the insulating substrate 1, peeling of the conductor wiring 2 can be reduced. Thus, a highly reliable wiring board can be obtained.

Although the present invention has been specifically described based on the above embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

For example, in the above-described embodiment, a chromium sputtered film is used as the first conductor 201, which serves as an underlayer when the conductor wiring 2 is formed by using the semi-additive method, and electrolytic copper plating is performed on the first conductor. After stacking, the potassium permanganate aqueous solution that selectively corrodes and dissolves only the chromium sputtered film is used as the etching solution, but the present invention is not limited to this, and is insoluble or difficult in the etching solution that dissolves the first conductor. After forming the soluble second conductor, only the first conductor needs to be selectively etched. For example, as the first conductor, a metal or a conductive material that dissolves in an alkaline solution is used, and the second conductor is used. As the material, a metal or a conductive material which is insoluble or hardly soluble in the alkaline solution can be used.

Further, in the above-mentioned embodiment, the wiring substrate used for the driver for driving the liquid crystal panel is described as an example of the wiring substrate, but the present invention is not limited to this, and it can be applied to wiring substrates used for various purposes. Needless to say. At this time, the method of mounting the semiconductor chip on the wiring board is
The present invention is not limited to the COF method described in the above embodiments, but may be applied to a wiring board provided with device holes, such as a wiring board used for a TBGA (Tape Ball Grid Array) package.

[0078]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1) In the method of manufacturing a wiring board in which the conductor wiring is formed by using the additive method, it is possible to reduce short-circuit defects of the conductor wiring.

(2) In the method of manufacturing a wiring board in which the conductor wiring is formed by using the additive method, the flatness of the surface of the conductor wiring can be improved.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a schematic configuration of a wiring board according to an embodiment of the present invention, and is a plan view of the entire wiring board.

2 is a schematic diagram showing a schematic configuration of a wiring board of the present embodiment, FIG. 2 (a) is an enlarged plan view of a region L2 of FIG. 1, FIG.
2B is a sectional view taken along the line AA ′ of FIG.

FIG. 3 is a schematic view for explaining the method for manufacturing the wiring board of the present embodiment, and FIGS. 3A and 3B are cross-sectional views in each step.

FIG. 4 is a schematic view for explaining the method for manufacturing the wiring board of the present embodiment, and FIGS. 4 (a) and 4 (b) are cross-sectional views in each step.

FIG. 5 is a schematic view for explaining the method for manufacturing the wiring board according to the present embodiment, and FIGS. 5A and 5B are cross-sectional views in each step.

FIG. 6 is a schematic plan view for explaining the method for manufacturing a semiconductor device using the wiring board according to the present embodiment.

FIG. 7 is a schematic view for explaining the method for manufacturing a semiconductor device using the wiring board of the present embodiment, which is a cross-sectional view of FIG.

8 is a schematic view for explaining the method for manufacturing a semiconductor device using the wiring board of the present embodiment, which is an enlarged plan view of a region L2 of FIG.

FIG. 9 is a schematic plan view for explaining the method for manufacturing a semiconductor device using the wiring board according to the present embodiment.

FIG. 10 is a schematic plan view for explaining the method for manufacturing a semiconductor device using the wiring board according to the present embodiment.

11A and 11B are schematic diagrams showing a schematic configuration of a conventional wiring board (tape carrier). FIG. 11A is a plan view of the wiring board, and FIG. 11B is BB ′ of FIG. 11A. It is sectional drawing in a line.

FIG. 12 is a schematic diagram for explaining a conventional method for manufacturing a wiring board, and FIGS. 12 (a) and 12 (b) are cross-sectional views in each step.

FIG. 13 is a schematic diagram for explaining a conventional method for manufacturing a wiring board, and FIGS. 13A and 13B are cross-sectional views in each step.

FIG. 14 is a schematic cross-sectional view for explaining the conventional method for manufacturing a wiring board.

FIG. 15 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device using a conventional wiring board.

FIG. 16 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device using a conventional wiring board.

FIG. 17 is a schematic cross-sectional view for explaining another method for manufacturing a semiconductor device using a conventional wiring board.

FIG. 18 is a schematic plan view showing a schematic configuration of a wiring board used for a conventional driver for driving a liquid crystal panel.

19 is a schematic diagram showing a schematic configuration of a wiring board used for a conventional driver for driving a liquid crystal panel, and is an enlarged plan view of a region L2 of FIG.

FIG. 20 is a schematic cross-sectional view for explaining a conventional method of manufacturing a semiconductor device by the COF method.

FIG. 21 is a schematic cross-sectional view for explaining a conventional method of manufacturing a semiconductor device by the COF method.

FIG. 22 is a schematic cross-sectional view for explaining the conventional method of manufacturing a semiconductor device by the COF method.

FIG. 23 is a schematic cross-sectional view for explaining the problems of the conventional wiring board.

FIG. 24 is a schematic cross-sectional view for explaining the problems of the conventional wiring board.

[Explanation of symbols]

1 Insulation board 1A First main surface of insulating substrate 1B Second main surface of insulating substrate 1C opening (sprocket hole) 1D opening (device hole) 1E opening 2 conductor wiring 2A input signal line 2B source signal line (output signal line) 201 First conductor (chromium sputtered film) 202 First conductor protection film (copper sputter film) 203 Second conductor (electrolytic copper plating) 204 1st conductor (nickel alloy) 3 Solder protection film (solder resist) 4 terminal plating 5 Plating resist 6 semiconductor chips 601 External terminal of semiconductor chip 7 bumps 8 collets 9 light 10 Bonding tool 11 Sealing resin

Continued front page    F-term (reference) 4E351 AA04 BB01 BB33 BB35 CC03                       CC06 DD04 DD17 GG20                 5E339 AA02 AB02 AC06 AD01 BC02                       BD03 BD08 BD11 BE13 BE17                       CD05 CE01 GG01                 5E343 AA03 AA05 AA18 AA33 BB24                       BB38 CC62 DD25 DD43 ER13                       ER16 ER18 ER26 GG06 GG20                 5F044 MM03 MM22 MM48

Claims (5)

[Claims] 1. A thin film made of a first conductor is formed on the entire surface of an insulating substrate, a second conductor having a predetermined pattern is formed on the first conductor, and the second conductor of the first conductor is formed. In a method of manufacturing a wiring board, wherein an unetched portion is removed by etching to form a conductor wiring, a conductor in which the second conductor is soluble in a solution in which the second conductor is insoluble or hardly soluble is used as the first conductor. And a method for manufacturing a wiring board. 2. The method for manufacturing a wiring board according to claim 1, wherein a thin film is formed by using chromium (Cr) as the first conductor and a pattern is formed by using copper as the second conductor. . 3. The method of manufacturing a wiring board according to claim 2, wherein after the pattern is formed using the copper, the chromium thin film is etched using a potassium permanganate solution. 4. A wiring board in which a conductor wiring having a predetermined pattern is provided on a surface of an insulating substrate, wherein the conductor wiring is formed by laminating a second conductor with a first conductor as a base layer, and the first conductor is The wiring board, wherein the second conductor is made of a conductor that is soluble in a solution that is insoluble or hardly soluble. 5. The wiring board according to claim 4, wherein the first conductor is chromium (Cr) and the second conductor is copper (Cu).