JPS59106181A - Method of producing printed circuit board - Google Patents

Method of producing printed circuit board

Info

Publication number
JPS59106181A
JPS59106181A JP21718482A JP21718482A JPS59106181A JP S59106181 A JPS59106181 A JP S59106181A JP 21718482 A JP21718482 A JP 21718482A JP 21718482 A JP21718482 A JP 21718482A JP S59106181 A JPS59106181 A JP S59106181A
Authority
JP
Japan
Prior art keywords
copper
plating layer
predetermined circuit
thin film
copper plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21718482A
Other languages
Japanese (ja)
Inventor
浩司 河野
斉宮 正一
宇佐美 昇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TOUYOU SHIGIYOU KK
TOYO SHIGYO KK
Original Assignee
TOUYOU SHIGIYOU KK
TOYO SHIGYO KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TOUYOU SHIGIYOU KK, TOYO SHIGYO KK filed Critical TOUYOU SHIGIYOU KK
Priority to JP21718482A priority Critical patent/JPS59106181A/en
Publication of JPS59106181A publication Critical patent/JPS59106181A/en
Pending legal-status Critical Current

Links

Landscapes

  • Manufacturing Of Printed Wiring (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明はプリント配線基板の製造方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a printed wiring board.

従来、プリント配線基板の製造に関して種々の方法が考
えられている。例えば、絶縁基板上に厚さが35ミクロ
ン程度の銅箔を貼着した後、所定回路部分にエツチング
レジスト被膜を形成し、次に所定回路部分を除く銅箔を
エツチングにより除去した後、該エツチングレジスト被
膜を剥離することによって所定回路を形成する方法があ
る。この方法は所定回路部分を除く厚さが35ミクロン
程度の銅箔をエツチングにより除去しなければならず、
このエツチングの際、多量の銅が無駄に消費され、しか
も所定回路部分の銅箔にエツチングによるサイドエッチ
が発生する危険性が極めて高く、正確々回路導体幅を得
るには高価な装置と充分な管理を必要としだ。
Conventionally, various methods have been considered for manufacturing printed wiring boards. For example, after pasting a copper foil with a thickness of about 35 microns on an insulating substrate, an etching resist film is formed on a predetermined circuit portion, and then the copper foil except for the predetermined circuit portion is removed by etching. There is a method of forming a predetermined circuit by peeling off a resist film. This method requires removing the copper foil with a thickness of approximately 35 microns excluding the designated circuit portion by etching.
During this etching, a large amount of copper is wasted, and there is an extremely high risk that side etching will occur in the copper foil in the predetermined circuit area. It requires management.

また、従来法には絶縁基板上に所定回路部分をメノギ法
により直接形成する方法もあるが、この方法は絶縁基板
を塩化第一錫溶液と非常に高価な塩化パラジウム溶液に
、高精度の薬液管理を行いながら順次浸漬させ、該絶縁
基板表面に金属パラジウムを析出させる活性化処理工程
と、所定回路部分を除く該絶縁基板上にメツキレシスト
被膜を形成する工程、さらに化学銅メッキにより所定回
路部分に銅メッキ層を形成させる]二稈とが必要であり
、該銅メッキ層のjワみがさらに必要な場合には、該銅
メツキ層表面にさらに電気銅メッキを施し、該銅メッキ
層を成長させなければならなかった。
In addition, there is a conventional method in which a predetermined circuit part is directly formed on an insulating substrate using the agate method, but in this method, the insulating substrate is coated with a stannous chloride solution and a very expensive palladium chloride solution using a high-precision chemical solution. An activation treatment step in which metal palladium is deposited on the surface of the insulating substrate by sequential immersion under controlled conditions, a step of forming a metal resist film on the insulating substrate excluding predetermined circuit portions, and a further step in which predetermined circuit portions are coated with chemical copper plating. Forming a copper plating layer] If a double culm is required and further warping of the copper plating layer is required, electrolytic copper plating is further applied to the surface of the copper plating layer and the copper plating layer is grown. I had to let it happen.

このように、従来法においては複雑々製造工程を必要と
し、銅などの金属の無駄な消費と、塩化パラジウムなど
の高価な薬液を用いると同時に、その薬液管理は多大の
労力を要し、非常に難しいものとされていた。本発明は
、これら従来法の欠点を解消し、信頼性の高いプリント
配線基板を簡易な工程で、銅などの金用の無駄力消費を
減少せしめ、高価な薬液を用いることなく、薬液管理の
困難さをも減少させることによって安価に製造する方法
を提供するものである。
As described above, the conventional method requires complicated manufacturing processes, wastes metals such as copper, uses expensive chemicals such as palladium chloride, and requires a great deal of effort to manage the chemicals. was considered difficult. The present invention eliminates the shortcomings of these conventional methods, makes it possible to manufacture highly reliable printed wiring boards through a simple process, reduces wasted power consumption for copper and other metals, and improves chemical management without using expensive chemicals. It also provides a method of manufacturing at low cost by reducing the difficulty.

以下、本発明を図面に基づき説明すると、第1図、第2
図、第3図、第4図、第5図は本発明のプリント配線基
板の製造方法を示す説明図である。
Hereinafter, the present invention will be explained based on the drawings.
3, 4, and 5 are explanatory diagrams showing the method for manufacturing a printed wiring board according to the present invention.

第1図は、サンドブラスト加工などにより表面粗化を施
したガラスエボキン樹脂板、寸たけポリエステル樹脂フ
ィルムやポリイミド樹脂フィルムなどの絶縁基板(1)
−Lに真空蒸着法、寸たはスパッタリング法により銅薄
膜(2)を形成した状態を示しており、該絶縁基板(1
)表面に施した粗化加工は該銅薄膜(2)との密着性を
増大させるためのものである。
Figure 1 shows an insulating substrate (1) such as a glass Evokin resin plate whose surface has been roughened by sandblasting etc., a thin polyester resin film, or a polyimide resin film.
-L shows a state in which a copper thin film (2) is formed by vacuum evaporation, thin film or sputtering, and the insulating substrate (1
) The roughening process applied to the surface is for increasing the adhesion with the copper thin film (2).

第2図は、該銅薄膜(2)表面の所定回路部分を−除く
部分に、アルカリ溶解型メツキレシスト被膜(3)を印
刷法、写真法、あるいは転写法などにより形成した後、
乾燥、硬化させた状態を示している。
FIG. 2 shows that after forming an alkali-soluble metskiresist coating (3) on the surface of the copper thin film (2) except for a predetermined circuit area by a printing method, a photographic method, or a transfer method,
It shows the dried and hardened state.

第3図は、酸性銅メッキ浴にて該所定回路部分に銅メッ
キ層(4)を形成した状態を示している。
FIG. 3 shows a copper plating layer (4) formed on the predetermined circuit portion in an acidic copper plating bath.

尚、この工程における該銅メッキ層(4)は、電気銅メ
ッキ法、寸たけ化学銅メッキ法のいずれのメッキ法を用
いて形成してもよい。
The copper plating layer (4) in this step may be formed using either electrolytic copper plating or dimension chemical copper plating.

第4図は、酸性のメッキ浴にてアルカリ性エツチング液
に対して耐腐食性のあるニッケル、錫鉛合金、錫ニッケ
ル合金などの金属メッキ層(5)を該所定回路部分に形
成した状態を示している。この工程においても、該金属
メッキ層(5)は電気メツキ法、捷だは化学メッキ法の
いずれのメッキ法を用いて形成してもよい。このように
して形成した金属メッキ層(5)は、後記第5図に示す
エツチング液稈でのエツチングレジスト被膜として作用
すると同時に該銅メッキ層(4)の酸化防止としての作
用をも有している。
Figure 4 shows a state in which a metal plating layer (5) made of nickel, tin-lead alloy, tin-nickel alloy, etc., which is resistant to corrosion against alkaline etching liquid in an acidic plating bath, is formed on the predetermined circuit portion. ing. In this step as well, the metal plating layer (5) may be formed using any of the electroplating methods, plating methods, or chemical plating methods. The metal plating layer (5) thus formed acts as an etching resist film in the etching solution shown in FIG. There is.

さらに第5図は、アンモニアエツチング液などのアルカ
リ性エツチング液にて該アルカリ溶解型メツキレシスト
被膜(3)、及び該所定回路部分を除く部分の銅薄膜(
2)を除去し、該所定回路部分を有するプリント配線基
板が完成した状態を示している。
Furthermore, FIG. 5 shows that the alkaline soluble metal oxide film (3) is etched with an alkaline etching solution such as an ammonia etching solution, and the copper thin film (
2) is removed, and a printed wiring board having the predetermined circuit portion is completed.

このように、本発明によるプリント配線基板の製造方法
は第1図の説明図に示しだように、真空蒸着法、寸だけ
スパッタリング法により形成した銅薄膜を用いるため、
従来法のごとく、高価で、薬液管理の困難な塩化パラジ
ウムなどを用いる化学銅メッキの核の形成を必要としな
い0 さらに、本発明に用いるアルカリ溶解型メツキレシスト
被膜(3)は、第3図において所定回路部分に銅メッキ
層(4)を形成する際のマスキングの役割と、第4図に
おける所定回路部分に金属メッキ層(5)を形成する際
のマスキングの役割を有するたけでなく、第5図におけ
る所定回路部分以外の銅薄膜(2)のエツチングの際、
除去されてし寸うので、従来法のごとくエツチング工程
後の剥離工程を必要とせず、工程か簡略化される。しか
も、エツチングに要する時間は、銅薄膜(2)か真空蒸
着法、あるいけスパッタリング法で形成されている為、
膜厚が非常に薄く、その為エツチングを瞬時で完了させ
ることができる。
As described above, as shown in the explanatory diagram of FIG. 1, the method for manufacturing a printed wiring board according to the present invention uses a thin copper film formed by a vacuum evaporation method or a sputtering method.
Unlike conventional methods, formation of chemical copper plating nuclei using palladium chloride, which is expensive and difficult to control, is not required.Furthermore, the alkali-dissolved metsukire cyst coating (3) used in the present invention In addition to having a masking role when forming a copper plating layer (4) on a predetermined circuit portion and a masking role when forming a metal plating layer (5) on a predetermined circuit portion in FIG. When etching the thin copper film (2) other than the designated circuit portion in the figure,
Since it can be removed easily, there is no need for a peeling process after the etching process as in the conventional method, which simplifies the process. Moreover, the time required for etching is limited because the copper thin film (2) is formed by vacuum evaporation or sputtering.
The film thickness is extremely thin, so etching can be completed instantly.

よって、従来法に比較して高い生産性が得られる利点を
有している。
Therefore, it has the advantage that higher productivity can be obtained compared to the conventional method.

このように、本発明は従来法のごとく、高価、且つ困難
な管理を必要とする薬液を用いず、少々い工程で短時間
に高品質のプリント配線基板を製造できる、実用上極め
て有益、多大な効果をイ」するものである。
As described above, the present invention is a method that is extremely useful in practice and has many benefits, as it enables the production of high-quality printed wiring boards in a short period of time in a relatively simple process without using chemicals that are expensive and require difficult management, unlike conventional methods. It has a certain effect.

【図面の簡単な説明】[Brief explanation of drawings]

第1〜5図は、本発明のプリント配線基板の製造方法を
示す説明図。 1・・・絶縁基板 2・・・銅薄膜 3・・・アルカリ溶解型メツキレシスト被膜4・・・銅
メッキ層 5・・・金属メッキ層 特許出願人 東洋紙業株式会社 391
1 to 5 are explanatory diagrams showing the method of manufacturing a printed wiring board of the present invention. 1... Insulating substrate 2... Copper thin film 3... Alkali-dissolved metal resist coating 4... Copper plating layer 5... Metal plating layer Patent applicant Toyo Shigyo Co., Ltd. 391

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板上に真空蒸着法、丑だけスパッタリング法によ
り銅薄膜を形成した後、該銅薄膜表面の所定回路部分を
除く部分にアルカリ溶解型メツキレシスト被膜を形成し
、次に酸性銅メッキ浴にて該所定回路部分に銅メッキ層
を形成し、さらに該銅メツキ層表面にアルカリ性エツチ
ング液に対して耐腐食性のある金属メッキ層を形成した
後、アルカリ性エツチング液にて該アルカリ溶解型メツ
キレシスト被膜、及び該所定回路部分を除く銅薄膜を除
去することを特徴とするプリント配線基板の一製造方法
After forming a copper thin film on an insulating substrate by vacuum evaporation and ox sputtering, an alkali-dissolved metal resist coating is formed on the surface of the copper thin film except for the predetermined circuit area, and then an acidic copper plating bath is used to form the copper thin film. After forming a copper plating layer on a predetermined circuit portion and further forming a metal plating layer that is resistant to corrosion with an alkaline etching solution on the surface of the copper plating layer, the alkali-dissolved metal-resist coating is removed using an alkaline etching solution. A method for manufacturing a printed wiring board, comprising removing the copper thin film except for the predetermined circuit portion.
JP21718482A 1982-12-10 1982-12-10 Method of producing printed circuit board Pending JPS59106181A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21718482A JPS59106181A (en) 1982-12-10 1982-12-10 Method of producing printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21718482A JPS59106181A (en) 1982-12-10 1982-12-10 Method of producing printed circuit board

Publications (1)

Publication Number Publication Date
JPS59106181A true JPS59106181A (en) 1984-06-19

Family

ID=16700174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21718482A Pending JPS59106181A (en) 1982-12-10 1982-12-10 Method of producing printed circuit board

Country Status (1)

Country Link
JP (1) JPS59106181A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6149496A (en) * 1984-08-16 1986-03-11 ローベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Method of forming solder layer on inorganic substrate
JPH02303086A (en) * 1989-05-17 1990-12-17 Hitachi Ltd Manufacture of printed wiring board, and sputter deposition equipment and copper-clad laminate therefor
JP2009071066A (en) * 2007-09-13 2009-04-02 Sumitomo Metal Mining Package Materials Co Ltd Chip on film (cof) wiring substrate and manufacturing method of the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6149496A (en) * 1984-08-16 1986-03-11 ローベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Method of forming solder layer on inorganic substrate
JPH02303086A (en) * 1989-05-17 1990-12-17 Hitachi Ltd Manufacture of printed wiring board, and sputter deposition equipment and copper-clad laminate therefor
JP2009071066A (en) * 2007-09-13 2009-04-02 Sumitomo Metal Mining Package Materials Co Ltd Chip on film (cof) wiring substrate and manufacturing method of the same

Similar Documents

Publication Publication Date Title
US5733466A (en) Electrolytic method of depositing gold connectors on a printed circuit board
US3691632A (en) Method of making multi layer circuit boards
JPS60147192A (en) Method of producing printed circuit board
JP3112128B2 (en) Method for producing metal-coated glass epoxy substrate
JPS59106181A (en) Method of producing printed circuit board
JPH03196597A (en) Manufacture of printed wiring board
JPS61102093A (en) Manufacture of printed circuit board
JPS5999793A (en) Printed circuit board
JPS61140194A (en) Multilayer circuit board and manufacture thereof
JPS59106191A (en) Method of producing circuit board with through hole
JPS6138638B2 (en)
JPS6170790A (en) Method of producing printed circuit board
JPS59155994A (en) Method of producing printed circuit board
JPS6372189A (en) Manufacture of circuit board
JPS6255997A (en) Manufacture of substrate for printed circuit
JPS6167289A (en) Method of producing printed circuit board
JPS6345893A (en) Manufacture of printed wiring board
JPS6387787A (en) Manufacture of printed wiring board
JPH05259609A (en) Manufacture of printed wiring board
JPS613494A (en) Method of producing printed board
JPS62257788A (en) Manufacture of flexible printed circuit
JPS6052087A (en) Method of producing printed board
JPH03175695A (en) Manufacture of through hole printed wiring board
JPS62225000A (en) Manufacture of printed circuit board
JPS63187687A (en) Manufacture of printed wiring board