JPS6167289A - Method of producing printed circuit board - Google Patents
Method of producing printed circuit boardInfo
- Publication number
- JPS6167289A JPS6167289A JP18908984A JP18908984A JPS6167289A JP S6167289 A JPS6167289 A JP S6167289A JP 18908984 A JP18908984 A JP 18908984A JP 18908984 A JP18908984 A JP 18908984A JP S6167289 A JPS6167289 A JP S6167289A
- Authority
- JP
- Japan
- Prior art keywords
- copper plating
- plating layer
- different metal
- printed wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、フルアディティブ法によるプリント配線板の
製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a printed wiring board by a fully additive method.
従来、フルアディティブ法によるプリント配線板の製造
方法においては、導体を化学銅メッキ処理のみによって
完成させでいるが、この化学銅メッキ処理のみによる回
路形成は析出銅がバラツキ易く、接続信頼性の向上が期
待できないものであった。Conventionally, in the fully additive manufacturing method of printed wiring boards, conductors are completed only by chemical copper plating, but when forming circuits only by chemical copper plating, the deposited copper tends to vary, making it difficult to improve connection reliability. was something that could not be expected.
しかるに、本発明はプリント配線板をフルアディティブ
法により完成するに際し、化学銅メッキ、電気銅メッキ
および異金属メッキを併用することに、より高信頼性の
プリント配線板を提供するものである。However, the present invention provides a more reliable printed wiring board by using chemical copper plating, electrolytic copper plating, and different metal plating in combination when completing the printed wiring board by a fully additive method.
以下、本発明の一実施例を第１図乃至第３図と共に説明
する。先ず、第１図（ａ）に示すように積層板からなる
絶縁基体（１）を準備し、スルホールを形成する部分に
第１図（ｂ）に示すようにドリル加工またはパンチング
加工により透孔（２）を形成する。次に、第１図（ｃ）
に示すように絶縁基体（１）の表面および透孔（２）の
内壁を表面粗面（３）化処理を施す。通常この表面粗面
化処理は化学処理にて行なわれ、有機溶剤で表面の油分
の除去後に、クロム酸と硫酸との混合溶液により表面処
理され５、水洗される。An embodiment of the present invention will be described below with reference to FIGS. 1 to 3. First, as shown in FIG. 1(a), an insulating substrate (1) made of a laminate is prepared, and a through hole (1) is formed in the portion where the through hole is to be formed by drilling or punching as shown in FIG. 1(b). 2) Form. Next, Figure 1(c)
As shown in Figure 2, the surface of the insulating substrate (1) and the inner wall of the through hole (2) are subjected to surface roughening treatment (3). Usually, this surface roughening treatment is carried out by chemical treatment, and after removing oil from the surface with an organic solvent, the surface is treated with a mixed solution of chromic acid and sulfuric acid5, and then washed with water.
引続き、活性化処理し、粗面化された絶縁基体−（１）
の表面および透孔（２）の内壁に第１図（ｄ）に示すよ
うに化学銅メッキの核（４）、通常はパラジウム核を析
出させる。しかる後、第１図（ｅ）に示すように絶縁基
体（１）の全面に化学銅メッキ、つまりパネルメッキを
施し、第１の銅メッキ層（５）を形成する。この銅メッ
キ層（５）厚は３〜５μｍ程度である。この化学銅メッ
キ処理後、第１図Ｃ１）に示すように所要箇所にメッキ
レシスト（６）を印刷または写真処理法によって形成す
る。次いで、メッキレシスト（６）で被覆されていない
第１の銅メッキ層（５）に対して電気銅メッキ、つまり
部分メッキを施し、第２の銅メッキ層（７）を第２図（
ａ）に示すように形成する。この銅メッキ層（７）厚は
加〜カμｍ程度である。さらに、第２の銅メッキ層（７
）上に錫または半田などの異金属メッキを施し、第２図
（ｂ）に示すように異金属メッキ層（８）を５〜８μｍ
程度形成し、エツチングレジストとしての膜厚を確保す
る。第２図（ｃ）に示し・たようにメッキレシスト（６
）を剥離した後に、第１力鋼メッキ層（５）をエツチン
グ処理して除去すると第２図（ｄ）に示すように所要の
回路パターンを形成したプリント配線板（９）が得られ
る。なお、銅スルホールメッキ仕上げの場合には第３図
に示すようにさらに異金属メッキ層（８）を酸処理によ
って除去する。Subsequently, the insulating substrate was activated and roughened - (1)
As shown in FIG. 1(d), chemical copper plating nuclei (4), usually palladium nuclei, are deposited on the surface of the plate and the inner wall of the through hole (2). Thereafter, as shown in FIG. 1(e), the entire surface of the insulating substrate (1) is subjected to chemical copper plating, that is, panel plating to form a first copper plating layer (5). The thickness of this copper plating layer (5) is about 3 to 5 μm. After this chemical copper plating treatment, plating resists (6) are formed at required locations by printing or photo processing, as shown in FIG. 1 C1). Next, the first copper plating layer (5) not covered with the plating resist (6) is subjected to electrolytic copper plating, that is, partial plating, and the second copper plating layer (7) is coated as shown in FIG.
Form as shown in a). The thickness of this copper plating layer (7) is about 1 to 10 μm. Furthermore, a second copper plating layer (7
) is plated with a different metal such as tin or solder, and the different metal plating layer (8) is applied to a thickness of 5 to 8 μm as shown in Figure 2(b).
The thickness of the etching resist is ensured. As shown in Figure 2(c), the plating resist (6
) and then remove the first steel plating layer (5) by etching to obtain a printed wiring board (9) on which a desired circuit pattern is formed, as shown in FIG. 2(d). In the case of copper through-hole plating, the dissimilar metal plating layer (8) is further removed by acid treatment as shown in FIG.
以上にて述べたように、本発明においては比較的薄い（
３〜５μｍ）第１の銅メッキ層を化学銅メッキ処理によ
って形成し、その上に比較的厚い（２０〜３０μｍ）第
２の銅メッキ層を電気銅メッキ処理によって形成し、さ
らに異金属メッキ層を形成するように構成したために、
従来の回路形成が化学銅メッキ処理によって構成されて
いたのに比較すると、析出鋼のバラツキが少なく、シた
がうて接続信頼の高いプリント配線板を提供できるもの
である。また、第１の銅メッキ層は３〜５μｍと薄い膜
厚であるために、導体パターンのファインパターン化を
はかることもできるものである。As mentioned above, in the present invention, the relatively thin (
3 to 5 μm) A first copper plating layer is formed by chemical copper plating, a relatively thick (20 to 30 μm) second copper plating layer is formed thereon by electrolytic copper plating, and then a different metal plating layer is formed. Because it was configured to form
Compared to conventional circuits formed by chemical copper plating, there is less variation in deposited steel, and it is possible to provide a printed wiring board with high connection reliability. Further, since the first copper plating layer has a thin film thickness of 3 to 5 μm, it is possible to form a fine conductor pattern.
第１図（ａ）〜（ｆ）、第２図（ａ）〜（ｄ）および第
３図は本発明に係る製造方法を説明するための工程図で
ある０
図中、（１）・・・絶縁基板、（２）・・・透孔、（３
）・・・粗面、（４）・・・核、（５）、（７１・・・
銅メッキ層、（６）・・・メッキレシスト、（８）・・
・異金属メッキ層、（９）プリント配線板。Figures 1 (a) to (f), Figures 2 (a) to (d), and Figure 3 are process diagrams for explaining the manufacturing method according to the present invention. In the figures, (1)...・Insulating substrate, (2)...Through hole, (3
)... Rough surface, (4)... Nucleus, (5), (71...
Copper plating layer, (6)...Plating resist, (8)...
- Different metal plating layer, (9) printed wiring board.
Claims (2)
活性化処理し、活性化処理後に全面を化学銅メッキ処理
により第１の銅メッキ層を形成しメッキレジスト形成後
に電気銅メッキ処理により第１の銅メッキ層上に第２の
銅メッキ層を形成し、さらに第２の銅メッキ層上に異金
属メッキ処理により異金属メッキ層を形成し、メッキレ
ジスト剥離後に異金属メッキ層をエッチングレジストと
して第１の銅メッキ層をエッチング処理し、除去してな
るプリント配線板の製造方法。(1) Forming through holes in the insulating substrate and roughening the surface,
Activation treatment is performed, and after the activation treatment, a first copper plating layer is formed on the entire surface by chemical copper plating treatment, and after a plating resist is formed, a second copper plating layer is formed on the first copper plating layer by electrolytic copper plating treatment. Further, a different metal plating layer is formed on the second copper plating layer by a different metal plating process, and after the plating resist is removed, the first copper plating layer is etched and removed using the different metal plating layer as an etching resist. A method of manufacturing a printed wiring board.
ッキ層を除去してなるプリント配線板の製造方法。(2) A method for manufacturing a printed wiring board according to claim (1), further comprising removing a different metal plating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18908984A JPS6167289A (en) | 1984-09-10 | 1984-09-10 | Method of producing printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18908984A JPS6167289A (en) | 1984-09-10 | 1984-09-10 | Method of producing printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6167289A true JPS6167289A (en) | 1986-04-07 |
Family
ID=16235139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18908984A Pending JPS6167289A (en) | 1984-09-10 | 1984-09-10 | Method of producing printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6167289A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6484698A (en) * | 1987-09-26 | 1989-03-29 | Matsushita Electric Works Ltd | Manufacture of multilayer circuit board |
-
1984
- 1984-09-10 JP JP18908984A patent/JPS6167289A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6484698A (en) * | 1987-09-26 | 1989-03-29 | Matsushita Electric Works Ltd | Manufacture of multilayer circuit board |
| JPH0565078B2 (en) * | 1987-09-26 | 1993-09-16 | Matsushita Electric Works Ltd |
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