JPS5999793A - Printed circuit board - Google Patents

Printed circuit board

Info

Publication number
JPS5999793A
JPS5999793A JP20771982A JP20771982A JPS5999793A JP S5999793 A JPS5999793 A JP S5999793A JP 20771982 A JP20771982 A JP 20771982A JP 20771982 A JP20771982 A JP 20771982A JP S5999793 A JPS5999793 A JP S5999793A
Authority
JP
Japan
Prior art keywords
plating
resist
copper
solder
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20771982A
Other languages
Japanese (ja)
Inventor
杉若 伸章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
YAMASHITA KAKOU KK
Original Assignee
YAMASHITA KAKOU KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by YAMASHITA KAKOU KK filed Critical YAMASHITA KAKOU KK
Priority to JP20771982A priority Critical patent/JPS5999793A/en
Publication of JPS5999793A publication Critical patent/JPS5999793A/en
Pending legal-status Critical Current

Links

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は、プリント配線板の構造に関し、特に、銅エツ
チングのためのメタルレジストの改良に係る。
DETAILED DESCRIPTION OF THE INVENTION This invention relates to printed wiring board structures and, more particularly, to improved metal resists for copper etching.

第1図(a)〜(g)は、従来の銅エツチング法による
プリント配線板の製造方法の一例を示す。
FIGS. 1(a) to 1(g) show an example of a method for manufacturing a printed wiring board using a conventional copper etching method.

即ち、銅張積層板1に穴明は加工(第1図(a))して
パネル銅めっき2を施しく第1図(b))、該パネル銅
めっき2上にメタルレジストめっき用レジスト3を印刷
して、該メタルレジストめっき用レジスト3,3間に直
接メタルレノストとしてのはんだめっき4を施しく第1
図(C))、その後、メタルレジストめっき用レジスト
3を溶剤等で除去しく第1図(d))、はんだめっき4
をメタルレゾストとして・ぐネル銅めっき2及び銅張積
層板1の銅箔1aをエツチングしく第1図(e))、そ
の後、はんだめっき4を剥離を等によシ除去して(第1
図(f))、ソルダコート用レジスト5を印刷して、ソ
ルダコート6を施していく(第1図(g))のである・
なお、図中、符号7はスルホールであシ、ここにも・母
ネル銅めっき2及びソルダコート6が施される。
That is, holes are formed in the copper-clad laminate 1 (FIG. 1(a)), panel copper plating 2 is applied (FIG. 1(b)), and a resist 3 for metal resist plating is applied on the panel copper plating 2. , and solder plating 4 as a metal resist is applied directly between the resists 3 and 3 for metal resist plating.
Figure (C)), then remove the resist 3 for metal resist plating with a solvent etc. (Figure 1 (d)), solder plating 4.
As a metal resist, the Gunnel copper plating 2 and the copper foil 1a of the copper-clad laminate 1 are etched (Fig. 1(e)), and then the solder plating 4 is removed by peeling or the like (first
(Fig. 1 (f)), print the resist 5 for solder coating, and apply the solder coat 6 (Fig. 1 (g)).
Note that in the figure, reference numeral 7 indicates a through hole, and a mother plate copper plating 2 and a solder coat 6 are applied here as well.

しかしながら、はんだめっき4は多孔性で組織カ粗く、
ピンホールがあるので、これを補償するために膜厚を厚
くする必要がある(約7〜14μm)上、これを剥離液
等によシ除去してソルダコート6を施す必要があるので
、めっきの作業時間が長く(通常、15〜17分間)、
除去時間も多く、とられ(約3〜5分間)、消費電力が
多くなシ、コスト高騰を招いて因る。また、はんだめっ
き4はあまシフラットではないため、プリント配線の目
視検査が比較的困難であ多、プリント配線の欠損部の発
見率が悪い。
However, solder plating 4 is porous and has a coarse structure.
Since there are pinholes, it is necessary to make the film thicker (approximately 7 to 14 μm) to compensate for this, and it is also necessary to remove this with a stripping solution and apply solder coat 6, so plating The working time is long (usually 15-17 minutes),
Removal time is long (approximately 3 to 5 minutes), and power consumption is high, leading to a rise in costs. Furthermore, since the solder plating 4 is not flat, it is relatively difficult to visually inspect the printed wiring, and the rate of finding defective parts of the printed wiring is low.

従って本発明の目的は、製造能率が良く、製造コストの
低減等ができるプリント配線板を提供することにある。
Therefore, an object of the present invention is to provide a printed wiring board that has good manufacturing efficiency and can reduce manufacturing costs.

而して、その要旨は、銅エツチングのメタルレジストと
してスズ・ニッケルめっきを用い、残存させた該メタル
レジストの上にソルダコートを施したことである。
The gist is that tin-nickel plating is used as a metal resist for copper etching, and a solder coat is applied on the remaining metal resist.

第2図(a)〜(f)は、本発明の一実施例を示す。本
例は、第1図の銅張積層板1を用い、第1図の製造工程
と基本的に同じ工程によるものであるが、第1図のはん
だめっき4の代わシにスズ・ニッケルめっき8をメタル
レジストとしてメタルレノストめっき用レジス)13.
13間に薄く(約0.3〜0.6μm)施すようにして
おシ、かつ、これを除去せず、残存させたままソルダコ
ート用レジスト15全印刷し、ソルダコート16を該ス
ズ・ニッケルめっき8の上に施すようにしている(第2
図(f))。
FIGS. 2(a) to 2(f) show an embodiment of the present invention. In this example, the copper-clad laminate 1 shown in FIG. 1 is used, and the manufacturing process is basically the same as that shown in FIG. 1, but the solder plating 4 in FIG. as a metal resist (resist for metal renost plating) 13.
Apply a thin layer (approximately 0.3 to 0.6 μm) between solder coats 13 and print the entire solder coat resist 15 while leaving it without removing it. It is applied on top of plating 8 (second
Figure (f)).

このスズ・ニッケルめっき8は、主に、塩化第一スズ、
硫酸ニッケル、ピロリン酸カリウム〜共析剤、光沢剤等
から成シ、融点が高く、組織が緻密である。乙のため、
めっき膜厚を薄くでき(これに付随してメタルレジスト
めっき用レジスト13の膜厚も薄くてき丞)、かつ、こ
のスズ・ニッケルめりき8を残存させたままソルダコー
ト16を施すことができるのである。従って、このスズ
・ニッケルめっき8のめっき作業時間はきわめて短く(
約2〜4分間)、また、めっきレジスト除去の工程も全
く省略されるため、全体の製造能率が従来のはんだめっ
き使用の場合と比べて大幅に向上する。又、めっき膜厚
及びメタルレジストめっき用レジスト13の膜厚の減少
によシ消費電力及び材料が大幅に節減され、薬品代等も
節約されるため、総合的に製造コストの和尚な低減とな
る。
This tin-nickel plating 8 is mainly made of stannous chloride,
It is made of nickel sulfate, potassium pyrophosphate, eutectoid, brightening agent, etc., and has a high melting point and a dense structure. For you,
The plating film thickness can be made thinner (correspondingly, the film thickness of the resist 13 for metal resist plating can also be made thinner), and the solder coat 16 can be applied while the tin/nickel plating 8 remains. be. Therefore, the plating time for this tin-nickel plating 8 is extremely short (
(about 2 to 4 minutes), and the step of removing the plating resist is also completely omitted, so the overall manufacturing efficiency is greatly improved compared to the case of using conventional solder plating. In addition, by reducing the plating film thickness and the film thickness of the resist 13 for metal resist plating, power consumption and materials are significantly reduced, and chemical costs are also saved, resulting in an overall modest reduction in manufacturing costs. .

さらに、スズ・ニッケルめっき8が比較的フラットであ
るためプリント配線の目視検査も比較的容易となシ、プ
リント配線の欠損部等が容易に発見される等の種々の効
果が発揮されるのである。
Furthermore, since the tin/nickel plating 8 is relatively flat, visual inspection of the printed wiring is relatively easy, and defects in the printed wiring can be easily discovered, among other effects. .

本発明は第2図に示した構造の両面プリント配線板以外
にも、穏々構造の両面プリント配線板や片面プリント配
線板、多層プリント配線板にも公知の技法によシ適用で
きるものであシ、第3図〜第7図にその適用例を示す。
In addition to the double-sided printed wiring board with the structure shown in FIG. 2, the present invention can also be applied to double-sided printed wiring boards, single-sided printed wiring boards, and multilayer printed wiring boards with a moderate structure using known techniques. Examples of its application are shown in FIGS. 3 to 7.

即ち、第3図(a)〜(f)は、第2図の場合と同様、
銅張積層板1を用いた場合を示すものであるが、この場
合の特徴は、メタルレジストめっき用レジス)23.2
3間に先づ、パターン銅めっき1゜を施しく第3図(C
))、その上にスズ・ニッケルめっき8を飾している(
第3図(d))点にある。
That is, in FIGS. 3(a) to (f), as in the case of FIG. 2,
This shows the case where the copper-clad laminate 1 is used, and the characteristics of this case are that the resist for metal resist plating) 23.2
First, pattern copper plating 1° is applied to Figure 3 (C).
)), on which tin-nickel plating 8 is decorated (
It is located at point (d) in Figure 3.

第4図(、)〜(f)に示した実施例の第2図の実施例
と比較した特徴は、銅張積層板1ではなく、銅箔を被覆
していない積層板11にパネル銅めっき12を施し、そ
の上に、メタルレジストめっき用レジスト33および、
スズ・ニッケルめっき18を施していることである。
The feature of the embodiments shown in FIGS. 4(a) to (f) as compared with the embodiment of FIG. 12, and on top of that, a resist 33 for metal resist plating and
It is tin-nickel plated 18.

第5図(a)〜(f)の実施例は、第4図の実施例と同
様、積層板11に・やネル銅めっき12を施したものに
適用しているものであるが、この場合の特徴は若干、厚
めのメタルレジストめっキ用レジスト43.43間に先
づ、パターン餉めっき2oを施しく第5図(b))、そ
の上にスズ・ニッケルめっき28を施している点にある
The embodiments shown in FIGS. 5(a) to 5(f) are applied to a laminate 11 coated with flannel copper plating 12, similar to the embodiment shown in FIG. The characteristic of this is that pattern glaze plating 2o is first applied between the thicker metal resist plating resists 43 and 43 (Fig. 5(b)), and then tin/nickel plating 28 is applied on top of that. It is in.

第6図(、)〜(f)の第2図と比較した特徴は、中間
の銅箔21aが既にエツチング処理されている多層銅張
積層板21にパネル銅めっき12を施し、その上に、メ
タルレジストめっき用レジスト53およびスズ・ニッケ
ルめっき38を施していることである。
The features of FIGS. 6(a) to 6(f) compared with FIG. 2 are that panel copper plating 12 is applied to the multilayer copper-clad laminate 21 on which the intermediate copper foil 21a has already been etched; A metal resist plating resist 53 and tin/nickel plating 38 are applied.

第7図(a)〜(f)は、第6図と同様の多層銅張積層
板21にパネル銅めっき12を施したものに適用してい
るものであるが、この場合の特徴は若干厚めのメタルレ
ジストめっき用レジスト63.63間に先づ、パターン
銅めっき30を施しく第7図(C))、その上にスズ・
ニッケルめっき48を施している(第7図(d))点に
ある。
Figures 7(a) to (f) are applied to a panel copper plating 12 applied to the same multilayer copper-clad laminate 21 as in Figure 6, but the characteristic of this case is that it is slightly thicker. First, pattern copper plating 30 is applied between the metal resist plating resist 63.
It is located at the point where nickel plating 48 is applied (FIG. 7(d)).

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(g)は銅エツチングのメタルレジスト
としてはんだめっきを使用していた従来のプリント配線
板の製造方法の一例を示す説明図、第2図(、)〜(f
)は銅エツチングのメタルレジストとしてスズ・ニッケ
ルめっきを使用する本発明の一実施例を示す説明図、第
3図〜第7図は本発明の他の実施例を示す説明図である
。 1・・・銅張積層板1.11・・・積層板、21・・・
多層銅張積層板、31・・・多層積層板、2.12.2
2・・・パネル銅メッキ、3,13.23,33,43
゜53.63.73・・・メタルレジストめっき用レジ
スト、4・・・はんだめっき、5.15・・・ソルダコ
ート用レジスト、6.16・・・ソルダコート、7・・
・スルホール、8,18,28,38,48,58゜6
8・・・スズ・ニッケルめっき、10.20..30゜
40・・・パターン銅メッキ。 特許出願人 山下化工株式会社 代理人弁理士 増  1)    9 第1図 (Q) (b) (C) (d) (9) 箋2−口 (Q) 第30 1坪目 (Q) (b) (C) (d) (e) (f) 扁50 (C1) (d) (e) (f) 第60 (C1)
Figures 1 (a) to (g) are explanatory diagrams showing an example of a conventional printed wiring board manufacturing method that uses solder plating as a metal resist for copper etching, and Figures 2 (,) to (f)
) is an explanatory diagram showing one embodiment of the present invention in which tin-nickel plating is used as a metal resist for copper etching, and FIGS. 3 to 7 are explanatory diagrams showing other embodiments of the present invention. 1... Copper-clad laminate 1.11... Laminate, 21...
Multilayer copper-clad laminate, 31...Multilayer laminate, 2.12.2
2...Panel copper plating, 3,13.23,33,43
゜53.63.73...Resist for metal resist plating, 4...Solder plating, 5.15...Resist for solder coat, 6.16...Solder coat, 7...
・Through hole, 8, 18, 28, 38, 48, 58°6
8...Tin/nickel plating, 10.20. .. 30゜40... pattern copper plating. Patent applicant Yamashita Kako Co., Ltd. Patent attorney Masu 1) 9 Figure 1 (Q) (b) (C) (d) (9) Paper 2-mouth (Q) No. 30 1st tsubo (Q) (b ) (C) (d) (e) (f) Bian 50 (C1) (d) (e) (f) 60th (C1)

Claims (1)

【特許請求の範囲】[Claims] 銅エツチングのメタルレジストとしてスズ・ニッケルめ
っきを用い、残存させた該メタルレジストの上にソルダ
コートを施して成る、プリント配線板。
A printed wiring board using tin-nickel plating as a metal resist for copper etching, and applying a solder coat on the remaining metal resist.
JP20771982A 1982-11-29 1982-11-29 Printed circuit board Pending JPS5999793A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20771982A JPS5999793A (en) 1982-11-29 1982-11-29 Printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20771982A JPS5999793A (en) 1982-11-29 1982-11-29 Printed circuit board

Publications (1)

Publication Number Publication Date
JPS5999793A true JPS5999793A (en) 1984-06-08

Family

ID=16544413

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20771982A Pending JPS5999793A (en) 1982-11-29 1982-11-29 Printed circuit board

Country Status (1)

Country Link
JP (1) JPS5999793A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS624396A (en) * 1985-07-01 1987-01-10 株式会社 コサク Manufacture of printed wiring board by tin alloy through hole plating
JPS624397A (en) * 1985-07-01 1987-01-10 株式会社 コサク Manufacture of copper through hole printed wiring board
JPS62200792A (en) * 1986-02-27 1987-09-04 イビデン株式会社 Printed wiring board and manufacture of the same
JPS63503585A (en) * 1986-06-18 1988-12-22 マクダーミッド,インコーポレーテッド Improved methods for printed circuit board manufacturing
JPS6489588A (en) * 1987-07-02 1989-04-04 Psi Star Inc Manufacture of pc board

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4961665A (en) * 1972-10-18 1974-06-14

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4961665A (en) * 1972-10-18 1974-06-14

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS624396A (en) * 1985-07-01 1987-01-10 株式会社 コサク Manufacture of printed wiring board by tin alloy through hole plating
JPS624397A (en) * 1985-07-01 1987-01-10 株式会社 コサク Manufacture of copper through hole printed wiring board
JPS62200792A (en) * 1986-02-27 1987-09-04 イビデン株式会社 Printed wiring board and manufacture of the same
JPS63503585A (en) * 1986-06-18 1988-12-22 マクダーミッド,インコーポレーテッド Improved methods for printed circuit board manufacturing
JPS6489588A (en) * 1987-07-02 1989-04-04 Psi Star Inc Manufacture of pc board

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