CN114501801A - Circuit board processing method and circuit board - Google Patents
Circuit board processing method and circuit board Download PDFInfo
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- CN114501801A CN114501801A CN202011173689.XA CN202011173689A CN114501801A CN 114501801 A CN114501801 A CN 114501801A CN 202011173689 A CN202011173689 A CN 202011173689A CN 114501801 A CN114501801 A CN 114501801A
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- dry film
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- 238000003672 processing method Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 230000001681 protective effect Effects 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 19
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 12
- 239000013043 chemical agent Substances 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 14
- 238000012545 processing Methods 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 238000005553 drilling Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 239000003153 chemical reaction reagent Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- LCPVQAHEFVXVKT-UHFFFAOYSA-N 2-(2,4-difluorophenoxy)pyridin-3-amine Chemical compound NC1=CC=CN=C1OC1=CC=C(F)C=C1F LCPVQAHEFVXVKT-UHFFFAOYSA-N 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- CHQMHPLRPQMAMX-UHFFFAOYSA-L sodium persulfate Substances [Na+].[Na+].[O-]S(=O)(=O)OOS([O-])(=O)=O CHQMHPLRPQMAMX-UHFFFAOYSA-L 0.000 description 1
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0073—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
- H05K3/0082—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the exposure method of radiation-sensitive masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The application discloses a processing method of a circuit board and the circuit board, comprising: forming a through hole on a substrate, wherein the substrate comprises a first surface and a second surface which are arranged oppositely, and the through hole penetrates through the first surface and the second surface; forming a conductive layer on the first surface, the second surface and the inner wall of the through hole by the substrate; covering the first surface and/or the second surface of the substrate with a dry film; forming a plurality of openings on the dry film, wherein the conductive layer at the positions of the openings is exposed, and the vertical section of each opening is in an inverted trapezoid in the direction away from the substrate; forming a conductive block on the exposed conductive layer; and removing the dry film. Through the mode, the top layer line width and the bottom layer line width of the circuit board can be very close.
Description
Technical Field
The application relates to the technical field of circuit board processing, in particular to a circuit board processing method and a circuit board.
Background
Electronic products are being refined and function of the electronic products is being improved, and in the process, wiring of the circuit board is also more and more precise, which obviously puts higher demands on the manufacturing process of the circuit board.
For the outer layer traces of a multilayer PCB, the current processing capability is typically 3mil/3mil (line width/line spacing). However, in the conventional manufacturing process, the existing process is difficult to make finer lines due to the limitations of resolution, dry film adhesion, liquid medicine stability and the like in the image transfer process. Therefore, it is necessary to provide a new circuit board manufacturing process to solve the above problems.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a processing method of a circuit board and the circuit board, so that the top layer line width and the bottom layer line width of the circuit board are very close.
In order to solve the technical problem, the application adopts a technical scheme that: provided is a processing method of a circuit board, comprising the following steps: forming a through hole on a substrate, wherein the substrate comprises a first surface and a second surface which are arranged oppositely, and the through hole penetrates through the first surface and the second surface; forming a conductive layer on the first surface, the second surface and the inner wall of the through hole by the substrate; covering the first surface and/or the second surface of the substrate with a dry film; forming a plurality of openings on the dry film, wherein the conductive layer at the positions of the openings is exposed, and the vertical section of each opening is in an inverted trapezoid in the direction away from the substrate; forming a conductive block on the exposed conductive layer; and removing the dry film.
Wherein, the ratio range of the first opening area of the opening close to the base material side to the second opening area of the opening far away from the base material side is 0.6:1-1: 1.
In the direction parallel to the first surface, the length of the openings is less than or equal to 3 mils, and the length of the dry film between adjacent openings is less than or equal to 3 mils.
Wherein the step of forming a plurality of openings on the dry film comprises: a plurality of openings are formed in the dry film using a laser.
Wherein the step of forming a plurality of openings on the dry film using a laser includes: and forming a plurality of openings on the dry film corresponding to the through hole position and the dry film at the non-through hole position by using laser.
Wherein the step of removing the dry film comprises: removing the dry film by using a chemical agent, wherein the chemical agent comprises sodium hydroxide.
Wherein, after the step of removing the dry film, comprising: covering a protective film at the position of the through hole; performing micro-etching on the conductive block and/or the conductive layer exposed from the protective film; and removing the protective film.
In order to solve the technical problem, the other technical scheme adopted by the application is as follows: provided is a wiring board including: the substrate comprises a first surface and a second surface which are arranged oppositely, and a through hole is formed in the substrate and penetrates through the first surface and the second surface; the conducting layer covers the first surface, the second surface and the inner wall of the through hole; and the conductive blocks are arranged on the conductive layer at intervals, and the vertical sections of the conductive blocks positioned on the first surface and/or the second surface are inverted trapezoids in the direction away from the base material.
And for the conductive block with the inverted trapezoid shape, the ratio of the area of the third surface close to the base material side to the area of the fourth surface far away from the base material side ranges from 0.6:1 to 1: 1.
In the direction parallel to the first surface, the lengths of the conductive blocks are less than or equal to 3mil, and the distance between adjacent conductive blocks is less than or equal to 3 mil.
Different from the prior art, the beneficial effects of the application are that: the processing method of the circuit board in the application comprises the following steps: forming a through hole on a substrate, wherein the substrate comprises a first surface and a second surface which are arranged oppositely, and the through hole penetrates through the first surface and the second surface; forming a conductive layer on the first surface, the second surface and the inner wall of the through hole by the substrate; covering a dry film on the first surface and/or the second surface of the base material, and carrying out exposure treatment on the dry film; forming a plurality of openings on the dry film, wherein the conductive layer at the positions of the openings is exposed, and the vertical section of each opening is in an inverted trapezoid in the direction away from the substrate; forming a conductive block on the exposed conductive layer; and removing the dry film. By the design scheme of the inverted trapezoid, the line widths of the top layer and the bottom layer of the circuit board can be very close, so that the processing technology of a high-precision circuit is facilitated, and the processing capacity of the precision circuit can reach 20 mu m/20 mu m (line width/line distance).
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic flow chart of an embodiment of a method for processing a circuit board according to the present application;
FIG. 2 is a schematic structural diagram of an embodiment corresponding to step S1 in FIG. 1;
FIG. 3 is a schematic structural diagram of an embodiment corresponding to step S2 in FIG. 1;
FIG. 4 is a schematic structural diagram of an embodiment corresponding to step S3 in FIG. 1;
FIG. 5 is a schematic structural diagram of an embodiment corresponding to step S4 in FIG. 1;
FIG. 6 is a schematic structural diagram of an embodiment corresponding to step S5 in FIG. 1;
FIG. 7 is an enlarged schematic view of the opening in step S4 in FIG. 1;
fig. 8 is a schematic flow chart illustrating an embodiment of a method for processing a circuit board after step S6 in fig. 1;
FIG. 9 is a schematic structural diagram of an embodiment corresponding to step S12 in FIG. 8;
FIG. 10 is a schematic structural diagram of an embodiment of a wiring board of the present application;
fig. 11 is an enlarged schematic view of the conductive block of fig. 10.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart of an embodiment of a method for processing a circuit board according to the present application. The processing method of the circuit board provided by the application comprises the following steps:
step S1: a through hole 16 is formed in the substrate 10, wherein the substrate 10 includes a first surface 12 and a second surface 14 opposite to each other, and the through hole 16 penetrates through the first surface 12 and the second surface 14.
Specifically, referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment corresponding to step S1 in fig. 1. The wiring board 1 includes a substrate 10. Specifically, the substrate 10 may be formed by stacking a plurality of layers of materials, for example, the base layer 10 includes a copper layer, an insulating layer, a copper layer, etc. stacked in sequence, and the first surface 12 and the second surface 14 may be outer surfaces of the copper layer. The number of the through holes 16 on the substrate 10 may be one or more, and the through holes 16 penetrate through the first surface 12 and the second surface 14, and may be formed by a mechanical drilling method. Of course, in other embodiments, the through hole 16 may be formed by laser drilling, etc., which is not limited in this application.
Step S2: the conductive layer 11 is formed on the first surface 12, the second surface 14, and the inner wall 18 of the through hole 16 of the substrate 10.
Specifically, referring to fig. 3, fig. 3 is a schematic structural diagram of an embodiment corresponding to step S2 in fig. 1. In this embodiment, the specific implementation process of step S2 may be: after the activation, glue removal and neutralization processes are sequentially performed on the whole of step S1, a copper layer is deposited on the first surface 12, the second surface 14 and the inner wall 18 of the through hole 16, where the copper layer is the conductive layer 11, so that the circuit board 1 achieves the effect of energizing.
Step S3: the first surface 12 and/or the second surface 14 of the substrate 10 are covered with a dry film 13.
Specifically, in an embodiment, please refer to fig. 4, where fig. 4 is a schematic structural diagram of an embodiment corresponding to step S3 in fig. 1. In the wiring board 1, a dry film 13 may be coated on the first surface 12 and the second surface 14 of the substrate 10. Of course, in other embodiments, the dry film 13 may be coated only on the first surface 12 of the substrate 10; or only the first surface 12 of the substrate 10 may be covered with the dry film 13. Among them, the dry film 13 may be a solvent-based dry film. Of course, the dry film 13 may be a water-soluble dry film, a dry developing or peeling dry film, or the like, and the present application does not limit the present invention.
After the step S3, the dry film 13 may be exposed to make the dry film 13 adhere to the conductive layer 11.
Step S4: a plurality of openings 15 are formed in the dry film 13 such that the conductive layer 11 is exposed at the positions of the openings 15.
Specifically, referring to fig. 5, fig. 5 is a schematic structural diagram of an embodiment corresponding to step S4 in fig. 1. In the wiring board 1, the vertical cross section of the opening 15 is an inverted trapezoid in a direction away from the substrate 10. The specific implementation of the above step S4 will be described in detail later.
Step S5: conductive bumps 17 are formed on the exposed conductive layer 11.
In an embodiment, please refer to fig. 6, where fig. 6 is a schematic structural diagram of an embodiment corresponding to step S5 in fig. 1. The conductive block 17 is formed by electroplating, and the electroplated material may be copper, or other materials, such as tin-lead alloy, gold, etc., which is not limited in the present application, and only needs to enable the circuit board 1 to form a loop to be conductive. The thickness of the material plated on the first surface 12 and the second surface 14 may or may not be the same as the thickness of the material plated on the inner wall 18 of the through hole 16. The thickness of the electroplated material can be set according to the requirements of users.
Step S6: the dry film 13 is removed.
Specifically, referring to fig. 6, in the present embodiment, the step S6 specifically includes: the dry film 13 is removed using a chemical reagent. In this embodiment, the chemical agent comprises sodium hydroxide. Of course, in other embodiments, the chemical agent may be other chemical agents, and it is only necessary to remove the dry film 13 without damaging the first surface 12 and the second surface 14.
The vertical sections of the openings 15 in the dry film 13 are designed to be inverted trapezoids, so that the line widths of the top layer and the bottom layer of the circuit board 1 are very close to each other, the processing technology of a high-precision circuit is facilitated, and the processing capacity of the precision circuit can reach 20 mu m/20 mu m (line width/line distance).
In one embodiment, with continuing reference to fig. 5, the step S4 specifically includes: a plurality of openings 15 are formed on the dry film 13 using a laser to expose the conductive layer 11. The dry film 13 is ablated by the laser method, so that the opening 15 is in an inverted trapezoid shape, and the surface of the opening 15 is free of residual glue, foreign matters and the like.
Further, with reference to fig. 5, the step of forming the plurality of openings 15 on the dry film 13 by using the laser includes: a plurality of openings 15 are formed on the dry film 13 corresponding to the positions of the through holes 16 and the dry film 13 not corresponding to the positions of the through holes 16 by using laser, so that the conductive layer 11 is exposed, and the surface has no adhesive residue, foreign matters and the like. This way, the conductive layer 11 in the subsequent through hole 16 can be in a closed circuit with the conductive layer 11 on the surface.
In addition, referring to fig. 7, fig. 7 is an enlarged schematic view of the opening in step S4 in fig. 1. The ratio of the area of the first opening 152 on the side of the opening 15 close to the substrate 10 to the area of the second opening 154 on the side far from the substrate 10 is in the range of 0.6:1 to 1:1, such as 0.6:1, 0.7:1, 0.8:1, 0.9:1, 1:1, etc. And the lengths of the short sides of the first opening 152 and the second opening 154 are the same, so the lengths of the long sides of the first opening 152 and the second opening 154 are close, and the top and bottom layer line widths of the circuit board 1 are very close. Specifically, in the present embodiment, the length of the opening 15 is equal to or less than 3 mils, e.g., 1mil, 2mil, 3mil, etc., in the direction parallel to the first surface 12; the length of the dry film 13 between adjacent openings 15 is less than or equal to 3 mils, e.g., 1mil, 2 mils, 3 mils, etc.
In addition, after the step S6, the circuit board 1 may be microetched to remove the conductive bumps 17 and/or the conductive layer 11 exposed from the protective film 19, specifically referring to fig. 8, where fig. 8 is a flowchart illustrating an embodiment of a processing method of the circuit board after the step S6 in fig. 1, and after the step S6, the method may further include:
step S11: a protective film 19 is covered at the location of the through-hole 16.
Specifically, please refer to fig. 9, fig. 9 is a schematic structural diagram of the circuit board after microetching according to the present application. A protective film 19 is applied at the location of the through-hole 16 to protect the plating material on the inner wall 18 of the through-hole 16. Alternatively, the protective film 19 may be a solvent-based dry film. Of course, in other embodiments, the protective film 19 may also be a water-soluble dry film, a dry developing or peeling dry film, etc., which is not limited in this application, and only needs to be able to protect the through hole 16 to prevent the plating material on the inner wall 18 of the through hole 16 in the circuit board 1 from being etched.
Step S12: the conductive bumps 17 and/or the conductive layer 11 exposed from the protective film 19 are microetched.
In one embodiment, with continued reference to fig. 9, the conductive bumps 17 exposed from the protective film 19 are microetched to remove the conductive bumps 17 outside the inner walls 18 of the through holes 16; or microetching the conductive layer 11 exposed from the protective film 19 to remove the conductive layer 11 except the inner wall 18 of the through hole 16; alternatively, the conductive pad 17 and the conductive layer 11 exposed from the protective film 19 may be microetched to remove the conductive pad 17 and the conductive layer 11 except for the inner wall 18 of the through hole 16. Wherein, the chemical reagent used for the micro-etching can be ferric chloride. Of course, in other embodiments, microetching may be performed using ammonium persulfate, sodium persulfate, or the like, but the present application is not limited thereto, and the conductive pad 17 and/or the conductive layer 11 exposed from the protective film 19 may be removed by microetching.
Step S13: the protective film 19 is removed.
Specifically, with continuing reference to fig. 9, in the present embodiment, the protective film 19 may be removed by using a chemical agent, the chemical agent includes sodium hydroxide, and in other embodiments, the chemical agent includes other chemical agents, which is not limited in this application, and only the protective film 19 may be removed without damaging other necessary portions. Of course, in other embodiments, the protective film 19 may be removed in other manners, which is not limited in this application, and the protective film 19 may be removed without damaging other necessary portions.
Referring to fig. 10, fig. 10 is a schematic structural diagram of an embodiment of the circuit board of the present application. The wiring board 2 may be formed by the processing method in the above embodiment, and mainly includes a base material 20, a conductive layer 28, and a plurality of conductive bumps 23.
Specifically, the substrate 20 may be formed by a plurality of material lamination, for example, the base layer 20 includes a copper layer, an insulating layer, a copper layer, etc. sequentially laminated, and the first surface 22 and the second surface 24 may be outer surfaces of the copper layer. The number of the through holes 26 on the substrate 20 may be one or more, and the through holes 26 penetrate through the first surface 22 and the second surface 24, which may be formed by a mechanical drilling method. Of course, in other embodiments, the through hole 26 may be formed by laser drilling, etc., which is not limited in this application. The conductive layer 28 covers the first surface 22, the second surface 24 and the inner wall 21 of the through hole 26. The conductive bumps 23 are spaced on the conductive layer 28, and the vertical cross-section of the conductive bumps 23 on the first surface 22 and/or the second surface 24 is inverted trapezoid in the direction away from the substrate 20.
Referring to fig. 10 and 11, fig. 11 is an enlarged view of the conductive block of fig. 10. In one embodiment, for the conductive block 23 with an inverted trapezoid shape, the ratio between the area of the third surface 25 on the side close to the substrate 20 and the area of the fourth surface 27 on the side far from the substrate 20 is in the range of 0.6:1-1:1, such as 0.6:1, 0.7:1, 0.8:1, 0.9:1, 1:1, and the like. And the lengths of the short sides of the third surface 25 and the fourth surface 27 are the same, so that the lengths of the long sides of the third surface 25 and the fourth surface 27 are close, and the top and bottom layer line widths of the wiring board 2 are very close.
In another embodiment, with continued reference to fig. 10, the length of the conductive block 23 is less than or equal to 3 mils, such as 1mil, 2mil, 3mil, etc., in a direction parallel to the first surface 22; the distance between adjacent conductive bumps 23 is equal to or less than 3 mils, e.g., 1mil, 2 mils, 3 mils, etc.
In the circuit board 2 provided in this embodiment, the vertical cross section of the conductive block 23 on the first surface 22 and/or the second surface 24 is designed to be an inverted trapezoid, and the area of the third surface 25 on the side of the conductive block 23 close to the substrate 20 is close to the area of the fourth surface 27 on the side of the conductive block away from the substrate 20, and the lengths of the short sides of the third surface 25 and the fourth surface 27 are the same, so that the lengths of the long sides of the third surface 25 and the fourth surface 27 are close, and the line widths of the top layer and the bottom layer of the circuit board 2 are very close, which is beneficial to the processing technology of high-precision circuits, and the processing capability of the precision circuits can reach 20 μm/20 μm (line width/line distance).
In summary, unlike the prior art, in the present application, a plurality of openings are formed by ablating a dry film corresponding to a through hole position and a dry film corresponding to a non-through hole position by using a laser, and the vertical cross section of the opening is an inverted trapezoid, so that a conductive block is formed on an exposed conductive layer, and therefore, the vertical cross section of the conductive block on a first surface and/or a second surface is also an inverted trapezoid, and the area of a third surface of the conductive block on a side close to a substrate is close to the area of a fourth surface of the conductive block on a side far from the substrate, so that the lengths of the long sides of the third surface and the fourth surface are close, and the top and bottom line widths of the circuit board are very close, which is beneficial to the processing of high-precision circuits, and the processing capacity of the precision circuits can reach 20 μm/20 μm (line width/line distance).
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A processing method of a circuit board is characterized by comprising the following steps:
forming a through hole on a substrate, wherein the substrate comprises a first surface and a second surface which are arranged oppositely, and the through hole penetrates through the first surface and the second surface;
forming a conductive layer on the first surface, the second surface and the inner wall of the through hole of the substrate;
covering the first surface and/or the second surface of the substrate with a dry film;
forming a plurality of openings on the dry film, wherein the conductive layer at the positions of the openings is exposed, and the vertical section of each opening is in an inverted trapezoid in the direction away from the substrate;
forming a conductive block on the exposed conductive layer;
and removing the dry film.
2. The process of claim 1 wherein the ratio of the area of the first opening on the side of the opening adjacent to the substrate to the area of the second opening on the side of the opening remote from the substrate is in the range of 0.6:1 to 1: 1.
3. The process of claim 1, wherein the openings have a length of 3 mils or less in a direction parallel to the first surface, and the dry film between adjacent openings has a length of 3 mils or less.
4. The process of claim 1, wherein said step of forming a plurality of openings in said dry film comprises:
forming a plurality of openings on the dry film using a laser.
5. The process of claim 4, wherein the step of forming a plurality of openings in the dry film using a laser comprises:
and forming a plurality of openings on the dry film corresponding to the through hole position and the dry film at the non-through hole position by utilizing laser.
6. The process of claim 1, wherein said step of removing said dry film comprises:
removing the dry film using a chemical agent, wherein the chemical agent comprises sodium hydroxide.
7. The process according to claim 1, characterized in that said step of removing said dry film is followed by:
covering a protective film at the position of the through hole;
microetching the conductive block and/or the conductive layer exposed from the protective film;
and removing the protective film.
8. A circuit board, comprising:
the substrate comprises a first surface and a second surface which are arranged oppositely, and a through hole is formed in the substrate and penetrates through the first surface and the second surface;
a conductive layer covering the first surface, the second surface, and an inner wall of the through-hole;
the conductive blocks are arranged on the conductive layer at intervals, and the vertical sections of the conductive blocks on the first surface and/or the second surface are in an inverted trapezoid shape in the direction away from the base material.
9. The wiring board of claim 8,
for the conductive block with the inverted trapezoid shape, the ratio of the area of the third surface on the side close to the base material to the area of the fourth surface on the side far from the base material ranges from 0.6:1 to 1: 1.
10. The circuit board of claim 8, wherein the conductive bumps have a length of 3 mils or less and a distance between adjacent conductive bumps of 3 mils or less in a direction parallel to the first surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011173689.XA CN114501801A (en) | 2020-10-28 | 2020-10-28 | Circuit board processing method and circuit board |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011173689.XA CN114501801A (en) | 2020-10-28 | 2020-10-28 | Circuit board processing method and circuit board |
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| CN114501801A true CN114501801A (en) | 2022-05-13 |
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| CN202011173689.XA Pending CN114501801A (en) | 2020-10-28 | 2020-10-28 | Circuit board processing method and circuit board |
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