JPS61140194A - Multilayer circuit board and manufacture thereof - Google Patents

Multilayer circuit board and manufacture thereof

Info

Publication number
JPS61140194A
JPS61140194A JP26251484A JP26251484A JPS61140194A JP S61140194 A JPS61140194 A JP S61140194A JP 26251484 A JP26251484 A JP 26251484A JP 26251484 A JP26251484 A JP 26251484A JP S61140194 A JPS61140194 A JP S61140194A
Authority
JP
Japan
Prior art keywords
copper
resin
reduced
hole
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26251484A
Other languages
Japanese (ja)
Inventor
鈴木 芳博
和嶋 元世
奈良原 俊和
嶋崎 威
古川 清則
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP26251484A priority Critical patent/JPS61140194A/en
Publication of JPS61140194A publication Critical patent/JPS61140194A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Laminated Bodies (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は多層回路板、特にレジンと銅配線とが高密着力
を有し、耐酸性が高く、且つ高精度の微細銅配線の形成
に好適な多層回路板およびその製造方法に関する。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides a multilayer circuit board, in particular, a multilayer circuit board in which resin and copper wiring have high adhesion, high acid resistance, and are suitable for forming fine copper wiring with high precision. The present invention relates to a multilayer circuit board and a method for manufacturing the same.

〔発明の背景〕[Background of the invention]

従来、レジンとそれに接する銅配線からなるプリント配
線板の製作に用いる鋼張板のレジンと銅箔との接着性を
高める方法としては、銅箔の表面を粗化し、この面を接
着面として用いることによ如、いわゆる投錨効果を利用
してレジンと銅箔との接着力を高める方法が用いられて
きた。しかじ銅箔の表面を単に機械的に粗化したのみで
は凹凸をかなシ大きくしない限)十分な接着力を得るこ
とは期待できないから、通常は鋼箔の表面をエツチング
によシ粗化し、この粗化面上に多孔質状の鋼酸化膜を形
成して、接着力を高める方法が採られている。
Conventionally, a method of increasing the adhesion between the resin and copper foil of a steel clad plate used to manufacture printed wiring boards consisting of resin and copper wiring in contact with it is to roughen the surface of the copper foil and use this surface as the adhesive surface. In particular, methods have been used to increase the adhesive strength between resin and copper foil by utilizing the so-called anchoring effect. However, if the surface of the copper foil is simply roughened mechanically, it cannot be expected to obtain sufficient adhesive strength (unless the irregularities are significantly increased), so usually the surface of the steel foil is roughened by etching. A method has been adopted in which a porous steel oxide film is formed on this roughened surface to increase adhesive strength.

ところで、多層プリント配線板を製造するプロセスでは
、(1)ドリルによる機械的なスルーホール形成、(2
)スルーホール内の導通を得るのに必要な化学鋼めっき
のための酸性触媒液への浸漬などの工程がある。このた
め、多層プリント配線板の製作に用いられる鋼張板とし
ては、レジンに対する鋼箔の密着性が高いこと、および
耐酸性がすぐれていることが要求される。
By the way, in the process of manufacturing multilayer printed wiring boards, (1) mechanical through-hole formation using a drill, (2)
) There are steps such as immersion in acidic catalyst liquid for chemical steel plating that are necessary to obtain continuity in the through-hole. For this reason, steel clad plates used in the production of multilayer printed wiring boards are required to have high adhesion of the steel foil to the resin and excellent acid resistance.

しかるに、接着性を高めるために、鋼箔表面を機械的も
しくは電気化学的に粗化し、さらにその上に多孔質の酸
化膜を形成する前記従来の方法では、鋼箔表面に酸化膜
を形成している以上、得られた多層配線板のスルーホー
ルと接する部分の酸化膜の耐酸性は極めて乏しいもので
あし、逆に、耐酸性を上げようとして酸化膜の厚さを薄
くすると接着性は低下するという問題がある。
However, in the conventional method described above, in which the surface of the steel foil is mechanically or electrochemically roughened and a porous oxide film is formed thereon in order to improve adhesion, the oxide film is not formed on the surface of the steel foil. Therefore, the acid resistance of the oxide film in contact with the through-holes of the obtained multilayer wiring board is extremely poor.Conversely, if the thickness of the oxide film is thinned in an attempt to increase the acid resistance, the adhesion will decrease. There is a problem with doing so.

さらに、従来の銅張板はレゾ/と鋼箔との接着性を高め
るため、銅箔の表面は粗化された状態(10〜20μm
)になっている。このため、銅張板上にエツチングによ
シ、銅配線を形成しようとすると、鋼箔面がレジン界面
に複雑に入組んだ状態になっているため、これらの非回
路部の銅を完全に除去することが困難である。もちろん
エツチングを十分に実施すれば非回路部の鋼を完全に除
去することは可能であるが、しかし、それに伴い回路部
の銅配線の/4ターン精度が低下するという問題が生ず
る。この問題は薄い鋼箔の上にレジストパターンを形成
し、回路部上のみに更に銅を厚つけ形成するという、い
わゆる1ノーターンめっき法“においても、レゾストを
除去した後に非回路部の銅をエツチングによシ除去する
際、問題となる。
Furthermore, in order to improve the adhesion between the conventional copper clad plate and the steel foil, the surface of the copper foil is roughened (10 to 20 μm).
)It has become. For this reason, when attempting to form copper wiring on a copper clad plate by etching, the steel foil surface is intricately intertwined with the resin interface, so it is necessary to completely remove the copper in these non-circuit areas. Difficult to remove. Of course, if etching is carried out sufficiently, it is possible to completely remove the steel in non-circuit areas, but this causes a problem in that the quarter-turn accuracy of the copper wiring in the circuit areas is reduced. This problem also occurs in the so-called one-no-turn plating method, in which a resist pattern is formed on a thin steel foil and a thick layer of copper is further deposited only on the circuit area, but after the resist is removed, the copper in the non-circuit area is etched. It becomes a problem when removing it.

機械的に粗化した銅箔の面に直接レジンを接着する方法
で銅−レジン複合板を作れば、酸化膜の介在がないので
耐酸性上の問題はないとしても、十分な接着力を得るた
めにはよ)大きい凹凸を要するので、上記の銅配線の/
母ターン精度の問題はよシ顕著となる。また、鋼箔の表
面の凹凸を大きくすることは、薄い鋼箔を絶縁基板上に
接着させることも極めて困難にする。
If a copper-resin composite board is made by bonding resin directly to the surface of mechanically roughened copper foil, sufficient adhesion strength can be obtained even though there is no problem with acid resistance since there is no intervening oxide film. For this purpose, large unevenness is required, so the above copper wiring /
The problem of mother turn accuracy becomes even more noticeable. Furthermore, increasing the irregularities on the surface of the steel foil also makes it extremely difficult to adhere the thin steel foil onto an insulating substrate.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、銅配線とレジンとの密着力が高く、ス
ルーホール形成においても耐酸性が良好で、しかも銅配
線パターンの精、度の高い多層回路板およびその製造法
を提供するにある。
An object of the present invention is to provide a multilayer circuit board that has high adhesion between copper wiring and resin, has good acid resistance even when forming through holes, and has a high precision copper wiring pattern, and a method for manufacturing the same. .

〔発明の概要〕[Summary of the invention]

本発明の多層回路板は、レジンとそれに接する銅配線と
の積層体よシなシ、少くともスルーホールと交叉するレ
ジンと銅との接着界面が、JISB0601に記載され
た十点平均粗さにおいて100μmの規準長さLに対し
Rzが0.1μm以上6μm以下の凹凸をなす酸化後還
元された銅の面よりなることを特徴とする。
The multilayer circuit board of the present invention is a laminate of resin and copper wiring in contact with it, and at least the adhesive interface between the resin and copper that intersects with the through hole has a ten-point average roughness specified in JISB0601. It is characterized by being made of an oxidized and reduced copper surface having an unevenness Rz of 0.1 μm or more and 6 μm or less with respect to a standard length L of 100 μm.

本発明の多層回路板の製造方法は、薄い鋼箔の片面を酸
化後に還元してJIS110601に記載された十点平
均粗さにおいて100μmの規準長さLに対しR8が0
.1μm以上6μm以下の凹凸を持つ還元銅の面となし
た後に、液面にレジン層を接着し、その後、該鋼箔の他
面を酸化後還元して上記と同程度の凹凸を持つ還元銅の
面となした後に、該他面に配線−4声−ンに従って鋼の
回路を厚づけし、その後、該鋼の回路の表面を酸化後還
元して前記と同程度の凹凸を持つ還元鼾の面となした後
、前記レジ7層上の非回路部の鋼箔をエツチングによシ
除去し、その後、上記鋼の回路のうち少くとも後記スル
ーホール形成部の厚さ方向と垂直な表面は上記還元銅の
状態を保ったまま、少くとも以上の過程を経たレジン板
の複数枚をレジンシリプレグを介して積層接着し、この
積層物の所定部分にスルーホールを形成し、該スルーホ
ール内面に銅をメッキすることを特徴とする。
The method for manufacturing a multilayer circuit board of the present invention is to oxidize and then reduce one side of a thin steel foil so that R8 is 0 for a standard length L of 100 μm in the ten-point average roughness described in JIS110601.
.. After forming a reduced copper surface with unevenness of 1 μm or more and 6 μm or less, a resin layer is adhered to the liquid surface, and then the other side of the steel foil is oxidized and reduced to form a reduced copper surface with unevenness of the same degree as above. After forming the surface, a steel circuit is thickened on the other surface according to the wiring pattern, and then the surface of the steel circuit is oxidized and reduced to form a reduced surface having the same degree of unevenness as above. After that, the steel foil in the non-circuit part on the seventh register layer is removed by etching, and then the surface perpendicular to the thickness direction of at least the through-hole forming part of the above-mentioned steel circuit is etched. While maintaining the state of the reduced copper, multiple sheets of resin plates that have gone through at least the above process are laminated and bonded via a resin preg, a through hole is formed in a predetermined part of this laminate, and a through hole is formed on the inner surface of the through hole. Characterized by plating copper.

本発明者らは、銅の表面を酸化した後に鋼酸化膜の表面
の粗さと同程度に還元することによって、該表面を上記
に特定した表面粗さを持つ凹凸状になし得ること、而し
て、かかる凹凸を有する還元銅表面をレジンとの接着界
面とすることによって銅とレジンとの接着力が従来の酸
化膜を介する接着の場合と匹適する高強度のものになる
こと、このような還元銅は酸化膜に比べて酸に極めて溶
解し難いものであることを見出した。しかも、この還元
銅面の凹凸は上記のように微細であって、レジン層上の
銅配線の形成精度に支障を与えないこともわかった。本
発明はこのような知見に基づいてなされたものである〇 本発明の実施態様には、スルーホールと接しないレジン
と銅との接着界面に鋼酸化膜が介在する実施態様(例え
ば後述の実施例1,2)も含まれるが、その場合でも、
酸性液に曝されるスルーホールと交る銅−レジン界面は
還元銅であシ酸化膜が介在していないから、耐酸性が損
われることはない。
The present inventors have discovered that by oxidizing the copper surface and then reducing it to the same degree as the surface roughness of the steel oxide film, the surface can be made into an uneven shape having the surface roughness specified above. Therefore, by using the reduced copper surface with such irregularities as the adhesive interface with the resin, the adhesive force between the copper and the resin becomes high strength comparable to that of conventional adhesives through oxide films. It has been found that reduced copper is extremely difficult to dissolve in acids compared to oxide films. Furthermore, it has been found that the irregularities on the reduced copper surface are minute as described above and do not interfere with the accuracy of forming copper wiring on the resin layer. The present invention has been made based on such findings. Embodiments of the present invention include embodiments in which a steel oxide film is interposed at the adhesive interface between the resin and copper that does not contact the through hole (for example, the embodiment described below). Examples 1 and 2) are also included, but even in that case,
Since the copper-resin interface that intersects with the through-hole exposed to the acidic liquid is reduced copper and has no oxidized film interposed therebetween, acid resistance is not impaired.

なお、本発明の実際の実施において、レジンとの接着前
に、空気に曝される等の原因で還元銅の面に不可避的に
微量の酸化物が生じ得るが、このような不可避的な微量
酸化物はレジンと銅との接着力に悪影響を及ぼすもので
はなく、また耐酸性に悪影響を及ぼすものでもない・ 〔発明の実施例〕 実施例1 第1図において、表面の凹凸がJISB0601に記載
される十点平均あらさにおいて、規準長さLが100μ
mにおけるRzが61tnよシも小さいステンレス板1
をめっき下地用の基板として用い、この上にめっきによ
、り@2を4μmの厚さにめっきする(&)。次に、こ
のめっき膜をエツチングによシ、1〜1.5μmの凹凸
になるように#i2の表面を粗化する(b)。粗化され
た銅表面上に銅の酸化、[3を形成する(e)。この酸
化膜の形成は、液組成がNILO■4I/!、NasP
O< ・2H201211/7、NaCtOz 30 
F/Aであるような液に、液温70℃の条件で、1分間
浸漬する方法によりて行なう。次に、この酸化膜をアル
カリ性の液中で電気的に還元する(d)。この電解還元
は、NaOH41/lk水溶液(pH12)中で、対極
にステンレス板を用いて0.2 A/dm2で実施する
。次に、この還元膜4を!リグレグ5側に向けて加熱、
加圧によジグリグレグ5と接着し、ステンレス板1をは
がす(・)。次に、#t2の外表面がエツチングによ)
1〜1.5μmの凹凸になるように粗化する(f)。粗
化された鋼の外表面上に酸化膜3を形成する(g)。こ
の形成方法は(e)と同じ方法による。
In the actual implementation of the present invention, a trace amount of oxide may inevitably be generated on the surface of the reduced copper due to exposure to air or other causes before bonding with the resin; The oxide does not have a negative effect on the adhesion between the resin and the copper, nor does it have a negative effect on the acid resistance. [Embodiments of the Invention] Example 1 In Figure 1, the surface irregularities are as described in JISB0601. For the ten-point average roughness, the standard length L is 100μ
Stainless steel plate 1 whose Rz at m is smaller than 61tn
was used as a substrate for plating, and R@2 was plated on this to a thickness of 4 μm (&). Next, this plating film is etched to roughen the surface of #i2 so that it has irregularities of 1 to 1.5 μm (b). Copper oxidation forms [3] on the roughened copper surface (e). This oxide film is formed when the liquid composition is NILO■4I/! , NasP
O< ・2H201211/7, NaCtOz 30
This is carried out by immersing the specimen in a liquid such as F/A at a temperature of 70° C. for 1 minute. Next, this oxide film is electrically reduced in an alkaline solution (d). This electrolytic reduction is carried out in a NaOH41/lk aqueous solution (pH 12) at 0.2 A/dm2 using a stainless steel plate as a counter electrode. Next, this reduced film 4! Heat toward the reg 5 side,
It adheres to the jig leg 5 by applying pressure, and then peels off the stainless steel plate 1 (・). Next, the outer surface of #t2 is etched)
It is roughened to have an unevenness of 1 to 1.5 μm (f). An oxide film 3 is formed on the roughened outer surface of the steel (g). This formation method is the same as that in (e).

次に、この酸化膜3をアルカリ性の液中で電気的に還元
する(h)。この還元は(d)と同じ条件で実施する。
Next, this oxide film 3 is electrically reduced in an alkaline solution (h). This reduction is carried out under the same conditions as in (d).

以上によシ、各銅2の表面および裏面は酸化後に還元さ
れた銅還光膜4となる。次に、還元した膜4上にレノス
ト/4ター76を形成する(1)。次に、めっきによシ
、回路部に相当する部分に!i7を厚づけする(j)。
As described above, the front and back surfaces of each copper 2 become a reduced copper return film 4 after oxidation. Next, a renost/quater 76 is formed on the reduced film 4 (1). Next, plating the part corresponding to the circuit part! Thicken i7 (j).

次に、レノストロをはく離する(k)。次に、露出部の
鋼の表面(側面も含め)に酸化膜3を形成する(4゜こ
の形成方法は(c)と同じ方法による。次に、この酸化
膜をアルカリ性の液中で電気的に還元して還元膜4とす
るー。この還元は(d)と同じ条件で実施する。次に、
基板の厚さ方向に対して垂直な銅配線の平面部にレジン
)パターン8を形成する(11)。次に、エツチングに
よシ、非回路部の鋼を除去する(0)。次に、露出部の
鋼表面(側面)上に酸化膜3を形成する(p)。この形
成方法は(c)と同じ方法による。この後、ととべ還元
膜を形成することは、電気的導通が得られないため不可
能である。しかし、酸化膜と還元膜は基本的には密着力
はほぼ同程度であシ、また、この側面では耐塩酸性は要
求されていないので問題はない。次に、レゾスト8をは
く離する(q)。次に、これらの基板の複数枚をプリプ
レグ5′によシ、積層接着する(r)。但しこのとき本
例では最外層は銅箔面のままのものとする。次に、ドリ
ルにより、スルーホールHを形成する(8)。次に、ス
ルーホールHの側面に触媒を付与した後、該スルーホー
ル側面および最外層に化学鋼めっき膜9を薄づけ形成し
、最外層にレゾストパターン10を形成する(1)。
Next, peel off the lenostro (k). Next, an oxide film 3 is formed on the exposed steel surface (including the side surfaces) (4° This formation method is the same as in (c). Next, this oxide film is electrically heated in an alkaline solution. to form a reduced film 4.This reduction is carried out under the same conditions as in (d).Next,
A resin pattern 8 is formed on a flat surface of the copper wiring perpendicular to the thickness direction of the substrate (11). Next, the steel in the non-circuit portion is removed by etching (0). Next, an oxide film 3 is formed on the exposed steel surface (side surface) (p). This formation method is the same as in (c). After this, it is impossible to form a totobe reduction film because electrical continuity cannot be obtained. However, the oxide film and the reduced film basically have approximately the same adhesion strength, and in this aspect, hydrochloric acid resistance is not required, so there is no problem. Next, the resist 8 is peeled off (q). Next, a plurality of these substrates are laminated and bonded to prepreg 5' (r). However, in this example, the outermost layer is left as a copper foil surface. Next, a through hole H is formed using a drill (8). Next, after applying a catalyst to the side surface of the through hole H, a thin chemical steel plating film 9 is formed on the side surface of the through hole and the outermost layer, and a resist pattern 10 is formed on the outermost layer (1).

次に、回路部に電気#i11を厚づけめっきし、レジン
)10をはく離した後、エツチングによシ回路を形成す
′る(ul)。
Next, the circuit portion is plated with a thick layer of electrical #i11, and after the resin 10 is peeled off, a circuit is formed by etching (ul).

以上のプロセスによシ作成した多層板(第1図(−”)
)は、上記(1)における化学鋼めっきの前処理工程で
の触媒付与の際にもスルーホール()I)に接するレジ
ンと銅との界面への塩酸による浸み込みはなく、耐塩酸
性は良好であった。また、酸化膜および還元膜の表面粗
さはいずれもJI8B0601に記載される十点平均あ
らさにおいて規準長さLが100μmにおいてRzが3
.5μmでちゃ、レジンと還元銅との接着力も1.2 
KqA−IL  であシ、良好であったO 実施例2 第2図に示すように、実施例1の工程(n)において、
基板に対して平行な銅配線のパッド部(スルーホールを
穿孔する銅配線広幅部)に相当する平面部(第2図P部
)のみレゾストでマスクしくn′)、それ以外は実施例
1と同様な条件で行なった。以上のプロセスによシ作成
した多層板(第2図(u2))はスルーホール側面の化
学鋼めっきの前処理工程における触媒付与の際にもスル
ーホールに接するレジンと銅との界面への塩酸による浸
み込みはなく、耐塩酸性は良好であった。また、酸化膜
および還元膜の表面粗さは実施例1で示した膜の粗さと
いずれも同じであった。レジンと銅との接着性も1.2
 K4/cmであシ、良好であった。
Multilayer board made by the above process (Fig. 1 (-”)
) has no hydrochloric acid penetration into the interface between the resin and copper that is in contact with the through-hole (I) even when applying a catalyst in the pretreatment process for chemical steel plating in (1) above, and the hydrochloric acid resistance is low. It was good. In addition, the surface roughness of both the oxide film and the reduced film is determined by the standard length L of 100 μm and Rz of 3 in the ten-point average roughness described in JI8B0601.
.. At 5 μm, the adhesive strength between the resin and reduced copper is also 1.2.
KqA-IL was good. Example 2 As shown in FIG. 2, in step (n) of Example 1,
Only the plane part (part P in Fig. 2) corresponding to the pad part of the copper wiring parallel to the substrate (the wide part of the copper wiring for drilling through holes) was masked with resist (n'), and the rest was the same as in Example 1. It was conducted under similar conditions. The multilayer board (Fig. 2 (u2)) created by the above process was prepared by applying hydrochloric acid to the interface between the resin and copper that is in contact with the through hole during the application of catalyst in the pretreatment process for chemical steel plating on the side surface of the through hole. There was no seepage due to water, and the hydrochloric acid resistance was good. Furthermore, the surface roughness of the oxide film and the reduced film was the same as that of the film shown in Example 1. Adhesion between resin and copper is also 1.2
K4/cm was good.

実施例3 第3図に示すように、実施例1の工程(o)完了後、レ
ゾスト8を除去し、工程(p) 、 (q)を経ずに、
積層接着し、ノ々ッド部にスルーホールを形成した後、
化学鋼めっきをするための触媒を付与し1最外層にレゾ
スト/4ターンを形成し、その後、化学鋼めっき膜をス
ルーホールおよび最外層の回路部に厚づけ形成し、その
後、レゾストをはく離し、非回路部の銅が除去されるま
で工、チングし、回路を形成した(u3)。以上のプロ
セスによシ作成した多層板(第3図(、’) )は、還
元膜の表面粗さは実施例1で示した膜の粗さと同じであ
った。またレジンと還元銅との接着性も1.2(伽であ
シ、良好であった。また、スルーホール側面への化学鋼
めっきの前処理工程における触媒付与の際にもスルーホ
ールに接するレジンと銅との界面への塩酸による浸み込
みはなく、耐塩酸性は良好であった。
Example 3 As shown in FIG. 3, after completing step (o) of Example 1, the resist 8 was removed, and without going through steps (p) and (q),
After laminating and bonding and forming through holes in the nodal parts,
A catalyst for chemical steel plating is applied and a resist/4 turn is formed on the outermost layer, and then a thick chemical steel plating film is formed on the through holes and the circuit part of the outermost layer, and then the resist is peeled off. Then, a circuit was formed by etching and etching until the copper in the non-circuit area was removed (u3). The surface roughness of the reduced film in the multilayer board (Fig. 3(,')) produced by the above process was the same as that of the film shown in Example 1. In addition, the adhesion between the resin and reduced copper was good (1.2).Also, when applying a catalyst in the pretreatment process for chemical steel plating to the side of the through hole, the adhesiveness of the resin in contact with the through hole was also good. Hydrochloric acid did not seep into the interface between copper and copper, and the hydrochloric acid resistance was good.

この実施例では、回路鋼の側面部は微細な凹凸状になっ
ていないため樹脂との密着力が弱いが、その平面部と樹
脂との密着力は十分である。しかし、高密度配線では、
側面部と樹脂との接着面積が平面部における接着面積に
対して無視できなくなるため、側面部にも微細な凹凸を
設けたのが実施例1である。
In this example, since the side surface of the circuit steel does not have minute irregularities, its adhesion to the resin is weak, but the adhesion between its flat surface and the resin is sufficient. However, in high-density wiring,
In Example 1, fine irregularities were also provided on the side surface because the bonding area between the side surface and the resin could not be ignored compared to the bonding area on the flat surface.

実施例4 第4図に示すように、実施例1の工程(0)において、
基板に対して、平行な銅配線の・々、ド部(スルーホー
ルを穿孔する銅配線広幅部)に相当する平面部(第4図
P部)にのみレジストでマスクしく第4図(O′))、
それ以外は実施例1と同様な条件で行なった。以上のプ
ロセスによシ、作成した多層板(第4図(、’))はス
ルーホール側面の化学鋼めっきの前処理工程における触
媒付与の際にもスルーホールに接するレジンと銅との界
面への塩酸による浸み込みはなく、耐塩酸性は良好であ
った。
Example 4 As shown in FIG. 4, in step (0) of Example 1,
4 (O' )),
The other conditions were the same as in Example 1. Through the above process, the multilayer board created (Fig. 4 (,')) is also applied to the interface between the resin and copper that is in contact with the through-hole during the application of catalyst in the pre-treatment process for chemical steel plating on the side of the through-hole. There was no penetration by hydrochloric acid, and the hydrochloric acid resistance was good.

また、酸化膜および還元膜の表面粗さは実施例1で示し
た膜の粗さといずれも同じであった。また、レジンと還
元銅との接着性も1.2 Kf/anであシ、良好であ
った・ 実施例5 第5図に示すように、実施例1において(e)までの工
程を経た後、(f) 、 (g) + (hJの工程を
経ずに、レゾスト/4ターンを形成して、以下化学めっ
きによシ、回路部に鋼を厚づけ形成し、レジストをはく
離した後、(粉取下の工程に従って、多層板を形成した
。以上のプロセスによシ作成した多層板(第5図(U)
)は、還元膜の表面粗さは実施例1で示した膜の粗さと
同じであった。またレジンと還元銅との接着力は1.2
 Kf/cmであシ、良好であった。また、スルーホー
ル側面への化学鋼めっきの前処理工程における触媒付与
の際にも、スルーホールに接するレジンと銅との界面へ
の塩酸による浸み込みはなく、耐塩酸性は良好であった
Furthermore, the surface roughness of the oxide film and the reduced film was the same as that of the film shown in Example 1. In addition, the adhesion between the resin and reduced copper was 1.2 Kf/an, which was good.Example 5 As shown in Figure 5, after going through the steps up to (e) in Example 1, , (f), (g) + (After forming a resist/4 turn without going through the hJ process, and then using chemical plating to thicken the steel on the circuit part and peeling off the resist, (A multilayer board was formed according to the powder removal process. The multilayer board created by the above process (Fig. 5 (U)
), the surface roughness of the reduced film was the same as that of the film shown in Example 1. Also, the adhesive strength between resin and reduced copper is 1.2
Kf/cm was good. Furthermore, even when a catalyst was applied to the side surface of the through hole in the pretreatment process for chemical steel plating, hydrochloric acid did not seep into the interface between the resin and copper that was in contact with the through hole, and the hydrochloric acid resistance was good.

比較例 第6図において、表面の凹凸がJISB0601に記載
される十点平均あらさにおいて、規準長さLが100μ
mにおけるRzが6μmよシも小さいステンレス板1を
めっき下地用の基板として用い、この上にめっきによシ
銅2を4μmの厚さにめっきする(&)。次にこのめり
き膜2をエツチングによシ1〜1.5μmの凹凸になる
ように銅表面を粗化する(b)。粗化された銅表間上に
酸化膜3を形成する(c)。
In Comparative Example Fig. 6, the standard length L is 100 μm when the surface unevenness is the ten-point average roughness described in JISB0601.
A stainless steel plate 1 whose Rz at m is as small as 6 μm is used as a substrate for plating, and copper 2 is plated on this plate to a thickness of 4 μm (&). Next, the plated film 2 is etched to roughen the copper surface so that it has irregularities of 1 to 1.5 μm (b). An oxide film 3 is formed on the roughened copper surface (c).

次に酸化膜3をプリプレグ5側に向けて加熱、加圧によ
)接着し、ステンレス板工をはがす(d)。次に、銅2
の外表面が1〜1.5μmの凹凸になるようにエッチン
グにより粗化する(e)。粗化された!!i2の外表面
上に酸化膜3を形成する(f)。次に、この酸化膜3上
にレゾスト/ぐター76を形成スる(SC)O次に、化
学めっきによシ回路部に相当する部分に銅7を厚づけす
る(h)。次に、レゾストロをはく離する(1)。次に
、エツチングによシ、非回路部の銅を除去する(J)。
Next, the oxide film 3 is attached to the prepreg 5 side (by heating and pressurizing), and the stainless steel plate is peeled off (d). Next, copper 2
The outer surface is roughened by etching so that it has an unevenness of 1 to 1.5 μm (e). Roughened! ! An oxide film 3 is formed on the outer surface of i2 (f). Next, a resist/gutter 76 is formed on this oxide film 3 (SC).Next, a thick layer of copper 7 is applied to a portion corresponding to the circuit portion by chemical plating (h). Next, peel off the resostro (1). Next, copper in non-circuit areas is removed by etching (J).

次に、露出部の鋼表面上に酸化膜3を形成する(幻。次
に、これらの基板の複数枚をプリプレグ5′によシ積層
接着する<1)。次にドリルによシスルーホールHを形
成する(ホ)。次に、スルーホールHの側面に触媒を付
与した後、スルーホール側面および最外層に化学銅めり
き膜を扉付は形成し、最外層にレゾストハターン10を
形成する(n)。次に、回路部に#111を厚づけめっ
きし、レノストをはく離した後、工、チングにょシ回路
を形成する(o)。
Next, an oxide film 3 is formed on the exposed steel surface (illustration).Next, a plurality of these substrates are laminated and bonded to the prepreg 5'(<1). Next, use a drill to form a through hole H (e). Next, after applying a catalyst to the side surface of the through hole H, a chemical copper plating film is formed on the side surface of the through hole and the outermost layer, and a resist pattern 10 is formed on the outermost layer (n). Next, the circuit part is plated with #111 thickly, and after peeling off the coating, a circuit is formed (o).

以上のプロセスによシ作成した多層板は、レジンと銅と
の接着力は1.3隔伽であシ、良好であるが、上記化学
めっきの前処理工程における触媒付与の際に、スルーホ
ールに接するレジンと銅との界習への塩酸による浸み込
みが生じ、耐塩酸性は不良であった。
The multilayer board made by the above process has good adhesion between the resin and copper, which is 1.3 degrees, but when applying catalyst in the pretreatment process for chemical plating, the through-hole Hydrochloric acid seeped into the contact between the resin and copper, and the hydrochloric acid resistance was poor.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、し2ンとの密着力の高い微細な銅配線
が絶縁基板上に精度よく形成された、かつ耐塩酸性にす
ぐれた多層回路板を得ることができる0
According to the present invention, it is possible to obtain a multilayer circuit board in which fine copper wiring with high adhesion to insulation substrates is precisely formed on an insulating substrate and has excellent hydrochloric acid resistance.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)ないしくul)、第2図(n’) (,2
) 、第3図(、) (u3)、第4図(o’)(u’
)および第5図(e) (u5)は本発明による多層回
路板形成プロセスの異る実スによる多層回路板形成プロ
セスの概略図である。 符号の説明 1・・・ステンレス基板 2・・・銅箔3・・・酸化膜
     4・・・還元膜5・・・し・クン     
6・・・レゾストア・・・厚づけ銅膜   8・・・レ
ジスト9・・・薄づけ化学銅めっき膜 5′・・・プリプレグ。 第1図 第1図 第1図 第2図 区 r4ゝ 寸  3          ミ 渋 第5図 第6図 第6図 第 6 図 り 第6図 手続補正書(カベ) 昭和lo年斗月−駈日
Figure 1 (a) or ul), Figure 2 (n') (,2
), Figure 3 (,) (u3), Figure 4 (o') (u'
) and FIG. 5(e) (u5) are schematic diagrams of the multilayer circuit board forming process according to different embodiments of the multilayer circuit board forming process according to the present invention. Explanation of symbols 1...Stainless steel substrate 2...Copper foil 3...Oxide film 4...Reduced film 5...Shi-kun
6... Resostore... Thick copper film 8... Resist 9... Thin chemical copper plating film 5'... Prepreg. Fig. 1 Fig. 1 Fig. 1 Fig. 2 Section r4ゝ dimension 3 Mi Shibu Fig. 5 Fig. 6 Fig. 6 Fig. 6 Diagram Fig. 6 Procedural amendment (wall) Showa LO year month - date

Claims (1)

【特許請求の範囲】 1、レジンとそれに接する銅配線との積層体よりなる多
層回路板において、少くともスルーホールと交叉するレ
ジンと銅との接着界面が、JISB0601に記載され
た十点平均粗さにおいて100μmの規準長さLに対し
R_zが0.1μm以上6μm以下の凹凸をなす酸化後
還元された銅の面よりなることを特徴とする多層回路板
。 2、薄い銅箔の片面を酸化後に還元してJISB060
1に記載された十点平均粗さにおいて100μmの規準
長さLに対しR_zが0.1μm以上6μm以下の凹凸
を持つ還元銅の面となした後に、該面にレジン層を接着
し、その後、該銅箔の他面を酸化後還元して上記と同程
度の凹凸を持つ還元銅の面となした後に、該他面に配線
パターンに従って銅の回路を厚づけし、その後、該銅の
回路の表面を酸化後還元して前記と同程度の凹凸を持つ
還元銅の面となした後、前記レジン層上の非回路部の銅
箔をエッチングにより除去し、その後、上記銅の回路の
うち少くとも後記スルーホール形成部の厚さ方向と垂直
な表面は上記還元銅の状態を保ったまま、少くとも以上
の過程を経たレジン板の複数枚をレジンプリプレグを介
して積層接着し、この積層物の所定部分にスルーホール
を形成し、該スルーホール内面に銅をメッキすることを
特徴とする多層回路板の製造方法。
[Claims] 1. In a multilayer circuit board made of a laminate of resin and copper wiring in contact with it, at least the bonding interface between the resin and the copper that intersects with the through hole has a ten-point average roughness specified in JISB0601. A multilayer circuit board comprising a surface of oxidized and reduced copper having an unevenness R_z of 0.1 μm or more and 6 μm or less with respect to a standard length L of 100 μm. 2. One side of thin copper foil is oxidized and reduced to JISB060.
After forming a reduced copper surface with unevenness of R_z of 0.1 μm or more and 6 μm or less with respect to the standard length L of 100 μm in the ten-point average roughness described in 1, a resin layer is adhered to the surface, and then After oxidizing and reducing the other side of the copper foil to form a reduced copper surface with the same level of unevenness as above, a copper circuit is thickened on the other side according to the wiring pattern, and then the copper circuit is thickened according to the wiring pattern. After the surface of the circuit is oxidized and reduced to form a reduced copper surface with the same level of unevenness as above, the copper foil in the non-circuit area on the resin layer is removed by etching, and then the copper circuit is removed. At least the surface perpendicular to the thickness direction of the through-hole forming part described later is kept in the above-mentioned reduced copper state, and a plurality of resin plates that have gone through at least the above process are laminated and bonded via a resin prepreg. A method for manufacturing a multilayer circuit board, comprising forming a through hole in a predetermined portion of a laminate, and plating the inner surface of the through hole with copper.
JP26251484A 1984-12-12 1984-12-12 Multilayer circuit board and manufacture thereof Pending JPS61140194A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26251484A JPS61140194A (en) 1984-12-12 1984-12-12 Multilayer circuit board and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26251484A JPS61140194A (en) 1984-12-12 1984-12-12 Multilayer circuit board and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS61140194A true JPS61140194A (en) 1986-06-27

Family

ID=17376855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26251484A Pending JPS61140194A (en) 1984-12-12 1984-12-12 Multilayer circuit board and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS61140194A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02306695A (en) * 1989-05-22 1990-12-20 Matsushita Electric Works Ltd Multilayer interconnection substrate
JPH03288493A (en) * 1990-04-05 1991-12-18 Sumitomo Bakelite Co Ltd Multilayer printed wiring board
JPH06350253A (en) * 1993-06-11 1994-12-22 Nec Corp Production of multilayer printed wiring board
JP2001326467A (en) * 2000-05-16 2001-11-22 Mitsui Mining & Smelting Co Ltd Method for manufacturing printed wiring board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02306695A (en) * 1989-05-22 1990-12-20 Matsushita Electric Works Ltd Multilayer interconnection substrate
JPH03288493A (en) * 1990-04-05 1991-12-18 Sumitomo Bakelite Co Ltd Multilayer printed wiring board
JPH06350253A (en) * 1993-06-11 1994-12-22 Nec Corp Production of multilayer printed wiring board
JP2001326467A (en) * 2000-05-16 2001-11-22 Mitsui Mining & Smelting Co Ltd Method for manufacturing printed wiring board
WO2001089276A1 (en) * 2000-05-16 2001-11-22 Mitsui Mining & Smelting Co., Ltd. Method for manufacturing printed wiring board

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