JPS60263494A - Method of producing recording electrode plate - Google Patents

Method of producing recording electrode plate

Info

Publication number
JPS60263494A
JPS60263494A JP12020384A JP12020384A JPS60263494A JP S60263494 A JPS60263494 A JP S60263494A JP 12020384 A JP12020384 A JP 12020384A JP 12020384 A JP12020384 A JP 12020384A JP S60263494 A JPS60263494 A JP S60263494A
Authority
JP
Japan
Prior art keywords
plating
copper
resist
etching
recording electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12020384A
Other languages
Japanese (ja)
Inventor
順雄 岩崎
直樹 福富
木田 明成
富士男 小島
川島 豊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP12020384A priority Critical patent/JPS60263494A/en
Publication of JPS60263494A publication Critical patent/JPS60263494A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、ファクシミリ、プリンター、グロツター等の
記録部に於て、静電記録、通電感熱記録、放電破壊記録
等の方式で記録する場合に使用される記録電極板の製造
法に関するものである。
Detailed Description of the Invention (Industrial Field of Application) The present invention is applicable to recording units of facsimiles, printers, grotteurs, etc., using methods such as electrostatic recording, current thermal recording, and discharge destruction recording. The present invention relates to a method of manufacturing the recording electrode plate used.

この記録電極板は、基板端部に導体が多数一定間隔で平
行に配列されて電極部か構成されており(通常の導体密
度8〜12本/mm)、導体の他端は、駆動回路に接続
して使用されるものである。
This recording electrode plate has an electrode section with a large number of conductors arranged in parallel at regular intervals on the edge of the substrate (normal conductor density 8 to 12 pieces/mm), and the other end of the conductor is connected to the drive circuit. It is used by connecting.

(従来の技術) 従来、この記録電極板としては、銅張#層板ケ蝕刻する
ものと、絶縁ワイヤ葡使用するものとが知られている。
(Prior Art) Conventionally, as recording electrode plates, there have been known those using etched copper-clad #layer plates and those using insulated wires.

絶縁ワイヤ葡使用するものは、例えば、円筒状のフレキ
シブル基板に絶縁ワイヤケコイル状に巻付け、電極部と
なる部分ケ樹脂で固定し、この部分ケ軸方向に切断し、
絶縁ワイヤの断面全露出させて電極部とし、フレキシブ
ル基板〒平面状にし、絶縁ワイヤの他端葡1本1本はん
だ付けにより駆動回路に接続して製造している。
Insulated wire is used, for example, by wrapping the insulated wire in a coil around a cylindrical flexible substrate, fixing the part that will become the electrode part with resin, and cutting this part in the axial direction.
The entire cross section of the insulated wire is exposed to serve as the electrode part, a flexible board is made into a flat shape, and the other end of the insulated wire is connected to the drive circuit by soldering one by one.

このため、端末のはんだ付けに多くの時間r要しコスト
高となる。またはんだ付けの信頼性紫確保するには熟練
を要す。
Therefore, it takes a lot of time to solder the terminals, resulting in high costs. It also requires skill to ensure the reliability of soldering.

銅張積層fii’i蝕刻するものは、銅張積層板にエツ
チングレジスト’に形成し、蝕刻により11mro当り
8〜12本の線密度の平行回路群會もつ回路音形成する
ものであるが次の欠点ヶもつ〇(1)通常の銅箔が65
μmと厚いため100μm以下のエツチングか非常に困
難となり5本712本/ filmの線密度ケ得ること
ができるが、回路の断面積(ドツト)が小さくなるため
、印刷密度か薄くなる。
The copper clad laminate fii'i etching method is to form a copper clad laminate with an etching resist and to form a circuit sound having a parallel circuit group with a line density of 8 to 12 lines per 11 mRO by etching. Has some defects〇(1) Ordinary copper foil is 65
Because it is as thick as 100 μm, it is extremely difficult to etch it below 100 μm, and a linear density of 5 lines/712 lines/film can be obtained, but since the cross-sectional area (dot) of the circuit becomes smaller, the printing density becomes thinner.

(6)銅張積層板製造工程において発生する銅箔面のへ
こみやキズなどにより断線、ショートが発生し、歩留り
か悪い。
(6) Disconnections and short circuits occur due to dents and scratches on the copper foil surface that occur during the manufacturing process of copper-clad laminates, resulting in poor yields.

このような墨から、エツチング法ではなく、必1 要な
部分にめっきにより回路音形成するアディティブ法か微
細パターンの形成に適するが、現状では、不必要な場所
にもめっきが析出する銅ふり現象や耐めっき性に優れ、
安定性の高いレジストの開発などがあり70μm以下の
ライン(線密度7本/mm)が形成できない。
From this type of ink, it is suitable for forming fine patterns by using the additive method, which forms circuit sounds by plating on the necessary areas, rather than the etching method, but at present, the copper splatter phenomenon, in which plating precipitates in unnecessary places, is used. and has excellent plating resistance,
Due to the development of highly stable resists, lines smaller than 70 μm (line density 7 lines/mm) cannot be formed.

(発明の目的) 本発明の目的は、高い線密度?安定的に得ることができ
る記録電極板の製造法紫提供するものである。
(Objective of the invention) Is the object of the invention high linear density? The present invention provides a method for producing a recording electrode plate that can be stably obtained.

(発明の構成) 本発明は、金属板上に形成された銅めりき層にレジスト
會形成し、金めつきあるいは金めつき後ニッケルめっき
ヶ行ったのち、更に銅めっし、パターン付きMffik
形成する工程と、上記パターン付き鋼箔の酸化銅処理面
にプリプレグを重ね合せ、加熱加圧して積層体r形成す
る工程と、上記積層体に穴あけ、穴内壁の銅めっき會行
った後、更にレジス)k形成したのち、ハンダめっき、
レジスト剥離後、エツチングする工程よりなる記録電極
板の製造法である。
(Structure of the Invention) The present invention forms a resist on a copper plated layer formed on a metal plate, performs gold plating or nickel plating after gold plating, and then further copper plating and patterned Mffik.
After forming a prepreg on the copper oxide treated surface of the patterned steel foil and applying heat and pressure to form a laminate, drilling a hole in the laminate and copper plating the inner wall of the hole, further After forming resist) k, solder plating,
This is a method for manufacturing a recording electrode plate, which includes a step of etching after removing the resist.

図面に基いて、本発明の一実施例紫更に詳細に説、明す
る。
An embodiment of the present invention will be described and explained in more detail with reference to the drawings.

銅張積層板の欠点であるへこみやキズ盆排除するために
、第1図に示したようにステンレス板1に、剥離可能な
ように電気めっきや無電解めっきで銅めっき層2(厚み
は例えば20μm)r形成する0銅めっき層20表面に
、感光性レジストフィルムγラミネートする方法又は敵
状の感光性レジストパターン、乾燥するこ□とによりレ
ジスト層紫形成し、露光、現像により第2図のようにレ
ジストパターン3ケ形成する0記録i1を極部のS密度
が低い場合は、スクリーン印刷法でレジストパターンケ
形成してもよい。
In order to eliminate the dents and scratches that are the drawbacks of copper-clad laminates, as shown in Figure 1, a copper plating layer 2 (with a thickness of e.g. 20 μm) r On the surface of the 0 copper plating layer 20 to be formed, a photosensitive resist film γ is laminated or a photosensitive resist pattern is formed in the form of a photosensitive resist, and then a purple resist layer is formed by drying. If the S density at the extreme portion of the 0 recording i1 in which three resist patterns are formed is low, the resist patterns may be formed by screen printing.

次に、銅めっき層2とエツチング条件の異なる金めつき
あるいは金めつき後ニッケルめっきケ行い耐蝕層4(厚
みは例えば1μm)k形成した後、銅めっきパターン5
葡形成する0これらのめっきは、電気めっき、無msめ
っきのいずれでもよい。厚みは例えば60μmである。
Next, gold plating with different etching conditions from the copper plating layer 2 or nickel plating after gold plating is performed to form a corrosion-resistant layer 4 (thickness: 1 μm, for example), and then a copper plating pattern 5 is formed.
These platings may be either electroplating or MS-less plating. The thickness is, for example, 60 μm.

そして第4図に示したようにレジストパターン5− 全剥離したのち、プリプレグとの接着力會向上させるた
めに銅めっきパターン5と銅めっき層2の表面に酸化銅
皮膜音形成する。酸化銅皮膜は例えば亜塩素酸ソーダ、
水酸化ナトリウム水溶液により形成される〇 次に、第5図に示したようにステンレス板1ヶ機械的に
剥離し、パターン付き銅箔6全形成し、第6図に示した
ように、パターン付き銅箔6の酸化銅処理面にプリプレ
グ7と内l−回路板8ヶ交互に重ね合せさらにパターン
付き鉤だの反対側に銅箔9を配し、加熱加圧して積層体
r形成する。
After the resist pattern 5 is completely peeled off as shown in FIG. 4, a copper oxide film is formed on the surfaces of the copper plating pattern 5 and the copper plating layer 2 in order to improve the adhesive strength with the prepreg. For example, copper oxide film is made of sodium chlorite,
Next, as shown in Fig. 5, one stainless steel plate was mechanically peeled off, and the entire patterned copper foil 6 was formed, as shown in Fig. 6. The prepregs 7 and the inner circuit boards 8 are alternately stacked on the copper oxidized surface of the copper foil 6, and the copper foil 9 is placed on the opposite side of the patterned hook, and heated and pressed to form a laminate.

プリプレグ7は、ガラス布にエポキシ樹脂、ボリイξド
樹脂、ポリエステル樹脂等の熱硬化性樹脂ケ含浸させ、
Bステージの状態まで硬化させたものケ使用することか
できる。また内層回路板は、銅張り積層板を用いてサブ
トラクト法やセミアディティブ法によって製造したもの
等ケ使用することができる。
The prepreg 7 is made by impregnating glass cloth with thermosetting resin such as epoxy resin, polyester resin, etc.
Only those that have been cured to B stage can be used. Further, the inner layer circuit board may be one manufactured by a subtract method or a semi-additive method using a copper-clad laminate.

上記積層体にドリル等で穴あけしたのち、無6− 電解鋼めっき又は無電解銅めっきと電気鋼めっき〒使用
して導通孔r形成する。
After drilling holes in the laminate with a drill or the like, conductive holes r are formed using electroless steel plating or electroless copper plating and electric steel plating.

次に穴内、パッド部および必要とされる表面パターンケ
除く部分に第2図のレジストパターン6と同様の手法で
レジスl”r形成し、半田めっきしたのちレジス)k剥
離する。
Next, a resist l''r is formed in the hole, in the pad area, and in the area other than the required surface pattern by the same method as the resist pattern 6 in FIG. 2, and after solder plating, the resist l''r is peeled off.

そして、半田めっき層16ケ腐蝕させることなく、銅お
よび酸化銅(Cub)皮膜tエツチングするためにクロ
ム酸と硫酸の水浴准でエツチングする。
Then, in order to etch the copper and copper oxide (Cub) films without corroding the solder plating layer 16, etching is performed in a water bath of chromic acid and sulfuric acid.

なお、半田めっき葡エッチンクレジストとするサブトラ
クト法のエツチングは、通常アンモニウムイオン盆含む
エツチング液や過硫識塩を含むエツチング液が使用され
るか、これらのエツチング液は酸化銅のエツチング速度
が極めて遅い欠点かあるため作業効率上好ましくない。
In addition, when etching the solder plated etch resist using the subtract method, an etching solution containing an ammonium ion basin or an etching solution containing a supersulfur salt is usually used, or these etching solutions have an extremely high etching speed for copper oxide. It is unfavorable in terms of work efficiency because it has the disadvantage of being slow.

上記のエツチングにより、ベースとなった銅1 箔がエ
ツチング除去されるとあらかじめ形成された回路が基板
内に埋め込まれた形で露出する。
When the copper foil serving as the base is etched away by the above-described etching, the circuit formed in advance is exposed in the form of being embedded in the substrate.

またエツチングは金めつき層で停止するため、オーバー
エッチによるパターンの断線か発生しない特長?もって
いる。
Also, since the etching stops at the gold-plated layer, there is no risk of pattern breakage due to over-etching. I have it.

第7図は、このようにして得られた記録電極板の断面図
に示すもので、10はスルーホールめっき、11は内層
回路、12は銅箔9?ベースにした回路、4と5はあら
かじめ形成された回路で、2はエツチングされずに残り
fc銅市である。
FIG. 7 shows a cross-sectional view of the recording electrode plate thus obtained, in which 10 is a through-hole plating, 11 is an inner layer circuit, and 12 is a copper foil 9? The base circuits 4 and 5 are preformed circuits, and 2 is the fc copper plate that remains unetched.

(発明の効果) 本発明の記録電極板の製造法に於て次の効果ケ達成する
ことができる。
(Effects of the Invention) The following effects can be achieved in the method of manufacturing a recording electrode plate of the present invention.

(1)表面にへこみやキズの無い銅めっき面上にパター
ンケ形成することにより、線巾、線間隔がそれぞれ70
μm以下の微細パターン會容易に得ることができる。こ
のため8本/mm〜16本/ filmの高い線密匿の
記峰電極部が高歩留りで製造できる。
(1) By forming a pattern on a copper-plated surface with no dents or scratches on the surface, the line width and line spacing are each 70 mm.
Fine patterns of micrometers or less can be easily obtained. Therefore, a highly line-contained recording electrode part of 8 lines/mm to 16 lines/film can be manufactured at a high yield.

(2)めっきで回路音形成するため、サブトラクト法よ
り回路の断面積(ドツト)か大きくなり、印刷密度が濃
くなる。
(2) Since the circuit sound is formed by plating, the cross-sectional area (dots) of the circuit is larger than that of the subtract method, and the printing density is higher.

(3)あらかじめ微aな記録電極部ケ形成したのち積層
するので、積層前に検査ができ、歩留りが向上する。
(3) Since a fine recording electrode portion is formed in advance and then laminated, inspection can be performed before lamination, improving yield.

(4)銅めっきにより形成した導体は樹脂に埋めこまれ
かつ金めつき層に保護されるのでオーバーエッチによる
断線がなく、サイドエッチがないため線巾精度か極めて
高い◎
(4) The conductor formed by copper plating is embedded in the resin and protected by the gold plating layer, so there is no disconnection due to overetching, and there is no side etching, so the line width accuracy is extremely high.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図から第7図は本発明の製造法葡示すための断面図
である〇 符号の説明 1 ステンレス板 2 銅めっき層 3 レジストパターン 4 金めつき層5 パターン銅
めっき 6 パターン付き銅箔7 プリプレグ 8 内
層回路板 9 銅rI310 スルーホールめっき11 内層回路
 12 銅M’にベースにした回路13 半田めっき層 9− 第1図 第4図 第1頁の続き ■Int、CI、’ 識別記号 庁内整理番号H05K
 3/42 6679−5F ■発 明 者 川 島 豊 下館市大字小ノー内 474−
1 to 7 are cross-sectional views showing the manufacturing method of the present invention. 〇 Explanation of symbols 1 Stainless steel plate 2 Copper plating layer 3 Resist pattern 4 Gold plating layer 5 Patterned copper plating 6 Patterned copper foil 7 Prepreg 8 Inner layer circuit board 9 Copper rI310 Through-hole plating 11 Inner layer circuit 12 Circuit based on copper M' 13 Solder plating layer 9- Figure 1 Figure 4 Continued from page 1 ■Int, CI,' Identification symbol Inside the office Reference number H05K
3/42 6679-5F ■Inventor Yutaka Kawashima 474 Konouchi, Shimodate City

Claims (1)

【特許請求の範囲】[Claims] 1、 金属版上に形成された銅めっきノーにレジスト紫
形成し、金めつきあるいは金めつき後ニッケルめっきr
行ったのち、更に銅めっきにパターン付き銅箔葡形成す
る工程と、上記パターン付き銅箔の酸化銅処理面にプリ
プレグ全型ね合せ、加熱加圧して積層体孕形成する工程
と、上記積層体に穴あけ、穴内壁の銅めっき會行った後
、更にレジス)k形成したのち、ハンダめっき、レジス
ト剥離後、エツチングする工程よVなる記録電極板の製
造法。
1. A purple resist is formed on the copper plating formed on the metal plate, and then gold plating or nickel plating is applied after gold plating.
After that, a step of forming a patterned copper foil on the copper plating, a step of laminating the entire prepreg on the copper oxide treated surface of the patterned copper foil, heating and pressurizing it to form a laminate, and a step of forming a laminate with the patterned copper foil. A method for producing a recording electrode plate V, which includes the steps of drilling a hole, copper plating the inner wall of the hole, forming a resist, solder plating, peeling off the resist, and etching.
JP12020384A 1984-06-12 1984-06-12 Method of producing recording electrode plate Pending JPS60263494A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12020384A JPS60263494A (en) 1984-06-12 1984-06-12 Method of producing recording electrode plate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12020384A JPS60263494A (en) 1984-06-12 1984-06-12 Method of producing recording electrode plate

Publications (1)

Publication Number Publication Date
JPS60263494A true JPS60263494A (en) 1985-12-26

Family

ID=14780453

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12020384A Pending JPS60263494A (en) 1984-06-12 1984-06-12 Method of producing recording electrode plate

Country Status (1)

Country Link
JP (1) JPS60263494A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62206897A (en) * 1986-03-05 1987-09-11 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Method of connecting by landless through-hole
JPS62276894A (en) * 1986-02-21 1987-12-01 株式会社メイコー Manufacture of conductor circuit board with through hole
JPH05504233A (en) * 1988-09-02 1993-07-01 ウエスチングハウス・エレクトリック・コーポレイション Printed circuit board and its manufacturing method
JPH09191164A (en) * 1996-01-10 1997-07-22 Asahi Chem Ind Co Ltd Fine thick film connection substrate and its manufacturing method
JP2008166464A (en) * 2006-12-28 2008-07-17 Toppan Printing Co Ltd Wiring substrate and manufacturing method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62276894A (en) * 1986-02-21 1987-12-01 株式会社メイコー Manufacture of conductor circuit board with through hole
JPH0466399B2 (en) * 1986-02-21 1992-10-23 Meikoo Kk
JPS62206897A (en) * 1986-03-05 1987-09-11 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Method of connecting by landless through-hole
JPH0347757B2 (en) * 1986-03-05 1991-07-22 Intaanashonaru Bijinesu Mashiinzu Corp
JPH05504233A (en) * 1988-09-02 1993-07-01 ウエスチングハウス・エレクトリック・コーポレイション Printed circuit board and its manufacturing method
JPH09191164A (en) * 1996-01-10 1997-07-22 Asahi Chem Ind Co Ltd Fine thick film connection substrate and its manufacturing method
JP2008166464A (en) * 2006-12-28 2008-07-17 Toppan Printing Co Ltd Wiring substrate and manufacturing method thereof

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