JPH05175636A - Manufacture of flexible printed wiring board - Google Patents

Manufacture of flexible printed wiring board

Info

Publication number
JPH05175636A
JPH05175636A JP34124991A JP34124991A JPH05175636A JP H05175636 A JPH05175636 A JP H05175636A JP 34124991 A JP34124991 A JP 34124991A JP 34124991 A JP34124991 A JP 34124991A JP H05175636 A JPH05175636 A JP H05175636A
Authority
JP
Japan
Prior art keywords
plating
forming
resist
etching
etching resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34124991A
Other languages
Japanese (ja)
Inventor
Osamu Otsuka
修 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP34124991A priority Critical patent/JPH05175636A/en
Publication of JPH05175636A publication Critical patent/JPH05175636A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make it possible to prevent a drop in flexibility and to deal with a high density pattern by forming plating only in a throughhole portion and a land portion. CONSTITUTION:A throughhole 4 is bored on a copper-clad film where copper foils 10 and 11 are bonded on both sides of a polyimide film 9. Then, a dry film is laminated thereon, thereby forming a negative type plating resist 12. The dry film is removed and an etching resist 13 is formed. Then, electroless copper plating and electrolytic plating 5 are carried out so as to take electric conduction for the copper foils 10 and 11. Then, the dry film is laminated, thereby forming a negative type resist 12. Then, there is formed an etching resist 14 for the throughhole and land portions by solder plating. Useless electroless plating, electrolytic plating and copper foils are etched so as to eliminate the solder plating and forming a specified circuit pattern.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、フレキシブルプリント
配線板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flexible printed wiring board.

【0002】[0002]

【従来の技術】従来のスルーホール導通構造をもつフレ
キシブルプリント配線板の製造法を図2に示す。図2
(1)に示すように、絶縁ベース材1の両面に導電材
2、3を被着したフレキシブルプリント配線板基材に、
所要のスルーホール用透孔4を設け、次に図2(2)に
示すように無電解めっきにて導電材2、3及びスルーホ
ール用透孔4の内面にめっき5を行い、導電材2、3間
の電気的導通を取る。次に電解めっきにて厚付けし、図
2(3)に示すように所要回路パターン部にエッチング
レジスト7を形成し、エッチングにて不要な導電材を除
去、エッチングレジストの剥離を行い、図2(4)に示
すような回路パターンを形成する。この様な手段では、
スルーホール部及び回路パターン部に硬い組織を有する
電解めっきが付着し、屈曲部においてはフレキシビリテ
ィが低下し、屈曲動作にて屈曲部回路パターンが断線す
ることがある。屈曲部の断線を解消する手段として、屈
曲部回路パターンに剥離可能なマスク材を被着、めっき
後マスクを剥離し、回路形成することで屈曲部にめっき
の付着を防止し、屈曲部のフレキシビリティを確保した
もの、例えば特開昭59−181094号及び特開昭5
7−79697号公報に記載されている技術がある。し
かし、マスク材を除去した後は、めっき境界面に段差が
発生するためパターンを形成する時に断線、くわれ等の
問題を発生させる。また回路パターンを形成し、被覆材
を積層したのち、両被覆材面にマスキングフィルムを貼
り合わせ、スルーホールを取るべき部分に両マスキング
フィルムを貫通する透孔を設けたのち、無電解めっきを
施し、最後にマスキングフィルムを取り去ることでスル
ーホール部のみに無電解めっきを施すもの、例えば特開
昭55−124295号公報に記載されている技術があ
る。しかし、回路パターンを形成した後、スルーホール
用透孔を明けるため基材の寸法変化を考慮して加工しな
ければならず、穴位置精度を良くするため非常に困難な
作業となる。
2. Description of the Related Art A conventional method for manufacturing a flexible printed wiring board having a through-hole conductive structure is shown in FIG. Figure 2
As shown in (1), on a flexible printed wiring board base material in which conductive materials 2 and 3 are adhered on both surfaces of an insulating base material 1,
The required through-hole through-hole 4 is provided, and then, as shown in FIG. 2B, electroless plating is applied to the conductive materials 2 and 3 and the through-hole through-hole 4 is plated 5 to form the conductive material 2. Electrical connection between 3 is taken. Next, thickening is performed by electrolytic plating, an etching resist 7 is formed on a required circuit pattern portion as shown in FIG. 2C, an unnecessary conductive material is removed by etching, and the etching resist is removed. A circuit pattern as shown in (4) is formed. In this way,
Electrolytic plating having a hard structure may adhere to the through-hole portion and the circuit pattern portion, flexibility may be deteriorated in the bending portion, and the bending portion circuit pattern may be broken by the bending operation. As a means of eliminating the disconnection of the bent portion, a peelable mask material is applied to the bent portion circuit pattern, the mask is peeled off after plating, and a circuit is formed to prevent the adhesion of plating to the bent portion, and the flexed portion of the bent portion is prevented. Those which ensure the ability, for example, Japanese Patent Laid-Open Nos. 59-181094 and 5
There is a technique described in JP-A-7-79697. However, after removing the mask material, a step is generated on the plating boundary surface, which causes problems such as disconnection and cracking when forming a pattern. Also, after forming the circuit pattern and laminating the covering material, a masking film is attached to both covering material surfaces, a through hole is formed through the both masking films at the portion where the through hole should be taken, and then electroless plating is applied. Finally, there is a technique in which electroless plating is applied only to the through-hole portion by removing the masking film, for example, a technique described in JP-A-55-124295. However, after forming the circuit pattern, the through holes for the through holes must be processed in consideration of the dimensional change of the base material, which is a very difficult work for improving the hole position accuracy.

【0003】[0003]

【発明が解決しようとする課題】この様な従来の製造方
法では、フレキシブルプリント配線板だけでなく、一般
のリジット配線板にも言えることであるが、エッチング
する際、銅箔面上に一様にめっきを行った後、回路形成
を行う。一般的には銅箔上にめっきが付着し厚くなる。
このためエッチング後の断面形状は垂直方向のエッチン
グだけではなく、エッチングレジストで保護された銅箔
が水平方向にもエッチングされ、銅箔だけのエッチング
に比べアンダーカット量が大きくなり、パターン幅、沿
面の精度が悪くなり、高密度パターンを形成することが
難しくなる。高密度パターンに対応するためには、パタ
ーン形成部分に電解めっきを付けない状態でパターン形
成することが必要となる。又、めっきが付着しているこ
とにより、フレキシビリティが低下し、屈曲部において
は、屈曲動作で断線に至るいう問題もある。この様な問
題を防止するために屈曲部にマスク材を付着させ、めっ
き後除去することが必要となるが、マスク材を付着、除
去させる工程は大幅な工数を要し、工程が煩雑化すると
いう問題がある。
The conventional manufacturing method as described above can be applied not only to a flexible printed wiring board but also to a general rigid wiring board. After plating on, the circuit is formed. Generally, the plating is thickened on the copper foil.
Therefore, the cross-sectional shape after etching is not limited to vertical etching, but copper foil protected by an etching resist is also etched horizontally, resulting in a larger undercut amount compared to etching copper foil alone. Accuracy becomes poor and it becomes difficult to form a high-density pattern. In order to deal with a high-density pattern, it is necessary to form a pattern in a state where electrolytic plating is not applied to the pattern forming portion. Further, since the plating is attached, the flexibility is lowered, and there is a problem that the bending operation causes disconnection at the bending portion. In order to prevent such a problem, it is necessary to attach a mask material to the bent portion and remove it after plating, but the step of attaching and removing the mask material requires a large number of steps and complicates the process. There is a problem.

【0004】[0004]

【課題を解決するための手段】本発明の製造法は、絶縁
材料の両面に導電材を有し、スルーホール用透孔を開孔
する前または後に所要の回路パターン部分にエッチング
レジスト像を形成する。次に無電解めっき、電解めっき
を行う。電解めっき後、めっきの上にエッチングレジス
ト像を所要な部分へ形成し、エッチングにより前記、導
電材及び無電解めっき、電解めっきを除去し、回路パタ
ーンを形成することを特徴とする。すなわち、本発明の
一実施例を図1に示すように、絶縁ベース材1、例えば
ポリイミドフィルム、ポリエステルフィルムの両面に導
電材2、3、例えば銅箔、アルミ箔を有する基材へドリ
ルまたはパンチなどでスルーホール用透孔を形成する工
程の前または後に、エッチングレジスト6、例えば半田
めっき、錫めっき、金めっき、液状レジスト、レジスト
インキなどを所要の回路パターン形状に印刷法、焼付法
を用いて形成する(図1(1)参照。)。次に無電解め
っき及び電解めっき5を施し、導電材2、3の電気的導
通を取り(図1(2)参照。)、スルーホール用透孔及
びランド部へエッチングレジスト7、例えば半田めっ
き、錫めっき、金めっき、液状レジスト、レジストイン
キを印刷法、焼付法を用いて形成する(図1(3)参
照。)。次にエッチングにて不要な導電材を除去した
後、エッチングレジストを剥離液にて除去し、回路形成
する(図1(4)参照。)。
According to the manufacturing method of the present invention, a conductive material is provided on both sides of an insulating material, and an etching resist image is formed on a required circuit pattern portion before or after opening a through hole for a through hole. To do. Next, electroless plating and electrolytic plating are performed. After electrolytic plating, an etching resist image is formed on a required portion on the plating, and the conductive material, electroless plating and electrolytic plating are removed by etching to form a circuit pattern. That is, as shown in FIG. 1, one embodiment of the present invention is to drill or punch into a base material having conductive materials 2, 3 such as copper foil or aluminum foil on both sides of an insulating base material 1, for example, a polyimide film or a polyester film. Before or after the step of forming through holes for through-holes, etc., an etching resist 6, for example, solder plating, tin plating, gold plating, liquid resist, resist ink, etc., is applied to a desired circuit pattern shape by a printing method or a baking method. Formed (see FIG. 1A). Next, electroless plating and electrolytic plating 5 are performed to establish electrical continuity between the conductive materials 2 and 3 (see FIG. 1 (2)), and etching resist 7 such as solder plating is applied to the through holes for through holes and lands. A tin plating, a gold plating, a liquid resist, and a resist ink are formed by using a printing method and a baking method (see FIG. 1 (3)). Next, after removing the unnecessary conductive material by etching, the etching resist is removed by a stripping solution to form a circuit (see FIG. 1 (4)).

【0005】[0005]

【作用】回路パターンのエッチングレジストを無電解め
っき前に形成することで、回路パターンのめっきレジス
トとしての働きを兼ねる。このため無電解めっき、電解
めっき後エッチングを行うことで回路パターン上の無電
解めっき及び電解めっきはエッチングされ、絶縁ベース
材上の導電材2、3にて回路パターンが形成され、エッ
チング精度が向上し、高密度パターンに対応することが
できる。又、スルーホール部及びランド部に無電解めっ
き及び電解めっきを形成し、屈曲部の無電解めっき及び
電解めっきをエッチングすることで、フレキシビリティ
を失わず、導電材2、3間の電気的導通をとることがで
きる。なお、無電解めっき、電解めっき後のエッチング
レジストをスルーホール穴以外の所要の部分8に形成す
ることで、導電材の厚さを部分的に厚くすることも可能
である。
[Function] By forming the etching resist of the circuit pattern before the electroless plating, it also functions as the plating resist of the circuit pattern. For this reason, the electroless plating and the electrolytic plating are followed by etching to etch the electroless plating and the electrolytic plating on the circuit pattern, and the conductive material 2 and 3 on the insulating base material form the circuit pattern, improving the etching accuracy. In addition, it is possible to deal with high-density patterns. In addition, electroless plating and electrolytic plating are formed on the through-holes and lands, and the electroless plating and electrolytic plating on the bent portions are etched, so that flexibility is not lost and electrical conduction between the conductive materials 2 and 3 is maintained. Can be taken. It is also possible to partially increase the thickness of the conductive material by forming an etching resist after electroless plating or electrolytic plating on a required portion 8 other than the through hole.

【0006】[0006]

【実施例】実施例の製造工程の断面図を図3に示す。ポ
リイミド25μmのフィルム9の両面に圧延銅箔35μ
m10、11をエポキシ系接着剤にて接着した銅張りフ
ィルムに、ドリル加工にてスルーホール用透孔4を明け
る(図3(1)参照。) 次にドライフィルムをラミネート、焼付、現像し、回路
パターンに対してネガタイプのめっきレジスト12を形
成する(図3(2)参照。)。次に、半田めっきを厚さ
5〜10μm施し、ドライフィルムを剥離液にて除去
し、半田めっきにてエッチングレジスト13を形成する
(図3(3)参照。)。次に、無電解銅めっきを0.5
〜1μm、電解銅めっき5を15〜20μm施し、圧延
銅箔10、11の電気的導通を取る。次にドライフィル
ムをラミネート、焼付、現像し、回路パターンに対して
ネガタンプのめっきレジスト12を形成する(図3
(4)参照。)。次に、半田めっきを厚さ5〜10μm
施し、半田めっきにてスルーホール用透孔及びランド部
のエッチングレジスト14を形成する(図3(5)参
照。)。次に、アルカリエッチングにて不要の無電解め
っき、電解めっき、銅箔をエッチングし、半田めっきを
剥離液で除去し、所要の回路パターンを形成する(図3
(6)参照。)。
EXAMPLE FIG. 3 shows a cross-sectional view of a manufacturing process of an example. Rolled copper foil 35μ on both sides of polyimide 25μm film 9
The through holes 4 for the through holes are opened by drilling in the copper-clad film in which m10 and m11 are bonded with an epoxy adhesive (see FIG. 3 (1).) Next, a dry film is laminated, baked, and developed. A negative type plating resist 12 is formed on the circuit pattern (see FIG. 3 (2)). Next, solder plating is applied to a thickness of 5 to 10 μm, the dry film is removed with a stripping solution, and an etching resist 13 is formed by solder plating (see FIG. 3C). Next, 0.5 electroless copper plating
˜1 μm, electrolytic copper plating 5 is applied for 15 to 20 μm, and the rolled copper foils 10 and 11 are electrically connected. Next, a dry film is laminated, baked, and developed to form a negative plating resist 12 on the circuit pattern (FIG. 3).
See (4). ). Next, solder plating is applied to a thickness of 5 to 10 μm.
Then, the through holes for through holes and the etching resist 14 for the lands are formed by solder plating (see FIG. 3 (5)). Next, unnecessary electroless plating, electrolytic plating, and copper foil are etched by alkali etching, and the solder plating is removed with a stripping solution to form a required circuit pattern (FIG. 3).
See (6). ).

【0007】[0007]

【発明の効果】スルーホール部及びランド部のみに無電
解めっき及び電解めっきを形成することによって、フレ
キシビリティを低下することを防止できる。銅箔上にエ
ッチングレジストを形成することで高密度パターンに対
応することができる。また、電解めっき後、所要のパタ
ーン部にエッチングレジスト15を形成し、エッチング
することで部分的に銅箔を厚くすることができる。
EFFECTS OF THE INVENTION By forming electroless plating and electrolytic plating only on through holes and lands, it is possible to prevent deterioration of flexibility. By forming an etching resist on the copper foil, a high density pattern can be dealt with. Further, after the electrolytic plating, the etching resist 15 is formed on a desired pattern portion, and the copper foil can be partially thickened by etching.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の各工程の説明をするための
断面図である。
FIG. 1 is a cross-sectional view for explaining each step of one embodiment of the present invention.

【図2】従来例の各工程を説明するための断面図であ
る。
FIG. 2 is a cross-sectional view for explaining each step of a conventional example.

【図3】本発明の他の実施例の各工程を説明するための
断面図である。
FIG. 3 is a cross-sectional view for explaining each step of another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 絶縁ベース材 2 導
電材 3 導電材 4 ス
ルーホール用透孔 5 めっき(無電解めっき及び電解めっき) 6 エ
ッチングレジスト 7 エッチングレジスト 8 エ
ッチングレジスト 9 ポリイミドフィルム 10 圧
延銅箔 11 圧延銅箔 12
めっきレジスト 13 エッチングレジスト 14
エッチングレジスト 15 エッチングレジスト
DESCRIPTION OF SYMBOLS 1 Insulating base material 2 Conductive material 3 Conductive material 4 Through-hole through hole 5 Plating (electroless plating and electrolytic plating) 6 Etching resist 7 Etching resist 8 Etching resist 9 Polyimide film 10 Rolled copper foil 11 Rolled copper foil 12
Plating resist 13 Etching resist 14
Etching resist 15 Etching resist

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】絶縁材料の両面に導電材を有し、スルーホ
ール用透孔を開孔する前または後に所要の回路パターン
部分にエッチングレジスト像を形成する。次に無電解め
っき、電解めっきを行う。電解めっき後、めっきの上に
エッチングレジスト像を所要な部分へ形成し、エッチン
グにより前記、導電材及び無電解めっき、電解めっきを
除去し、回路パターンを形成することを特徴とするフレ
キシブルプリント配線板の製造法。
1. An electrically conductive material is provided on both sides of an insulating material, and an etching resist image is formed on a required circuit pattern portion before or after forming a through hole for a through hole. Next, electroless plating and electrolytic plating are performed. A flexible printed wiring board characterized in that after electroplating, an etching resist image is formed on a required portion on the plating, and the conductive material, electroless plating, and electroplating are removed by etching to form a circuit pattern. Manufacturing method.
JP34124991A 1991-12-24 1991-12-24 Manufacture of flexible printed wiring board Pending JPH05175636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34124991A JPH05175636A (en) 1991-12-24 1991-12-24 Manufacture of flexible printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34124991A JPH05175636A (en) 1991-12-24 1991-12-24 Manufacture of flexible printed wiring board

Publications (1)

Publication Number Publication Date
JPH05175636A true JPH05175636A (en) 1993-07-13

Family

ID=18344568

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34124991A Pending JPH05175636A (en) 1991-12-24 1991-12-24 Manufacture of flexible printed wiring board

Country Status (1)

Country Link
JP (1) JPH05175636A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100576652B1 (en) * 2004-07-15 2006-05-08 엘지마이크론 주식회사 Method for making double sides wiring substrate
US7263769B2 (en) 2004-10-20 2007-09-04 Matsushita Electric Industrial Co., Ltd. Multi-layered flexible print circuit board and manufacturing method thereof
US7367116B2 (en) 2003-07-16 2008-05-06 Matsushita Electric Industrial Co., Ltd. Multi-layer printed circuit board, and method for fabricating the same
KR100851077B1 (en) * 2007-08-17 2008-08-12 삼성전기주식회사 Manufacturing method of substrate
US7543376B2 (en) 2004-10-20 2009-06-09 Panasonic Corporation Manufacturing method of flexible printed wiring board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7367116B2 (en) 2003-07-16 2008-05-06 Matsushita Electric Industrial Co., Ltd. Multi-layer printed circuit board, and method for fabricating the same
KR100576652B1 (en) * 2004-07-15 2006-05-08 엘지마이크론 주식회사 Method for making double sides wiring substrate
US7263769B2 (en) 2004-10-20 2007-09-04 Matsushita Electric Industrial Co., Ltd. Multi-layered flexible print circuit board and manufacturing method thereof
US7543376B2 (en) 2004-10-20 2009-06-09 Panasonic Corporation Manufacturing method of flexible printed wiring board
KR100851077B1 (en) * 2007-08-17 2008-08-12 삼성전기주식회사 Manufacturing method of substrate

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