TWI232527B - Method for manufacturing film ball grid array package - Google Patents

Method for manufacturing film ball grid array package Download PDF

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Publication number
TWI232527B
TWI232527B TW093100608A TW93100608A TWI232527B TW I232527 B TWI232527 B TW I232527B TW 093100608 A TW093100608 A TW 093100608A TW 93100608 A TW93100608 A TW 93100608A TW I232527 B TWI232527 B TW I232527B
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TW
Taiwan
Prior art keywords
thin film
film substrate
substrate strip
adhesive layer
grid array
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Application number
TW093100608A
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Chinese (zh)
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TW200524060A (en
Inventor
Kuo-Yuan Lee
Kuang-Chi Chao
Cheng-Tai Chen
Original Assignee
Walton Advanced Eng Inc
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Priority to TW093100608A priority Critical patent/TWI232527B/en
Application granted granted Critical
Publication of TWI232527B publication Critical patent/TWI232527B/en
Publication of TW200524060A publication Critical patent/TW200524060A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

A method for manufacturing film ball grid array is disclosed. A film substrate strip attaches an attaching layer. An lower surface of the film substrate strip is comprised a plurality of die-attaching areas, a plurality of packaging surrounding areas and a plurality of orientating areas. The attaching layer is comprised a plurality of frame-attaching tapes and a die-attaching tape. The frame-attaching tapes and the die-attaching tape is integrated with attaching to the lower surface of the film substrate strip, wherein the frame-attaching tapes is disposed on the orientating areas of the film substrate strip, and the die-attaching tape is disposed on the die-attaching areas and packaging surrounding areas of the film substrate strip. An orientating frame attaches on the attaching layer which parts are on the orientating areas of the film substrate strip for maintaining film substrate strip is flatness.

Description

12325271232527

五、發明說明（1) 【發明所屬之技術領域】 本發明係有關於—錄托 俜有Μ ^ ^ ^ 種球格陣列封裝之製造方法，特別 【先前技術】， 裝之“方法。 種技封裝技術〔βΜ1 Grid —，脇〕為-陳Μ # a# π ^，、、、牛導體封裝之製造方法，然而一般球格 == 基板材質為訂、FR~4㈣-5之硬板，其 序度马ϋ· 25mm以上，故咭其4c + +上社 ^ ί板ίίΐΓί16〕之問題，然而，在利用薄，膜〔filra〕 ί $ #涡f/ 9卩列封裝之基板時，由於該薄膜基板之厚度 係不^0·2_，在封裝過程中會有搬運、處理之問題。 # Wft /之薄^球袼陣列封裝之製造方法，其係將厚度不 二：始："ϋ膜基板條貼合於一定位框架，利用該定位 /^》膜基板條之平整度，用以避免該薄膜基板條 緣％錄ί中挽曲、變形’產生搬運、處理之問題，再繼 =、=:曰:、打線、封膠等封裝製程，而該薄膜基板條 、二=王木之貼合方法係先將該薄膜基板條置於該定位 框杀^丄再利用複數個貼框膠帶將該薄膜基板條之兩邊貼 合於该疋位框架，不但需要再投資額外之機器設備，且以 a些貼框膠帶貼合該基板條與該定位框架，該些貼框膠帶 係為^露，在封裝過程中該些貼框膠帶容易與機台摩擦而 產生靜電’造成產品損害，此外，因為該些框膠帶並非一 體形成，在該薄膜基板條與該定位框架之貼合過程中， 些框膠帶會因拉開的力量不同，而使該薄膜基板條與該-=、V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a manufacturing method of a ball grid array package, specifically [prior art], and a method of mounting. The packaging technology [βΜ1 Grid —, threat] is-ChenM # a # π ^ ,,,, and the manufacturing method of cattle conductor packaging, but the general ball grid == substrate material is a custom, FR ~ 4㈣-5 rigid board, its Dimensions: 25mm or more, so the problem of 4c + + Shangshe ^ ί 板 ίίΓΓί 16], however, when using a thin, thin film [filra] ί $ # vorf / 9 卩 package substrate, due to the thin film The thickness of the substrate is not ^ 0 · 2_, and there will be handling and handling problems during the packaging process. # Wft / 的 薄 ^ Ball 袼 Array packaging manufacturing method, which is based on the thickness: Start: " ϋ film substrate The strip is attached to a positioning frame, and the flatness of the positioning / ^ "film substrate strip is used to avoid the problem of handling and processing caused by the bending and deformation of the film substrate edge, and then continue =, = : Said: packaging processes such as wire bonding, sealing, etc., and the film substrate strip, two = Wang Muzhi's bonding side The film substrate strip is placed in the positioning frame first, and then the two sides of the film substrate strip are attached to the positioning frame with a plurality of framed tapes. Not only does it require additional investment in equipment and equipment, but also some The framing tape adheres the substrate strip and the positioning frame. The framing tape is exposed. During the packaging process, the framing tape is easy to rub against the machine and generate static electricity. This causes product damage. In addition, because of these The frame tape is not integrally formed. During the bonding process of the film substrate strip and the positioning frame, the frame tape will be different from the-=,

ι^^ιι 1^^ 第9頁 1232527ι ^^ ιι 1 ^^ Page 9 1232527

位框架貼合不良。 【發明内容】 本發明之主要目的係在於提供一種薄膜球格陣列 之製造方法，利用一包含有複數個貼框膠層及一點晶勝裝 之貼合膠一體貼設於一薄膜基板條之下表面，該黏晶膠^ 係設於該薄膜基板條之黏晶區與封装周邊區，該些貼樞取 I係設於該薄膜基板條之定位邊界區，使一定位框架^二 於定位邊界區之黏晶膠層，以取代習知之貼框膠帶，減少 額外之機器設備投資。 '/ 本發明之次一目的係在於提供一種薄膜球格陣列封裳 之製造方法，利用一包含有複數個貼框膠層及一黏晶膠層 之貼合膠一體貼設於一薄膜基板條之下表面，該些貼框膠 層係设於該薄膜基板條與一定位框架之間，以避免該也貼 框膠層與封裝機台直接接觸，減少靜電產生。 依本發明之薄膜球格陣列封裝之製造方法包含有下列 步驟：首先，提供一薄膜基板條，該薄膜基板條係具有一 上表面、一下表面及至少一開孔，該薄膜基板條之該下表 面係包含有複數個黏晶區，複數個封裝周邊區及複數個定 位邊界區；之後，貼合一貼合膠，該貼合膠係包含有複數 個貼框膠層及一黏晶膠層，該些貼框膠層及該黏晶膠層係 一體貼設於該薄膜基板條之該下表面，該些貼框膠層係設 於該薄膜基板條之定位邊界區，該黏晶膠層係設於該薄膜 基板條之黏晶區與封裝周邊區；之後，貼設一定位框架， 該疋位框架係具有一開口’該開口之尺寸係小於該薄膜基Bit frame fits poorly. [Summary of the Invention] The main object of the present invention is to provide a method for manufacturing a thin film ball grid array, which uses a laminating adhesive comprising a plurality of frame-adhesive layers and a single crystal wafer to be integrated under a thin-film substrate strip. On the surface, the die-attach adhesive ^ is provided on the die-bond region of the thin-film substrate strip and the peripheral area of the package, and the stickers are taken from the positioning boundary region of the thin-film substrate strip, so that a positioning frame ^ 2 is located on the positioning boundary. It can replace the conventional framed tape to reduce the additional investment in machinery and equipment. '/ A second object of the present invention is to provide a method for manufacturing a thin film ball grid array sealing skirt, which is integrally attached to a thin film substrate strip by using a laminating adhesive including a plurality of frame adhesive layers and a crystal adhesive layer. On the lower surface, the frame-adhesive layers are disposed between the film substrate strip and a positioning frame to prevent the frame-adhesive layers from directly contacting the packaging machine and reduce static electricity. The manufacturing method of the thin film ball grid array package according to the present invention includes the following steps: First, a thin film substrate strip is provided. The thin film substrate strip has an upper surface, a lower surface, and at least one opening. The surface system includes a plurality of adhesive regions, a plurality of packaging peripheral regions, and a plurality of positioning boundary regions; and then, an adhesive is applied, and the adhesive system includes a plurality of frame adhesive layers and a crystal adhesive layer. The frame-adhesive layer and the crystal-adhesive layer are integrally attached to the lower surface of the thin-film substrate strip, and the frame-adhesive layers are disposed at a positioning boundary region of the film-substrate strip, and the crystal-adhesive layer It is located in the die-bonding area and the peripheral area of the package of the thin-film substrate strip; then, a positioning frame is attached, and the positioning frame has an opening. The size of the opening is smaller than that of the thin-film substrate.

第10頁 1232527_ 說明(3) ' -----------^ J,之尺寸，該定位框架係貼合於在該基板之定位邊界區 U晶膠層；之後’貝占合複數個晶片，每一晶片係具有一 動面及一背面，該些晶片之主動面係形成有複數個銲 2，且該些銲墊係顯露於該開孔，該些晶片之主動面係 11该些黏晶區而貼合於該黏晶膠層，使得該黏晶膠層係 露於該些晶片；之後，再將該些晶片以複數個電性連接 裝置電性連接該些晶片與該薄膜基板條；以及形成一封膠 體保護該些晶片、該些電性連接裝置。 【實施方式】 參閱所附圖式’本發明將列舉以下之實施例說明。 •依本發明之一具體實施例，一種薄膜球格陣列封裝之 製造方法如下所述，請參閱第i及2人圖，第i圖係為該薄膜 球格陣列封裝之製造方法，提供一薄膜基板條11()，該薄、 膜基板條110之上視示意圖，第2A圖係為該薄膜基板條11() 之截面示意圖，該薄膜基板條1 1 〇之材質係為聚亞醯胺 〔Polyimide，PI〕，其寬度一般係為35mm、48mm 或 70mm ’而其厚度係為不超過〇 · 2min，該薄膜基板條11 〇係具 有一上表面111、一下表面丨丨2及至少一開孔丨丨3，該薄膜 基板條11 0之下表面11 2係包含有複數個黏晶區丨丨4，複數 個封裝周邊區11 5及複數個定位邊界區π 6，該些定位邊界 區116形成有複數個傳動孔117〔Sprocket〕；請再參閱第 2B及3圖，貼合一貼合膠12〇，第2B圖係為該貼合膠120貼 合於該基板條110之截面示意圖，第3圖係為該貼合膠12〇 貼合於該基板條1 10之下視示意圖，該貼合膠12〇係包含有Page 10 1232527_ Description (3) '----------- ^ J, the positioning frame is attached to the U crystal glue layer in the positioning boundary area of the substrate; after that, A plurality of wafers, each of which has a moving surface and a back surface, the active surfaces of the wafers are formed with a plurality of welds 2, and the pads are exposed in the openings, and the active surfaces of the wafers are 11 The sticky crystal regions are adhered to the sticky adhesive layer, so that the sticky adhesive layer is exposed on the wafers; then, the wafers are electrically connected to the wafers and the film by a plurality of electrical connection devices. A substrate strip; and forming a gel to protect the wafers and the electrical connection devices. [Embodiment] The present invention will be described with reference to the attached drawings. • According to a specific embodiment of the present invention, a method for manufacturing a thin film ball grid array package is as follows, please refer to the i and 2 figures, which is a method for manufacturing the thin film ball grid array package, and provides a thin film Substrate strip 11 (), a schematic top view of the thin, film substrate strip 110, FIG. 2A is a schematic cross-sectional view of the thin film substrate strip 11 (), and the material of the thin film substrate strip 1 1 10 is polyimide [ Polyimide, PI], its width is generally 35mm, 48mm or 70mm 'and its thickness is not more than 0.2 minutes, the thin film substrate strip 110 has an upper surface 111, a lower surface 丨 2 and at least one opening丨 丨 3, the lower surface 11 2 of the thin film substrate strip 110 includes a plurality of sticky crystal regions 丨 丨 4, a plurality of packaging peripheral regions 115 and a plurality of positioning boundary regions π 6, and the positioning boundary regions 116 are formed There are a plurality of transmission holes 117 [Sprocket]; please refer to Figs. 2B and 3 again, and apply a laminating adhesive 120. Fig. 2B is a schematic cross-sectional view of the laminating adhesive 120 attached to the substrate strip 110. Figure 3 is a schematic view of the laminating adhesive 12 attached to the substrate strip 1 10 The adhesive bonding system comprises 12〇

第11頁 1232527 五、發明說明（4) 複數個貼框膠層1 2 1及一黏晶膠層1 22，該些貼框膠層1 2 1Page 11 1232527 V. Description of the invention (4) A plurality of framed adhesive layers 1 2 1 and a sticky crystal adhesive layer 1 22, the framed adhesive layers 1 2 1

及該黏晶膠層1 2 2係先塗施於一承載薄膜〔圖未繪出〕， 再一體轉貼於該薄膜基板條1 1 〇之下表面1 1 2，即該些貼框 膠層1 2 1及該黏晶膠層1 22係一體貼設於該薄膜基板條1 1 0 之下表面1 12，該貼合膠120係可全面覆蓋該薄膜基板條 1 1 0之下表面1 1 1或僅留下該薄膜基板條1 1 〇之傳動孔Π 7不 覆蓋，其中該些貼框膠層1 2 1係設於該薄膜基板條1 1 〇之定 位邊界區116，該黏晶膠層1 22係設於該薄膜基板條1 1〇之 黏晶區11 4與封裝周邊區11 5，該些貼框膠層1 2 1之軟化溫 度係低於该黏晶膠層1 2 2之軟化溫度，在本實施例中，該 些貼框膠層1 2 1之軟化溫度係為1 〇 〇〜1 2 5 °C，該黏晶膠層 I 2 2之軟化溫度係為1 5 0〜1 7 5 °C，該黏晶膠層1 2 2係為一 彈性膠層〔elastomer〕，其係具有至少一開孔丨23 ,且該 黏晶膠層1 2 2之開孔1 2 3尺寸係等於該基板11 〇之開孔11 3， 该黏晶膠層1 2 2之厚度係不超過〇 · 1 mm，較佳地，該些貼框 膠層121之厚度係與該黏晶膠層丨22之厚度相同；請再參閱 第2C、3及4圖，第2C圖係為該薄膜球格陣列封裝之製造方 法中，貼設一定位框架1 3 〇時，該定位框架丨3 〇與該基板條And the adhesive layer 1 2 2 is first applied to a carrier film (not shown), and then integrally transferred to the lower surface 1 1 2 of the film substrate strip 1 1 0, that is, the framed adhesive layers 1 21 and the adhesive layer 1 22 are integrally attached to the lower surface 1 12 of the film substrate strip 1 1 0, and the adhesive 120 can completely cover the lower surface of the film substrate strip 1 1 0 1 1 1 Or only the transmission holes Π 7 of the thin film substrate strip 1 1 0 are left uncovered, wherein the framed adhesive layers 1 2 1 are provided in the positioning boundary region 116 of the thin film substrate strip 1 1 0, and the sticky crystal adhesive layer 1 22 is provided in the die-bonding region 11 4 of the thin-film substrate strip 1 10 and the package peripheral region 115. The softening temperature of the frame adhesive layers 1 2 1 is lower than the softening of the die-bonding layer 1 2 2 Temperature, in this embodiment, the softening temperature of the framed adhesive layers 1 2 1 is 100 ~ 1 2 5 ° C, and the softening temperature of the viscous adhesive layer I 2 2 is 1 50 ~ 1 7 5 ° C, the viscose adhesive layer 1 2 2 is an elastic adhesive layer [elastomer], which has at least one opening 丨 23, and the viscous adhesive layer 1 2 2 has an opening 1 2 3 size system Is equal to the openings 11 3 of the substrate 11 〇 The thickness of 1 2 2 is not more than 0.1 mm. Preferably, the thickness of the framed adhesive layers 121 is the same as the thickness of the viscous adhesive layer 丨 22; please refer to Figures 2C, 3 and 4 again. FIG. 2C is a method for manufacturing the thin film ball grid array package. When a positioning frame 1300 is attached, the positioning frame 丨 3 〇 and the substrate strip

II 0之截面示意圖，第4圖係為該定位框架丨3 〇之上視示意 圖，该定位框架1 3 0係具有一開口 1 3J，該定位框架1 3 0之 該開口 1 3 1之尺寸係小於該薄膜基板條丨丨〇之尺寸，該定位 框架1 3 0係貼合於在該基板丨丨〇之定位邊界區丨丨6之該些貼 框膠層121 ,以增進該薄膜基板條11〇之平整度，由於該些 貼框膠層121之軟化溫度係為1〇〇〜125t，在貼設該定位A cross-sectional view of II 0, and FIG. 4 is a schematic top view of the positioning frame 丨 3 〇, the positioning frame 1 3 0 has an opening 1 3J, the positioning frame 1 3 0 of the opening 1 31 size Less than the size of the thin film substrate strip 丨 丨 〇, the positioning frame 130 is attached to the framed adhesive layers 121 in the positioning boundary area 丨 6 of the substrate 丨 丨 0 to enhance the thin film substrate strip 11 〇The flatness, because the softening temperature of the framed adhesive layer 121 is 100 ~ 125t.

1232527 五、發明說明（5) 框架1 3 0時，貼合溫度係在1 〇 〇〜i 2 5艽不會使該黏晶膠層 1 2 2反應而產生黏性，依本發明之另一具體實施例，如第& 圖所示，一定位框架230係具有至少一開口mi及至少一強 化條2 3 2，该強化條2 3 2係設於該定位框架2 3 〇之開口 2 3 1， 其係用以貼合於該基板條11 〇之封裝周邊區丨丨5之間，以增 進基板條11 0之平整度；請再參閱第2 D及3圖，貼合複數個 晶片140，每一晶片140係具有一主動面141及一背面142， 該些晶片1 4 0之主動面1 4 1係形成有複數個銲墊1 4 3 ,且該 些銲墊143係顯露於該薄膜基板條丨10之開孔113 ,該些晶 片1 4 0之主動面1 4 1係對應於該些黏晶區11 4而貼合於該黏 晶膠層1 2 2，使得該黏晶膠層1 2 2係外露於該些晶片1 4 0， 即在該薄膜基板條11 〇之封裝周邊區11 5之黏晶膠層1.2 2係 外露於該些晶片1 40，在貼合該些晶片1 40時，貼合溫度係 控制在150〜175 °C，以使該黏晶膠層122反應；請再參閱 第2E圖，以複數個電性連接裝置150電性連接該些晶片140 與該薄膜基板條1 4 0，在本實施例中，該些電性連接裝置 1 50係為銲線〔Bonding Wire〕，其係電性連接該些晶片 140之銲墊143與該薄膜基板條110之上表面111 ;請再參閱 第2F及3圖，形成一封膠體160，以保護該些晶片140與該 些電性連接裝置150，該封膠體160係覆蓋至在該薄膜基板 _ 條11 0之封裝周邊區11 8之黏晶膠層1 2 0，以結合該晶片1 4 0 與該黏晶膠層122，增進該封膠體1 60與該薄膜基板條11〇 之結合力；請再參閱第2G圖，植接複數個銲球170於該薄 膜基板條11 0之該上表面111。1232527 V. Description of the invention (5) When the frame is 130, the bonding temperature is 100 ~ i 2 5 艽. It will not cause the adhesive layer 1 2 2 to react and produce stickiness. According to another aspect of the present invention, In a specific embodiment, as shown in FIG. &Amp;, a positioning frame 230 has at least one opening mi and at least one reinforcing strip 2 3 2, and the reinforcing strip 2 3 2 is provided at the opening 2 3 of the positioning frame 2 3 〇 1. It is used to adhere to the package peripheral area 丨 丨 5 of the substrate strip 110 to improve the flatness of the substrate strip 110. Please refer to Figures 2D and 3 again to attach a plurality of wafers 140 Each wafer 140 has an active surface 141 and a back surface 142. The active surfaces 1 41 of the wafers 140 are formed with a plurality of pads 1 4 3, and the pads 143 are exposed on the film. In the opening 113 of the substrate strip 10, the active surfaces 1 4 1 of the wafers 140 are corresponding to the sticky crystal regions 11 4 and are attached to the sticky adhesive layer 1 2 2 so that the sticky adhesive layer 1 2 2 is exposed on the wafers 1 40, that is, the adhesive layer on the thin film substrate strip 11 0 in the packaging peripheral area 115. 1.2 2 is exposed on the wafers 1 40, and the wafers 1 are bonded. 40 hours The bonding temperature is controlled at 150 ~ 175 ° C to make the adhesive layer 122 react; please refer to FIG. 2E again, and electrically connect the wafers 140 and the thin film substrate strip 1 with a plurality of electrical connection devices 150. 40, in this embodiment, the electrical connection devices 150 are bonding wires [Bonding Wire], which are electrically connected to the pads 143 of the wafers 140 and the upper surface 111 of the thin film substrate strip 110; Please refer to FIGS. 2F and 3 again to form a colloid 160 to protect the chips 140 and the electrical connection devices 150. The encapsulant 160 covers the package peripheral area 11 on the thin film substrate _ strip 11 0 The adhesive layer 8 of 8 is bonded to the wafer 140 and the adhesive layer 122 to improve the bonding force between the sealing compound 160 and the thin film substrate strip 110; please refer to FIG. 2G again. A plurality of solder balls 170 are connected to the upper surface 111 of the thin film substrate strip 110.

第13頁 1232527 五、發明說明（6) 利用包含有該些貼框膠層1 2 1及該黏晶膠層1 2 2之貼合 膠120 —體貼設於該薄膜基板條丨丨〇之下表面112，該黏晶 膠層1 2 2係設於該薄膜基板條丨1 〇之黏晶區11 4與封裝周邊 區11 5，該些貼框膠層1 2 1係設於該薄膜基板條11 〇之定位 邊界區11 6，使該定位框架1 3 〇直接以貼設至該薄膜基板條 1 1 0之定位邊界區11 6之貼框膠層1 2 1與該薄膜基板條1丨〇貼 合’以取代習知之貼框膠帶，減少額外之機器設備投資， 此外’在封裝過程中，封裝機台〔圖未繪出〕係直接接觸 該定位框架130，而不會與該貼合膠12〇接觸，減少靜電產 生。 本發明之保護範圍當視 為準’任何熟知此項技藝者 圍内所作之任何變化與修改 後附之申請專利範圍所界定者 ’在不脫離本發明之精神和範 ’均屬於本發明之保護範圍。Page 13 1232527 V. Description of the invention (6) Using the adhesive 120 including the frame adhesive layer 1 2 1 and the sticky crystal adhesive layer 1 2 2-body attached to the film substrate strip 丨 丨 〇 On the surface 112, the adhesive layer 1 2 2 is disposed on the adhesive region 11 4 of the thin film substrate strip 1 10 and the package peripheral region 115, and the framed adhesive layer 1 2 1 is disposed on the thin film substrate strip. 11 〇 positioning boundary area 116, so that the positioning frame 1 3 〇 directly attached to the film substrate strip 1 1 10 positioning boundary area 1 16 of the frame adhesive layer 1 2 1 and the film substrate strip 1 丨 〇 "Lamination" to replace the conventional framed tape, reducing additional investment in machinery and equipment. In addition, during the packaging process, the packaging machine [not shown] directly contacts the positioning frame 130, and does not contact the positioning adhesive. 12 o contact, reduce static electricity. The scope of protection of the present invention shall be deemed to be 'defined by the scope of any patents attached to any changes and modifications made by those skilled in the art' without departing from the spirit and scope of the present invention. .

1232527 圖式簡單說明 【圖式簡單說明 第 圖 第2A至2G圖 第 圖 第 圖 第 圖 依據本發明之薄膜球格陣列封贴 . 丁〜对裝之製造 法，一薄膜基板條之上視示意圖· :依據本發明之薄膜球格陣列壯’ 卞封裝之製 法，該薄膜基板條在製造過鞋由—1化万 圖； τ之截面示意 ••依據本發明之薄膜球格陣列封裝之製4 法，在第一實施例中，一貼合m ^^方 m 〇膠貼合於該其 板條之下視示意圖； & A & :依據本發明之薄膜球格陣列封敦之製生 法，在第一實施例中，一定位框 意圖；及 卞之上視不 •依據本發明之薄膜球格陣列封裝之製皮 法，在第二實施例中，—定位 一 意圖。 I朱之上視不 元件符號簡單說明 11 0薄膜基板條 11 3開孔 11 6 定位邊界區 1 2 0 貼合膠 123開孔 1 3 0 定位框架 1 4 0晶片 111上表面 11 4黏晶區 11 7傳動孔 1 21貼框膠層 1 3 1 開口 141主動面 112下表面 11 5 封裝周邊區 Φ 1 2 2黏晶膠層 142背面1232527 Brief description of the drawings [Schematic illustrations of Figures 2A to 2G Figures Figures Figures and Figures Figure 3 shows the film ball grid array sealing according to the present invention. ·: According to the manufacturing method of the thin-film ball grid array according to the present invention, the thin-film substrate strip has been manufactured in accordance with the present invention. The cross-section of τ is schematic. In the first embodiment, a laminating m ^^ square m 〇 glue is attached to the bottom of the slat; a schematic view; & A &: the production method of the film ball grid array sealing according to the present invention In the first embodiment, a positioning frame is intended; and on top of that, the skinning method of the thin film ball grid array package according to the present invention is not used. In the second embodiment, a positioning is intended. I Zhu on the element symbol simply explained 11 0 thin film substrate strip 11 3 openings 11 6 positioning boundary area 1 2 0 laminating glue 123 openings 1 3 0 positioning frame 1 4 0 top surface of wafer 111 11 4 sticky crystal area 11 7 Drive hole 1 21 Framed adhesive layer 1 3 1 Opening 141 Active surface 112 Lower surface 11 5 Peripheral area of the package Φ 1 2 2 Backside of adhesive layer 142

1232527 圖式簡單說明 143 銲墊 1 5 0電性連接裝置 1 6 0 封膠體 1 7 0 鮮球 230 定位框架 231開口 232強化條 〇 I·· 第16頁1232527 Brief description of drawings 143 Solder pads 1 5 0 Electrical connection device 1 6 0 Sealing gel 1 7 0 Fresh ball 230 Positioning frame 231 opening 232 reinforcement strip 〇 I ·· Page 16

Claims (1)

12325271232527 【申請專利範圍】 包含有下列步 1、一種薄膜球格陣列封裝之製造方法 驟： 提供一薄膜基板條，該薄膜基板條係具有一上表面、 一下表面及至少一開孔，該薄膜基板條之該下表面係包 含有複數個黏晶區、複數個封裝周邊區及複數個定位邊 界區；[Scope of patent application] It includes the following steps 1. A method for manufacturing a thin film ball grid array package: Provide a thin film substrate strip, the thin film substrate strip has an upper surface, a lower surface and at least one opening, and the thin film substrate strip The lower surface system includes a plurality of sticky crystal regions, a plurality of packaging peripheral regions, and a plurality of positioning boundary regions; 貼合一貼合膠，該貼合膠係包含有複數個貼框膠層及 一黏晶膠層’該些貼框膠層及該黏晶膠層係一體貼設於 該溥膜基板條之該下表面，該些貼框膠層係設於該薄膜 基板條之定位邊界區，該黏晶膠層係設於該薄膜基板條 之黏晶區與封裝周邊區； 貼設一定位框架，該定位框架係具有一開口，該開口 之尺寸係小於該薄膜基板條之尺寸，該定位框架係貼合 於在該基板之定位邊界區之貼框膠層；及Laminating a laminating adhesive, the laminating adhesive system comprises a plurality of framing adhesive layers and a crystalline adhesive layer. The framing adhesive layers and the crystalline adhesive layer are integrally attached to the film substrate strip. On the lower surface, the frame-adhesive layers are disposed on the positioning boundary area of the thin-film substrate strip, and the die-attach adhesive layer is disposed on the thin-crystal substrate area and the package peripheral area of the thin-film substrate strip; The positioning frame has an opening, the size of the opening is smaller than the size of the film substrate strip, and the positioning frame is adhered to the frame adhesive layer in the positioning boundary area of the substrate; and 貼合複數個晶片，每一晶片係具有一主動面及一背 面，該些晶片之主動面係形成有複數個銲塾，該些銲塾 係顯露於該薄膜基板條之該開孔，該些晶片之主動面係 對應於該些黏晶區而貼合於該黏晶膠層，使得該黏晶膠 層係外露於該些晶片。 2、 如申請專利範圍第1項所述之薄膜球格陣列封裝之製 造方法，其中該些貼框膠層之軟化溫度係低於該黏晶膠 層之軟化溫度。 3、 如申請專利範圍第1項所述之薄膜球格陣列封裝之製A plurality of wafers are bonded, and each wafer has an active surface and a back surface. The active surfaces of the wafers are formed with a plurality of welding pads, which are exposed in the openings of the thin film substrate strip. The active surface of the wafer corresponds to the sticky crystal regions and is attached to the sticky adhesive layer, so that the sticky adhesive layer is exposed on the wafers. 2. The method for manufacturing a thin film ball grid array package as described in item 1 of the scope of the patent application, wherein the softening temperature of the framed adhesive layers is lower than the softening temperature of the sticky crystal adhesive layer. 3. The system of thin film ball grid array packaging as described in item 1 of the scope of patent application 第17頁 1232527Page 12 1232527 造方法 度相同 其中該些貼框膠層之厚度係與該黏晶膠層之厚 4、如申請專利範圍第丨項所述之薄膜球格陣列封 造方法，其中該黏晶膠層之厚度係不超過〇. 1 mm。 β、如申請專利範圍第丨項所述之薄膜球格陣列封裝 ΐ A f中該薄膜基板條係為厚度不超過〇· 2_之薄 膜薄膜基板條。 6、如申請專利範圍第丨項所述之薄膜球格陣列封裝之 造方法·，其中該貼合膠係全面覆蓋該薄膜基板條之 面。 ” 衣 7、 如申請專利範圍第1項所述之薄膜球格陣列封裝之製 造方法’该黏晶膠層係具有至少一開孔，該黏晶膠芦之 該開孔之尺寸係等於該基板之該開孔之尺寸。 /曰 8、 如申請專利範圍第丨項所述之薄膜球格陣列封裝之製 造方法，其中該黏晶膠層係為一彈性膠層。 9、 如申請專利範圍第1項所述之薄膜球格陣列封裝之製 造方法，其中該定位框架係具有至少一強化條，其係役 於該定位框架之該開口。The manufacturing method is the same, wherein the thickness of the frame adhesive layer is the same as the thickness of the sticky crystal adhesive layer. 4. The thin film ball grid array encapsulation method described in item 丨 of the patent application scope, wherein the thickness of the sticky adhesive layer The system does not exceed 0.1 mm. β. According to the thin film ball grid array package ΐ A f described in the scope of the patent application, the thin film substrate strip is a thin film substrate strip having a thickness of not more than 0.2 mm. 6. The manufacturing method of the thin film ball grid array package as described in item 丨 of the patent application scope, wherein the laminating adhesive completely covers the surface of the thin film substrate strip. 7. The manufacturing method of the thin film ball grid array package described in item 1 of the scope of the patent application, 'The adhesive layer of glue has at least one opening, and the size of the opening of the adhesive glue is equal to the substrate The size of the opening. / Said 8. The method for manufacturing a thin film ball grid array package as described in item 丨 of the patent application range, wherein the adhesive layer is an elastic glue layer. The manufacturing method of the thin film ball grid array package according to item 1, wherein the positioning frame has at least one reinforcing strip, which is used in the opening of the positioning frame. 1 0、如申請專利範圍第1項所述之薄膜球格陣列封襄之製 造方法，於貼合該些晶片之步驟之後，其另包含之步 驟有：以複數個電性連接裝置電性連接該些晶片與該 薄膜基板條。 ' 1 1、如申請專利範圍第1項所述之薄膜球格陣列封裝之製 造方法，於貼合該些晶片之步驟之後，其另包含&之步10. The method for manufacturing a thin-film ball grid array enclosure as described in item 1 of the scope of patent application, after the steps of bonding the wafers, it further includes the steps of: electrically connecting with a plurality of electrical connection devices The wafers and the thin film substrate strip. '1 1. According to the manufacturing method of the thin film ball grid array package described in item 1 of the scope of patent application, after the step of bonding the wafers, it further includes the & step 第18頁Page 18 1232527_ 六、申請專利範圍 驟有：形成一封膠體，該封膠體係覆蓋至在該薄膜基 板條之封裝周邊區之黏晶膠層，以結合該晶片與該黏 晶膠層。 1 2、如申請專利範圍第1項所述之薄膜球格陣列封裝之製 造方法，於形成該些封膠體之步驟之後，其另包含之 步驟有：植接複數個銲球於該薄膜基板條之該上表 面。1232527_ VI. The scope of patent application is as follows: forming a colloid, the sealing system covers the adhesive layer on the peripheral area of the package of the thin film substrate, so as to combine the chip and the adhesive layer. 1 2. According to the manufacturing method of the thin film ball grid array package described in item 1 of the scope of the patent application, after the steps of forming the sealing gels, the additional steps include: implanting a plurality of solder balls on the thin film substrate strip On the top surface. 第19頁Page 19
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