TW200524060A - Method for manufacturing film ball grid array package - Google Patents

Method for manufacturing film ball grid array package Download PDF

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Publication number
TW200524060A
TW200524060A TW093100608A TW93100608A TW200524060A TW 200524060 A TW200524060 A TW 200524060A TW 093100608 A TW093100608 A TW 093100608A TW 93100608 A TW93100608 A TW 93100608A TW 200524060 A TW200524060 A TW 200524060A
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TW
Taiwan
Prior art keywords
thin film
adhesive layer
substrate strip
film substrate
patent application
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Application number
TW093100608A
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Chinese (zh)
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TWI232527B (en
Inventor
Kuo-Yuan Lee
Kuang-Chi Chao
Cheng-Tai Chen
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Walton Advanced Eng Inc
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Priority to TW093100608A priority Critical patent/TWI232527B/en
Application granted granted Critical
Publication of TWI232527B publication Critical patent/TWI232527B/en
Publication of TW200524060A publication Critical patent/TW200524060A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

A method for manufacturing film ball grid array is disclosed. A film substrate strip attaches an attaching layer. An lower surface of the film substrate strip is comprised a plurality of die-attaching areas, a plurality of packaging surrounding areas and a plurality of orientating areas. The attaching layer is comprised a plurality of frame-attaching tapes and a die-attaching tape. The frame-attaching tapes and the die-attaching tape is integrated with attaching to the lower surface of the film substrate strip, wherein the frame-attaching tapes is disposed on the orientating areas of the film substrate strip, and the die-attaching tape is disposed on the die-attaching areas and packaging surrounding areas of the film substrate strip. An orientating frame attaches on the attaching layer which parts are on the orientating areas of the film substrate strip for maintaining film substrate strip is flatness.

Description

200524060 五、發明說明（1) 【發明所屬之技術領域 係右ir月：於—種球格陣列封裝之製造方法，特別 一 ？薄膜球格陣列封裝之製造方法。 【先刖技術】 封裝技術〔Ball Grid Array，bga〕為一 成熟之半導體封裝之製造方法，然而一般球格 =! 2所使用之基板材質為BT、FR 40R 5之硬板，其 又”’、.25mm以上，故該基板在封裝過程中，不會有搬 匕f Ϊ ihandU〕之問題’然而’在利用薄膜〔f ilm〕 二=為球格陣列封裝之基板時，由於該薄膜基板之厚度 係不超過0.2随，在封裝過程中會有搬運、處理之問題。 ㈣二知之薄.膜球格陣列封裝之製造方法，其係將厚度不 薄膜基板條貼合於一定位框架，利用該定位 ‘：裝過ί :ί ί板條之平整度，用以避免該薄膜基板條 在封t過权中撓曲、變形，產生搬 續後續之黏晶、打缘、封腺望4+=處理之問74再繼 了踝封膠專封裝製程，而該薄膜基板條 ,^ :位框杀之貼合方法係先將該薄膜基板條置於該定位 ^上’再利用複數個貼框膠帶將該薄膜基板條之貼 ,於該定位框架，不但需要再投資額外之機器設備 膠！貼合該基板條與該定位框架，該些貼框膠帶 ，2露’在封裝過程中該些貼框膠帶容易與機台摩擦而 …ί二造成產品損# ’此外，因為該些框膠帶並非->成，在該薄膜基板條與該定位框架之貼合過程中， 些框膠帶會因拉開的力量不同’而使該薄膜基板條與該； 五、發明說明（2) 位框架貼合不良。 【發明内容】 列封裝 晶膠層 晶膠層 貼框膠 架貼設 ，減少 本發明之主要目的係在於提供一種薄膜球格陣 之製造方法，利用一包含有複數個貼框膠層及一黏 之貼合膠一體貼没於一薄膜基板條之下表面，該黏 係設於該薄膜基板條之黏晶區與封裝周邊區，該些 層係設於該薄膜基板條之定位邊界區，使一定位框 於定位邊界區之黏晶膠層’以取代習知之貼框膠帶 額外之機器設備投資。200524060 V. Description of the invention (1) [Technical field to which the invention belongs] Right month: a manufacturing method of a ball grid array package, particularly one? Manufacturing method of thin film ball grid array package. [Advanced technology] Packaging technology [Ball Grid Array, bga] is a mature semiconductor package manufacturing method, but the general ball grid =! 2 The substrate material used is BT, FR 40R 5 rigid board, which is "' .25mm or more, so the substrate will not have the problem of f Ϊ ihandU during the packaging process. However, when using thin film [f ilm] 2 = for the substrate of the ball grid array package, due to the thin film substrate The thickness is not more than 0.2, and there will be problems in handling and handling during the packaging process. The second is known as thin. The manufacturing method of the film ball grid array package is to attach a thin film substrate strip to a positioning frame and use the Positioning: Installed ί: ί ί The flatness of the slat, to avoid the film substrate strip from flexing and deforming during the sealing process, resulting in subsequent sticking crystals, edges, and glands 4 + = The processing problem 74 is followed by the ankle sealant special packaging process, and the film substrate strip, ^: The method of bit frame killing is to first place the film substrate strip on the positioning ^, and then use a plurality of framed tape Attach the film substrate strip to the positioning frame. Invest in additional machine and equipment adhesives! Laminate the substrate strip and the positioning frame, the framed tape, and expose the framed tape during the packaging process, which is easy to rub against the machine and cause product damage. In addition, because the frame tapes are not-> during the bonding process of the film substrate strip and the positioning frame, the frame tapes will be different from each other due to the force of pulling apart; Description of the invention (2) Poor adhesion of the bit frame. [Summary] The main purpose of reducing the present invention is to provide a method for manufacturing a thin film ball grid array by using a Containing a plurality of frame adhesive layers and a sticky adhesive glue are integrally attached to the lower surface of a thin film substrate strip, and the adhesive system is provided in the sticky crystal region and the package peripheral region of the thin film substrate strip. At the positioning boundary area of the thin film substrate strip, a positioning frame is formed at the positioning boundary area of the crystalline adhesive layer to replace the conventional additional investment in machinery and equipment of framed tape.

本發明之次一目的係在於提供一種薄膜球格陣列封裝 之製造方法’利用一包含有複數個貼框膠層及一黏晶膠層 之貼合膠一體貼設於一薄.膜基板條之下表面，該些貼框膠 層係3又於该薄膜基板條與一定位框架之間，以避免該些貼 框膠層與封裝機台直接接觸，減少靜電產生。 a 依本發明之薄膜球格陣列封裝之製造方法包含有下列 步驟·首先，提供一薄膜基板條，該薄膜基板條係具有一 上表面]一下表面及至少一開孔，該薄膜基板條之該下表 面係包含有複數個黏晶區，複數個封裝周邊區及複數個定 位邊界區，之後，貼合一貼合膠，該貼合膠係包含有複數 個貼框膠層及一黏晶膠層，該些貼框膠層及該黏晶膠層係 叹於該薄膜基板條之該下表面，該些貼框膠層係設 於4 4骐基板條之定位邊界區，該黏晶膠層係設於該薄膜 基，條之點晶區與封裝周邊區；之後，貼設一定位框架， 亥疋位框木係具有一開口，該開口之尺寸係小於該薄膜基A second object of the present invention is to provide a method for manufacturing a thin-film ball grid array package. 'A laminating adhesive including a plurality of frame adhesive layers and a crystal-adhesive adhesive layer is integrally attached to a thin film substrate. On the lower surface, the frame-adhesive layers 3 are between the film substrate strip and a positioning frame to avoid direct contact between the frame-adhesive layers and the packaging machine and reduce static electricity. a The manufacturing method of the thin film ball grid array package according to the present invention includes the following steps. First, a thin film substrate strip is provided, the thin film substrate strip has an upper surface] a lower surface and at least one opening. The lower surface system includes a plurality of adhesive regions, a plurality of packaging peripheral regions, and a plurality of positioning boundary regions. Then, an adhesive is applied, and the adhesive system includes a plurality of frame adhesive layers and a crystal adhesive. Layer, the frame-adhesive layer and the sticky crystal adhesive layer are sighed on the lower surface of the film substrate strip, and the frame-adhesive layers are provided at the positioning boundary area of the substrate strip, and the sticky crystal adhesive layer It is set on the film base, the crystalline region of the strip and the peripheral area of the package; after that, a positioning frame is attached, and the frame of the helium bit has an opening, and the size of the opening is smaller than the film base.

第10頁 200524060Page 10 200524060

五、發明說明（3) 板條之尺寸，該定位框架係貼合於在該基板之定位邊界區 之黏晶膠層；之後，貼合複數個晶片，每一晶片係具有一 主動面及一背面，該些晶片之主動面係形成有複數個銲 塾’且該些銲墊係顯露於該開孔，該些晶片之主動面係對 應於該些黏晶區而貼合於該黏晶膠層，使得該黏晶膠層係 外露於該些晶片；之後，再將該些晶片以複數個電性連接 裝置電性連接該些晶片與該薄膜基板條；以及形成一封膠 體保護該些晶片、該些電性連接裝置。 【實施方式】 參閱所附圖式，本發明將列舉以下之實施例說明。 依本發明之一具體實施例，一種薄膜·球格陣列封裝之❿ 製造方法如下所述，請參閱第i及以圖，第i圖係為該薄膜 球格陣列封裝之製造方法，提供一薄膜基板條丨丨〇，該薄 膜基板條110之上視示意圖，第2A圖係為該薄膜基板條110 之載面示意圖，該薄膜基板條丨丨〇之材質係為聚亞醢胺 〔Polyimide，PI〕，其寬度一般係為35mm、48mm 或 70mm ’而其厚度係為不超過〇· 2mnl，該薄膜基板條no係具 有一上表面111、一下表面11 2及至少一開孔1丨3，該薄膜 基板條11 0之下表面11 2係包含有複數個黏晶區11 4，複數 個封裝周邊區11 5及複數個定位邊界區11 6，該些定位邊界# 區11 6形成有複數個傳動孔11 7〔 Sprocket〕；請再參閱第 2B及3圖，貼合一貼合膠120，第2B圖係為該貼合膠120貼 合於該基板條11 〇之截面示意圖，第3圖係為該貼合膠12 〇 貼合於該基板條1 10之下視示意圖，該貼合膠12〇係包含有V. Description of the invention (3) The size of the slat, the positioning frame is attached to the adhesive layer of adhesive on the positioning boundary area of the substrate; after that, a plurality of wafers are attached, and each wafer has an active surface and a On the back side, the active surfaces of the wafers are formed with a plurality of welding pads, and the pads are exposed in the openings. The active surfaces of the wafers are corresponding to the sticky crystal regions and are attached to the sticky adhesive. Layer, so that the adhesive layer is exposed on the wafers; then, the wafers are electrically connected to the wafers and the thin film substrate strip by a plurality of electrical connection devices; and a colloid is formed to protect the wafers. 、 These electrical connection devices. [Embodiment] With reference to the drawings, the present invention will be described by the following embodiments. According to a specific embodiment of the present invention, a method for manufacturing a thin film ball grid array package is described below. Please refer to FIG. I and the figure, which is a method for manufacturing the thin film ball grid array package, and provides a thin film. Substrate strip 丨 丨 〇, a schematic view from above of the thin film substrate strip 110, FIG. 2A is a schematic view of a carrying surface of the thin film substrate strip 110, and the material of the thin film substrate strip 丨 丨 〇 is polyimide [PI ], Its width is generally 35mm, 48mm or 70mm 'and its thickness is not more than 0.2ml. The thin film substrate strip no has an upper surface 111, a lower surface 11 2 and at least one opening 1 丨 3, the The lower surface 11 2 of the thin film substrate strip 110 includes a plurality of sticky crystal regions 11 4, a plurality of packaging peripheral regions 115, and a plurality of positioning boundary regions 11 6. These positioning boundary # regions 11 6 form a plurality of transmissions. Hole 11 7 [Sprocket]; please refer to Figs. 2B and 3 again, and apply a laminating adhesive 120. Fig. 2B is a schematic cross-sectional view of the laminating adhesive 120 attached to the substrate strip 110. Fig. 3 It is a schematic view of the laminating adhesive 12 attached to the substrate strip 1 10, Bonded with glue based 12〇

第11頁 200524060 五、發明說明（4) 複數個貼框膠層1 2 1及一黏晶膠層1 2 2，該些貼框膠層1 2 1 及該黏晶膠層1 2 2係先塗施於一承載薄膜〔圖未繪出〕， 再一體轉貼於該薄膜基板條11 〇之下表面11 2，即該些貼框 膠層1 2 1及該黏晶膠層1 2 2係一體貼設於該薄膜基板條11 0 之下表面11 2，該貼合膠1 2 〇係可全面覆蓋該薄膜基板條Page 11 200524060 V. Description of the invention (4) A plurality of frame adhesive layers 1 2 1 and a crystal adhesive layer 1 2 2, the frame adhesive layers 1 2 1 and the crystal adhesive layers 1 2 2 are first It is applied to a carrier film (not shown in the figure), and then transferred to the lower surface 11 2 of the film substrate strip 11 2 as a whole, that is, the framed adhesive layers 1 2 1 and the sticky crystal adhesive layer 1 2 2 It is thoughtfully arranged on the lower surface 11 2 of the thin film substrate strip 110, and the bonding glue 12 2 can completely cover the thin film substrate strip

1 1 0之下表面1 1 1或僅留下該薄膜基板條1 1 〇之傳動孔1 1 7不 覆蓋’其中該些貼框膠層121係設於該薄膜基板條110之定 位邊界區116，該黏晶膠層122係設於該薄膜基板條110之 黏晶區11 4與封裝周邊區11 5，該些貼框膠層1 21之軟化溫 度係低於該黏晶膠層1 2 2之軟化溫度，在本實施例中，該 些貼框膠層1 2 1之軟化溫度係為1 〇 〇〜1 2 5 °C，該黏晶膠層 122之軟化溫度係為150〜175 °C，該黏晶膠層122係為一 彈性膠層〔elastomer〕，其係具有至少一開孔丨23，且該 黏晶膠層1 2 2之開孔1 2 3尺寸係等於該基板1 1 〇之開孔11 3， s玄黏晶膠層1 2 2之厚度係不超過〇 · 1 m m，較佳地，該些貼框 勝層121之厚度係與該黏晶膠層122之厚度相同；請再參閱 第2 C、3及4圖，第2 C圖係為該薄膜球格陣列封裝之製造方 法中，貼設一定位框架1 30時，該定位框架丨3〇與該基板條 110之截面示意圖，第4圖係為該定位框架13〇之上視示意 圖，鑲疋位框架1 3 0係具有一開口 1 31，該定位框架丨3 〇之 該開口131之尺寸係小於該薄膜基板條11〇之尺寸，該定位 框架1 30係貼合於在該基板丨丨〇之定位邊界區丨丨6之該些貼 框膠層121，以增進該薄膜基板條11〇之平整度，由於^該些 貼框膠層121之軟化溫度係為1〇〇〜125t，在貼設該定位The lower surface of 1 1 0 1 1 1 or only the transmission holes 1 1 7 of the thin film substrate strip 1 1 0 are left uncovered 'wherein the framed adhesive layers 121 are provided in the positioning boundary region 116 of the thin film substrate strip 110 The adhesive layer 122 is disposed in the adhesive region 11 4 and the package peripheral region 115 of the thin film substrate strip 110. The softening temperature of the frame adhesive layers 1 21 is lower than the adhesive layer 1 2 2 In this embodiment, the softening temperature of the framed adhesive layers 1 2 1 is 100 ~ 125 ° C, and the softening temperature of the viscous adhesive layer 122 is 150 ~ 175 ° C. The viscose adhesive layer 122 is an elastic adhesive layer [elastomer], which has at least one opening 丨 23, and the size of the openings 1 2 3 of the viscous adhesive layer 1 2 2 is equal to the substrate 1 1 〇 The thickness of the openings 11 3, s xuan adhesive layer 1 2 2 is not more than 0.1 mm, preferably, the thickness of the framed win layer 121 is the same as the thickness of the adhesive layer 122; Please refer to Figs. 2C, 3, and 4 again. Fig. 2C is the method for manufacturing the thin film ball grid array package. When a positioning frame 130 is attached, the positioning frame 315 and the substrate strip 110 Schematic section Fig. 4 is a schematic top view of the positioning frame 13o. The inlaid position frame 130 has an opening 1 31, and the size of the opening 131 of the positioning frame 315 is smaller than the film substrate strip 11o. Size, the positioning frame 1 30 is attached to the frame-adhesive layers 121 on the positioning boundary area 丨 6 of the substrate 丨 丨 0 to improve the flatness of the thin-film substrate strip 110. The softening temperature of the frame-adhesive layer 121 is 100 ~ 125t.

第12頁 200524060Page 12 200524060

1木130時’貼合溫度係在i 〇〇〜i 25 ^不會使該黏晶膠層 122反應而產生黏性，依本發明之另一具體實施例，如第5 圖所示，一定位框架230係具有至少一開口231及至少一強 化條2 3 2 4強化條2 3 2係設於該定位框架2 3 〇之開口 2 3 1，. 其係用以貼合於該基板條110之封裝周邊區115之間，以增 進基板條110之平整度；請再參閱第2〇及3圖，貼合複數個 ，片140，每一晶片14〇係具有一主動面141及一背面142， 遽些晶片1 4 0之主動面1 4 1係形成有複數個銲墊η 3 ,且該 些知=·塾1 4 3係顯露於該薄膜基板條1 1 〇之開孔11 3 ,該些晶 片1 4 0之主動面1 41係對應於該些黏晶區丨丨4而貼合於該黏《 曰曰膠層1 2 2 ,使得該黏晶膠層1 2 2係外露於該些晶片1 4 0， 即在該薄膜基板條11 〇之封装周邊區丨丨5之黏晶膠層丨2 2係 外露於該些晶片1 4 0，在貼合該些晶片1 4 〇時，貼合溫度係 控制在1 5 0〜1 7 5 °C，以使該黏晶膠層1 2 2反應；請再參閱 第2 E圖’以複數個電性連接裝置1 5 〇電性連接該些晶片1 4 0 與該薄膜基板條1 4 0，在本實施例中，該些電性連接裝置 1 50係為銲線〔Bonding Wire〕，其係電性連接該些晶片 140之知塾143與該薄膜基板條110之上表面ill ;請再參閱 第2F及3圖，形成一封膠體160，以保護該些晶片140與該 些電性連接裝置1 5 0，該封膠體1 6 0係覆蓋至在該薄膜基板 _ 條1 1 0之封裝周邊區11 8之黏晶膠層1 2 0，以結合該晶片1 4 0 與該黏晶膠層1 2 2，增進該封膠體1 6 0與該薄膜基板條11 〇 之結合力；請再參閱第2G圖，植接複數個銲球170於該薄 膜基板條1 1 〇之該上表面11 1。At 130 o'clock, the bonding temperature is between i 〇〇 ～ i 25 ^ does not cause the viscous adhesive layer 122 to react and produce tackiness. According to another specific embodiment of the present invention, as shown in FIG. 5, one The positioning frame 230 has at least one opening 231 and at least one reinforcing strip 2 3 2 4 and the reinforcing strip 2 3 2 is an opening 2 3 1 provided in the positioning frame 2 3 0. It is used to be attached to the substrate strip 110 Between the package peripheral regions 115 to improve the flatness of the substrate strip 110; please refer to FIGS. 20 and 3 again, and attach a plurality of wafers 140. Each wafer 14 has an active surface 141 and a back surface 142. The active surfaces 1 4 1 of these wafers 140 are formed with a plurality of pads η 3, and the knowledge = · 1 4 3 is exposed in the openings 11 3 of the film substrate strip 1 1 0, the The active surfaces 1 41 of the wafers 1 40 correspond to the sticky crystal regions 丨 4 and are adhered to the sticky layer, so that the sticky adhesive layer 1 2 2 is exposed to the sticky layers. The wafer 1 40, that is, the adhesive layer of the wafer 5 in the peripheral area of the package of the thin-film substrate strip 1 10, 2 2 is exposed on the wafers 1 40, and when the wafers 1 4 0 are bonded, the The closing temperature is controlled at 1 5 0 ~ 1 7 5 ° C to make the adhesive layer 1 2 2 react; please refer to FIG. 2E again to electrically connect the chips 1 4 0 and the film with a plurality of electrical connection devices 1 5 0 Substrate strip 1 40. In this embodiment, the electrical connection devices 150 are bonding wires, which are electrically connected to the chip 143 and the thin film substrate strip 110. The surface is ill; please refer to FIGS. 2F and 3 again to form a colloid 160 to protect the chips 140 and the electrical connection devices 150. The encapsulant 16 is covered to the film substrate. The 1 10 adhesive layer 1 2 0 of the packaging peripheral area 11 8 is used to combine the wafer 1 4 0 and the adhesive layer 1 2 2 to enhance the sealing compound 1 60 and the thin film substrate strip 11. Bonding force; referring to FIG. 2G again, a plurality of solder balls 170 are implanted on the upper surface 11 1 of the thin film substrate strip 1 1 0.

第13頁 200524060 _______ 五、發明說明（6) 利用包含有該些貼框膠層1 2 1及該黏晶膠層1 2 2之貼合 膠1 2 0 —體貼設於該薄膜基板條1 1 〇之下表面1 1 2，該黏晶 膠層1 2 2係設於該薄膜基板條1 1 〇之黏晶區11 4與封裝周邊 區1 1 5，該些貼框膠層1 2 1係設於該薄膜基板條1 1 〇之定位 邊界區1 1 6，使該定位框架1 30直接以貼設至該薄膜基板條 11 0之定位邊界區11 6之貼框膠層1 2 1與該薄膜基板條11 〇貼 合，以取代習知之貼框膠帶，減少額外之機器設備投資， 此外’在封裝過程中，封裝機台〔圖未繪出〕係直接接觸 該定位框架130，而不會與該貼合膠120接觸，減少靜電產 生。 、本發明之保護範圍當視後附之申請專利範圍所界定者 為準任何熟知此項技藝者，在不脫離本發明之精神和範 圍内所作之任何變化與修改，均屬於本發明之保護範圍。Page 13 200524060 _______ V. Description of the invention (6) Use of a laminating adhesive 1 2 1 containing the framed adhesive layer 1 2 1 and the sticky crystal adhesive layer 1 2 2 — body-mounted on the film substrate strip 1 1 The lower surface 1 12 is formed by the adhesive layer 12 of the thin film substrate strip 1 4 and the peripheral area 1 1 5 of the film substrate strip 1 2. The frame adhesive layers 1 2 1 are The positioning boundary area 1 1 6 of the thin film substrate strip 1 1 10 is provided, so that the positioning frame 1 30 is directly attached to the positioning adhesive area 1 16 of the thin film substrate strip 1 10 and the frame adhesive layer 1 2 1 and the The film substrate strip 11 is laminated to replace the conventional framing tape, reducing additional investment in machinery and equipment. In addition, during the packaging process, the packaging machine [not shown] directly contacts the positioning frame 130 without It is in contact with the adhesive glue 120 to reduce static electricity. 2. The protection scope of the present invention shall be determined by the scope of the appended patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. .

200524060 圖式簡單說明200524060 Schematic description

【圖式簡單說明】 第1 圖 第2A至2G圖 依據本發明之薄膜球格陣 法，一薄膜基板條之上視 依據本發明之薄膜球袼陣 法’该薄膜基板條在製造 圖； 列封裝之製造方 示意圖； 列封裝之製造方 過程中之截面示意 第 第 圖：依據本發明之薄膜球格 法，在第一實施例中， 板條之下視示意圖； 圖··依據本發明之薄膜球格 法，在第一實施例中， 意圖；及 陣列封裝之製造方 一貼合膠貼合於該基 陣列封裝之製造方 一定位框架之上視示[Brief description of the drawings] Figure 1 and Figures 2A to 2G. According to the thin film ball grid method of the present invention, a thin film substrate strip is viewed from above according to the thin film ball grid array method of the present invention. Schematic diagram of the manufacturer of the package; Schematic diagram of the cross-section during the process of manufacturing the package. Figure: The film ball grid method according to the present invention. In the first embodiment, a schematic view of the lower side of the slat; The thin film ball grid method, in the first embodiment, is intended; and the manufacturing method of the array package, an adhesive, is bonded to the manufacturing method of the base array package, and is positioned on the positioning frame.

第 圖：依據本發明之薄膜球格陣 法’在第二實施例中，一 意圖。 列封裝之製造方 定位框架之上視示 元件符號簡單說明 11 0薄膜基板條 11 3開孔 11 6 定位邊界區 120貼合膠 123開孔 1 3 0 定位框架 140晶片 111上表面 11 4黏晶區 11 7傳動孔 1 2 1貼框膠層 1 3 1 開口 1 4 1主動面 112下表面 11 5封裝周邊區 1 2 2黏晶膠層 142背面 200524060 圖式簡單說明 1 4 3 銲墊 150電性連接裝置 1 6 0封膠體 1 7 0 銲球 2 3 0 定位框架 2 3 1 開口 2 3 2 強化條 1111 第16頁Figure: The thin film ball grid method according to the present invention 'In the second embodiment, an idea is provided. Simple description of the components shown on the positioning frame of the packaging side of the package. 11 0 Thin film substrate strips 11 3 Openings 11 6 Positioning boundary area 120 Laminating adhesive 123 Openings 1 3 0 Positioning frame 140 Upper surface of wafer 111 11 4 Sticky crystals Area 11 7 Transmission hole 1 2 1 Framed adhesive layer 1 3 1 Opening 1 4 1 Active surface 112 Lower surface 11 5 Encapsulation peripheral area 1 2 2 Crystalline adhesive layer 142 Back 200524060 Illustration of simple illustration 1 4 3 Pad 150 Sexual connection device 1 6 0 Sealing gel 1 7 0 Solder ball 2 3 0 Positioning frame 2 3 1 Opening 2 3 2 Reinforcing strip 1111 Page 16

Claims (1)

200524060 六、申請專利範圍 【申請專利範圍】 1、 一種薄膜球格陣列封裝之製造方法，包含有下列步 驟： &供一清膜基板條’或薄膜基板條係具有一上表面、 一下表面及至少一開孔，該薄膜基板條之該下表面係包 含有複數個黏晶區、极數個封裝周邊區及複數個定位邊 界區； 貼合一貼合膠，該貼合膠係包含有複數個貼框膠層及 一黏晶膠層，該些貼框膠層及該黏晶膠層係一體貼設於 該薄膜基板條之該下表面，該些貼框膠層係設於該薄膜 基板條之疋位邊界區’該黏晶膠層係設於該薄膜基板條 之黏晶區與封裝周邊區； 貼設一定位框架，該定位框架係具有一開口，該開口 之尺寸係小於該薄膜基板條之尺寸，該定位框架係貼合 於在該基板之定位邊界區之貼框膠層；及 貼合複數個晶片，每一晶片係具有一主動面及一背 面，該些晶片之主動面係形成有複數個銲墊，該些銲墊 係顯露於該薄膜基板條之該開孔，該些晶片之主動面係 對應於該些黏晶區而貼合於該黏晶膠層，使得該黏晶膠 層係外露於該些晶片。 Μ 2、 如申請專利範圍第1項所述之薄膜球格陣列封裝之製 造方法’其中該些貼框膠層之軟化溫度係低於該黏晶膠 層之軟化溫度。 θθ 3、 如申請專利範圍第1項所述之薄膜球格陣列封裝之製200524060 VI. Scope of patent application [Scope of patent application] 1. A method for manufacturing a thin film ball grid array package, including the following steps: & for a clear film substrate strip 'or a thin film substrate strip has an upper surface, a lower surface and At least one opening, the lower surface of the thin film substrate strip includes a plurality of sticky crystal regions, a plurality of packaging peripheral regions, and a plurality of positioning boundary regions; a laminating adhesive, the laminating adhesive comprises a plurality of A frame adhesive layer and a crystal adhesive layer, the frame adhesive layer and the crystal adhesive layer are integrally attached to the lower surface of the film substrate strip, and the frame adhesive layers are disposed on the film substrate The boundary position of the stripe is' the sticky crystal adhesive layer is provided on the sticky crystal region of the thin film substrate strip and the peripheral area of the package; a positioning frame is attached, the positioning frame has an opening, and the size of the opening is smaller than the film The size of the substrate strip, the positioning frame is attached to the frame adhesive layer in the positioning boundary area of the substrate; and a plurality of wafers, each wafer has an active surface and a back surface, the active surfaces of the wafers Line formation There are a plurality of bonding pads, the bonding pads are exposed in the openings of the thin film substrate strip, and the active surfaces of the wafers correspond to the sticky crystal regions and are attached to the sticky crystal adhesive layer, so that the sticky crystals The glue layer is exposed on the wafers. M 2. The manufacturing method of the thin-film ball grid array package as described in item 1 of the scope of the patent application, wherein the softening temperature of the framed adhesive layers is lower than the softening temperature of the viscous adhesive layer. θθ 3, the manufacturing system of the thin film ball grid array package as described in item 1 of the scope of patent application 200524060200524060 六、申請專利範圍 造方法，其中該些貼框#層之厚度係與該黏晶膠層之厚 度相同。 4、 如申請專利範圍第1頊所述之薄膜球格陣列封裝.之製 造方法，其中該黏晶膠層之厚度係不超過0· 1 mm。 5、 如申請專利範圍第1項所述之薄膜球格陣列封裝之製 造方法，其中該薄膜基板條係為厚度不超過0· 2mm之薄 膜薄膜基板條。 6、如申請專利範圍第1項所述之薄膜球格陣列封裝之製 造方法，其中該貼合膠係全面覆蓋該薄膜基板條之下表 面0 7、 如申請專利範圍第1項所述之薄膜球格陣列封裂之製 造方法，該黏晶膠層係具有至少一開孔，該黏晶膠層之 該開孔之尺寸係等於該基板之該開孔之尺寸。 /曰 8、 如申請專利範圍第1項所述之薄膜球格陣列封裝之製 造方法，其中該黏晶膠層係為一彈性膠層。 9、 如申請專利範圍第1項所述之薄膜球格陣列封| 造方法，其中該定位框架係具有至少一強化條，t μ 於該定位框架之該開口。 ' 、係设 1 0、如申請專利範圍第1項所述之薄膜球格陣列 造方法，於貼合該些晶片之步驟之後，其另勺’人瑕之製 驟有：以複數個電性連接裝置電性連接該此^ 3之步 薄膜基板條。 —曰曰片與該 造 如申請專利範圍第1項所述之薄膜与 方法’於貼合該些晶片之步驟之後 再另包含 11 200524060_ 六、申請專利範圍 驟有：形成一封膠體，該封膠體係覆蓋至在該薄膜基 板條之封裝周邊區之黏晶膠層，以結合該晶片與該黏 晶膠層。 1 2、如申請專利範圍第1項所述之薄膜球格陣列封裝之製 造方法，於形成該些封膠體之步驟之後，其另包含之 步驟有：植接複數個銲球於該薄膜基板條之該上表 面。 #6. Scope of Patent Application The manufacturing method, wherein the thickness of the frame # layers is the same as the thickness of the sticky crystal adhesive layer. 4. The manufacturing method of the thin film ball grid array package as described in the first patent application scope, wherein the thickness of the adhesive layer is not more than 0.1 mm. 5. The manufacturing method of the thin film ball grid array package according to item 1 of the scope of the patent application, wherein the thin film substrate strip is a thin film thin film substrate strip having a thickness not exceeding 0.2 mm. 6. The manufacturing method of the thin film ball grid array package according to item 1 of the scope of patent application, wherein the bonding adhesive comprehensively covers the lower surface of the thin film substrate strip 0 7. The thin film as described in item 1 of the scope of patent application In the manufacturing method of ball grid array cracking, the adhesive layer has at least one opening, and the size of the opening of the adhesive layer is equal to the size of the opening of the substrate. 8. The method for manufacturing a thin film ball grid array package as described in item 1 of the scope of the patent application, wherein the adhesive layer is an elastic adhesive layer. 9. The thin film ball grid array sealing method described in item 1 of the scope of patent application, wherein the positioning frame has at least one reinforcing strip, t μ is at the opening of the positioning frame. 'It is set to 10, the thin film ball grid array manufacturing method described in item 1 of the scope of the patent application, after the steps of bonding the wafers, the other steps of the human defect are: The connecting device is electrically connected to the thin film substrate strip. — The film and the method described in item 1 of the scope of the patent application, and the film and method 'are included after the step of bonding the wafers 11 200524060_ 6. The scope of the patent application includes: forming a colloid, the seal The adhesive system covers the adhesive layer on the peripheral area of the package of the thin film substrate strip to combine the wafer and the adhesive layer. 1 2. According to the manufacturing method of the thin film ball grid array package described in item 1 of the scope of the patent application, after the steps of forming the sealing gels, the additional steps include: implanting a plurality of solder balls on the thin film substrate strip On the top surface. # 第19頁Page 19
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