JP4033780B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP4033780B2
JP4033780B2 JP2003032638A JP2003032638A JP4033780B2 JP 4033780 B2 JP4033780 B2 JP 4033780B2 JP 2003032638 A JP2003032638 A JP 2003032638A JP 2003032638 A JP2003032638 A JP 2003032638A JP 4033780 B2 JP4033780 B2 JP 4033780B2
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semiconductor chip
circuit
semiconductor
bonding
semiconductor device
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JP2004247347A (en
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要 小林
孝明 佐々木
高橋　　義和
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Description

【０００１】
【発明の属する技術分野】
本発明は、マルチチップ型の半導体装置とその製造方法に関するものである。
【０００２】
【従来の技術】
【０００３】
【特許文献１】
特開２００１−９４０４０号公報
【特許文献２】
特開２００１−１１０９８１号公報
【０００４】
図２は、前記特許文献２に記載された従来のマルチチップ型の半導体装置の断面図である。
【０００５】
この半導体装置は、リードフレームのダイパッド部２に、接着剤４を介して第１半導体チップ１ａの表面（接合電極を有する面）が接合され、更に、この第１半導体チップ１ａの裏面に、接着剤５を介して第２半導体チップ１ｂの裏面が接合されている。第１半導体チップ１ａの表面の電極は、ボンディングワイヤ６ａを介してリードフレームのインナーリード部３に接続され、第２半導体チップ１ｂの表面の電極は、ボンディングワイヤ６ｂを介してリードフレームのインナーリード部３に接続されている。そして、これら全体が封止剤７によって封止されている。これにより、パッケージ・サイズを大きくすることなく、複数の半導体チップを１つの半導体装置に封止することができ、高集積化が図られている。
【０００６】
【発明が解決しようとする課題】
しかしながら、従来の半導体装置では、次のような課題があった。
リードフレームのダイパッド部２の片面に２つの半導体チップを搭載するため、このリードフレームのダイパッド部２とインナーリード部３に段差を設け、このダイパッド部２の凹部の底面に半導体チップ１ａを接合するようにしている。このため、リードフレームの形状が複雑になりコストが増加するという課題があった。また、第１半導体チップ１ａと第２半導体チップ１ｂは、接着剤５を介して背中合わせに接合されているため、放熱性や電磁シールドの効果が得られないという課題があった。
【０００７】
【課題を解決するための手段】
前記課題を解決するために、本発明は、半導体装置において、ダイパッド部とインナーリード部が同一平面上に形成されたリードフレームと、前記ダイパッド部の表面と裏面にそれぞれ接着剤を介して固着された第１及び第２の半導体チップと、前記第１の半導体チップの回路面を保護するために、例えば、該第１の半導体チップの回路形成面の四隅に所定の厚さを有する絶縁性のテープを貼り付けて形成した回路面保護材と、前記第１及び第２の半導体チップの電極と前記インナーリード部を接続するボンディングワイヤと、前記第１及び第２の半導体チップと前記ボンディングワイヤを封止して保護する封止樹脂とを備えている。
【０００８】
また、本発明では半導体装置を、ダイパッド部とインナーリード部が同一平面上に形成されたリードフレームのダイパッド部の表面に、第１の半導体チップを接着剤を介して固着する第１ダイボンド工程と、前記第１の半導体チップの回路形成面に回路面を保護するための所定の高さを有する回路面保護材を設ける保護材形成工程と、前記第１の半導体チップの回路形成面を下にしてボンディングステージに搭載し、前記ダイパッド部の裏面に第２の半導体チップを接着剤を介して固着する第２ダイボンド工程と、前記第２の半導体チップの電極とこれに対応する前記インナーリード部をボンディングワイヤで接続する第１ワイヤボンド工程と、前記第１の半導体チップの電極とこれに対応する前記インナーリード部をボンディングワイヤで接続する第２ワイヤボンド工程と、前記第１及び第２の半導体チップと前記ボンディングワイヤを封止樹脂で封止する樹脂封止工程とを、順次行って製造するようにしている。
【０００９】
【発明の実施の形態】
図１は、本発明の実施形態を示すマルチチップ型の半導体装置の断面図である。
この半導体装置は、２つの半導体チップ１１，１２の裏面（回路面の反対側の面）が、リードフレーム１３の両面に、それぞれ接着剤１４，１５を用いて固着されている。リードフレーム１３は、例えば、鉄−ニッケル合金や銅等の０．１ｍｍ程度の薄い金属板を打ち抜いて形成したものである。リードフレーム１３は、半導体チップ１１，１２を搭載するためのダイパッド部１３ａと、この半導体チップ１１，１２からの配線を引き出すためのインナーリード部１３ｂと、半導体装置をプリント配線基板等に機械的及び電気的に接続するためのアウターリード部１３ｃを有しており、このダイパッド部１３ａとインナーリード部１３ｂは、同一平面上に形成されている。
【００１０】
半導体チップ１１の表面の四隅には、回路面を保護するための回路面保護材として、例えば、金を０．１ｍｍ程度の高さに盛り上げた保護バンプ１６が形成されている。また、半導体チップ１１，１２の表面の電極は、それぞれ金線等のボンディングワイヤ１７，１８を介して、リードフレーム１３の対応するインナーリード部１３ｂに接続されている。そして、これらの半導体チップ１１，１２、リードフレーム１３のダイパッド部１３ａとインナーリード部１３ｂ、及びボンディングワイヤ１７，１８を含む全体が、例えば、エポキシ樹脂等の封止樹脂１９によって封止されている。
【００１１】
また、封止樹脂１９から外部に引き出されたリードフレーム１３のアウターリード部１３ｃは、鍍金が施されて所定の形状に整形されている。
【００１２】
図３及び図４は、図１の半導体装置の製造方法を示す工程図とフローチャートである。以下、これらの図３及び図４を参照しつつ、図１の半導体装置の製造方法を説明する。
【００１３】
（１） 工程１（第１ダイボンド工程）
ボンディングステージ９１の上に、金属板を打ち抜いて平面状に形成されたリードフレーム１３を配置し、このリードフレーム１３のダイパッド部１３ａに、半導体チップ１１の裏面を接着剤１４を用いて固着する。接着剤１４としては、例えば、絶縁フィルムの両面にアクリル・エポキシ樹脂系の接着剤を塗布した両面接着テープが用いられる。なお、この工程図では、半導体装置１個分について図示しているが、実際にはリードフレーム１３には複数の半導体装置に対応するダイパッド部１３ａ等が形成され、同一工程で同時に複数の半導体装置が製造されるようになっている。
【００１４】
（２） 工程２（保護材形成工程、保護バンプ形成工程）
半導体チップ１１の表面の四隅に、金線をボンディングして、高さ０．１ｍｍ程度の保護バンプ１６を形成する。
【００１５】
（３） 工程３（第２ダイボンド工程）
半導体チップ１１が固着されたリードフレーム１３を裏返しして、この半導体チップ１１の表面が下側になるように、ボンディングステージ９１の上に乗せる。この時、半導体チップ１１の表面の四隅に形成された保護バンプ１６によって、この半導体チップ１１の回路面がボンディングステージ９１の表面に接触しないように保護される。
【００１６】
その後、リードフレーム１３のダイパッド部１３ａの半導体チップ１１とは反対側の面に、半導体チップ１２の裏面を接着剤１４と同様の接着剤１５を用いて固着する。
【００１７】
（４） 工程４（第１ワイヤボンド工程）
半導体チップ１２の表面の電極と、これに対応するリードフレーム１３のインナーリード部１３ｂとの間を、ワイヤボンディング装置を使用してボンディングワイヤ１８を介して接続する。ワイヤボンディング装置は、例えば、金線等のボンディングワイヤ１８を、熱圧着と超音波振動を併用して接続するものである。
【００１８】
（５） 工程５（第２ワイヤボンド工程）
半導体チップ１２とインナーリード部１３ｂとの間にワイヤボンディングが施されたリードフレーム１３を裏返しして、この半導体チップ１２の表面が下側になるように、ボンディングステージ９１の上に乗せる。この時、既に配線された裏面のボンディングワイヤ１８が、ボンディングステージ９１の表面に接触しないように、スペーサ９２等を用いてリードフレーム１３のインナーリード部１３ｂ及びアウターリード部１３ｃを固定する。
【００１９】
その後、半導体チップ１１の表面の電極と、これに対応するリードフレーム１３のインナーリード部１３ｂとの間を、ボンディングワイヤ１７を介して接続する。
【００２０】
（６） 工程６（樹脂封止工程）
半導体チップ１１，１２とインナーリード部１３ｂとの間にワイヤボンディングが施されたリードフレーム１３を、下金型９３と上金型９４で挟み、その空間に液状のエポキシ樹脂等の封止樹脂１９を注入する。
【００２１】
（７） 工程７（鍍金工程）
封止樹脂１９が固化して半導体チップ１１，１２とボンディングワイヤ１７，１８がモールドされたあと、リードフレーム１３を金型から取り出し、リード部１３ｃを鍍金する。
【００２２】
（８） 工程８（リード整形工程）
リードフレーム１３を切断して個々の半導体装置に分離し、アウターリード部１３ｃを所定の形状に整形する。これにより、図１に示すようなマルチチップ型の半導体装置が完成する。
【００２３】
このように、本実施形態の半導体装置は、平板状のリードフレーム１３を使用しているので、このリードフレーム１３の製造工程が簡素化されてコスト削減が可能になる。また、金属製のリードフレーム１３の両面に半導体チップ１１，１２を固着しているので、放熱性と電磁シールドの効果が得られる。
【００２４】
更に、半導体チップ１１の表面の四隅に保護バンプ１６を設けているので、図３の工程３，４で半導体チップ１２を搭載したり、ワイヤボンディングを行うときに、この半導体チップ１１の表面がボンディングステージ９１に接触することがなくなり、回路面が損傷するおそれがなくなって歩留まりが向上するという利点がある。
【００２５】
なお、本発明は、上記実施形態に限定されず、種々の変形が可能である。この変形例としては、例えば、次のようなものがある。
【００２６】
（ａ） この半導体装置を構成する材料や寸法形状は一例であり、説明したものに限定するものではない。
【００２７】
（ｂ） 半導体チップ１１の表面を保護するための回路面保護材として、この半導体チップ１１の表面の四隅に金の保護バンプ１６を設けているが、その他の回路面保護材を用いることができる。
【００２８】
図５（ａ）〜（ｃ）は、本発明のその他の実施形態を示す回路面保護材の説明図である。
【００２９】
図５（ａ）では、回路面保護材として、半導体チップ１１の表面の四隅に、例えば、厚さ０．１ｍｍ程度の裏面に接着剤が塗布されたポリイミド等の保護テープ２０を貼り付けている。
【００３０】
図５（ｂ）では、半導体チップ１１の表面の周囲で、接続用の電極が形成されていない箇所に、例えば、厚さ０．１ｍｍ程度に絶縁性の塗料を塗布し、保護被膜２１を形成している。これにより、確実に回路面を保護することができる。
【００３１】
図５（ｃ）では、半導体チップ１１の表面の中央部で、接続用の電極が形成されていない箇所に、例えば、厚さ０．１ｍｍ程度に絶縁性の塗料を塗布し、保護被膜２２を形成している。これにより、更に確実に回路面の保護が可能になると共に、樹脂封止時に封止樹脂１９の未充填部が発生するおそれがなくなって歩留まりが向上する。
【００３２】
【発明の効果】
以上詳細に説明したように、本発明によれば、ダイパッド部とインナーリード部が同一平面上に形成された平板状のリードフレームを使用しているので、このリードフレームの製造工程が簡素化されてコスト削減が可能になる。また、金属製のリードフレームの両面に第１及び第２の半導体チップを固着しているので、放熱性と電磁シールドの効果が得られる。更に、第１の半導体チップの回路形成面の四隅に所定の厚さの絶縁性テープや絶縁性塗料による回路面保護材を設けている。これにより、第２の半導体チップを搭載したりワイヤボンディングを行うときに、この第１の半導体チップの表面がボンディングステージ等に接触することがなくなり、回路面の損傷を防止できるという効果がある。
【図面の簡単な説明】
【図１】本発明の実施形態を示すマルチチップ型の半導体装置の断面図である。
【図２】従来のマルチチップ型の半導体装置の断面図である。
【図３】図１の半導体装置の製造方法を示す工程図である。
【図４】図１の半導体装置の製造方法を示すフローチャートである。
【図５】本発明のその他の実施形態を示す回路面保護材の説明図である。
【符号の説明】
１１，１２ 半導体チップ
１３ リードフレーム
１３ａ ダイパッド部
１３ｂ インナーリード部
１３ｃ アウターリード部
１４，１５ 接着剤
１６ 保護バンプ
１７，１８ ボンディングワイヤ
１９ 封止樹脂
２０ 保護テープ
２１，２２ 保護被膜
９１ ボンディングステージ
９２ スペーサ
９３ 下金型
９４ 上金型[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multichip semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
[0003]
[Patent Document 1]
JP 2001-94040 A [Patent Document 2]
Japanese Patent Laid-Open No. 2001-110981
FIG. 2 is a cross-sectional view of a conventional multi-chip type semiconductor device described in Patent Document 2. In FIG.
[0005]
In this semiconductor device, the surface of the first semiconductor chip 1a (the surface having the bonding electrode) is bonded to the die pad portion 2 of the lead frame via the adhesive 4, and further bonded to the back surface of the first semiconductor chip 1a. The back surface of the second semiconductor chip 1 b is bonded via the agent 5. The electrode on the surface of the first semiconductor chip 1a is connected to the inner lead part 3 of the lead frame via the bonding wire 6a, and the electrode on the surface of the second semiconductor chip 1b is connected to the inner lead of the lead frame via the bonding wire 6b. Connected to the unit 3. All of these are sealed with a sealant 7. Accordingly, a plurality of semiconductor chips can be sealed in one semiconductor device without increasing the package size, and high integration is achieved.
[0006]
[Problems to be solved by the invention]
However, the conventional semiconductor device has the following problems.
In order to mount two semiconductor chips on one side of the die pad portion 2 of the lead frame, a step is provided in the die pad portion 2 and the inner lead portion 3 of the lead frame, and the semiconductor chip 1a is joined to the bottom surface of the concave portion of the die pad portion 2. I am doing so. For this reason, there is a problem that the shape of the lead frame becomes complicated and the cost increases. Moreover, since the 1st semiconductor chip 1a and the 2nd semiconductor chip 1b were joined back to back via the adhesive agent 5, there existed a subject that the effect of heat dissipation or an electromagnetic shield was not acquired.
[0007]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention provides a semiconductor device in which a die pad portion and an inner lead portion are fixed on the same plane with an adhesive on the front and back surfaces of the die pad portion. In order to protect the first and second semiconductor chips and the circuit surface of the first semiconductor chip, for example, an insulating material having a predetermined thickness at four corners of the circuit forming surface of the first semiconductor chip. A circuit surface protecting material formed by adhering a tape; a bonding wire connecting the electrodes of the first and second semiconductor chips and the inner lead portion; and the first and second semiconductor chips and the bonding wire. And a sealing resin for sealing and protecting.
[0008]
According to the present invention, the semiconductor device is bonded to the surface of the die pad portion of the lead frame in which the die pad portion and the inner lead portion are formed on the same plane, with a first die bonding step for fixing the first semiconductor chip with an adhesive. A protective material forming step of providing a circuit surface protective material having a predetermined height for protecting the circuit surface on the circuit forming surface of the first semiconductor chip; and a circuit forming surface of the first semiconductor chip facing down. A second die bonding step of mounting the second semiconductor chip on the back surface of the die pad portion with an adhesive, an electrode of the second semiconductor chip and the corresponding inner lead portion. A first wire bonding step of connecting with a bonding wire, an electrode of the first semiconductor chip and the corresponding inner lead portion with a bonding wire; A second wire bonding step for continued and a resin sealing step of sealing with a sealing resin the bonding wire and the first and second semiconductor chips, so that manufacturing performed sequentially.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a cross-sectional view of a multi-chip type semiconductor device showing an embodiment of the present invention.
In this semiconductor device, the back surfaces (surfaces opposite to the circuit surface) of the two semiconductor chips 11 and 12 are fixed to both surfaces of the lead frame 13 using adhesives 14 and 15, respectively. The lead frame 13 is formed by punching a thin metal plate of about 0.1 mm such as an iron-nickel alloy or copper. The lead frame 13 includes a die pad portion 13a for mounting the semiconductor chips 11 and 12, an inner lead portion 13b for drawing wiring from the semiconductor chips 11 and 12, and a semiconductor device mechanically and printed on a printed wiring board or the like. An outer lead portion 13c for electrical connection is provided, and the die pad portion 13a and the inner lead portion 13b are formed on the same plane.
[0010]
At the four corners of the surface of the semiconductor chip 11, for example, protective bumps 16 in which gold is raised to a height of about 0.1 mm are formed as circuit surface protection materials for protecting the circuit surface. The electrodes on the surface of the semiconductor chips 11 and 12 are connected to corresponding inner lead portions 13b of the lead frame 13 via bonding wires 17 and 18 such as gold wires, respectively. The whole including the semiconductor chips 11 and 12, the die pad portion 13 a and the inner lead portion 13 b of the lead frame 13, and the bonding wires 17 and 18 is sealed with a sealing resin 19 such as an epoxy resin. .
[0011]
Further, the outer lead portion 13c of the lead frame 13 drawn out from the sealing resin 19 is plated and shaped into a predetermined shape.
[0012]
3 and 4 are process diagrams and a flowchart showing a method for manufacturing the semiconductor device of FIG. Hereinafter, a method of manufacturing the semiconductor device of FIG. 1 will be described with reference to FIGS. 3 and 4.
[0013]
(1) Step 1 (first die bonding step)
A lead frame 13 formed by punching a metal plate is disposed on the bonding stage 91, and the back surface of the semiconductor chip 11 is fixed to the die pad portion 13 a of the lead frame 13 using an adhesive 14. As the adhesive 14, for example, a double-sided adhesive tape in which an acrylic / epoxy resin adhesive is applied to both sides of an insulating film is used. In this process diagram, one semiconductor device is shown, but in reality, a die pad portion 13a corresponding to a plurality of semiconductor devices is formed on the lead frame 13, and a plurality of semiconductor devices are simultaneously formed in the same process. Has been manufactured.
[0014]
(2) Process 2 (protective material forming process, protective bump forming process)
Gold bumps are bonded to the four corners of the surface of the semiconductor chip 11 to form protective bumps 16 having a height of about 0.1 mm.
[0015]
(3) Step 3 (second die bonding step)
The lead frame 13 to which the semiconductor chip 11 is fixed is turned over and placed on the bonding stage 91 so that the surface of the semiconductor chip 11 faces down. At this time, the protection bumps 16 formed at the four corners of the surface of the semiconductor chip 11 are protected so that the circuit surface of the semiconductor chip 11 does not contact the surface of the bonding stage 91.
[0016]
Thereafter, the back surface of the semiconductor chip 12 is fixed to the surface of the die pad portion 13 a of the lead frame 13 opposite to the semiconductor chip 11 by using the adhesive 15 similar to the adhesive 14.
[0017]
(4) Step 4 (first wire bonding step)
The electrodes on the surface of the semiconductor chip 12 and the corresponding inner lead portions 13b of the lead frame 13 are connected via bonding wires 18 using a wire bonding apparatus. The wire bonding apparatus connects, for example, a bonding wire 18 such as a gold wire by using both thermocompression bonding and ultrasonic vibration.
[0018]
(5) Step 5 (second wire bonding step)
The lead frame 13 to which wire bonding is applied between the semiconductor chip 12 and the inner lead portion 13b is turned over and placed on the bonding stage 91 so that the surface of the semiconductor chip 12 is on the lower side. At this time, the inner lead portion 13b and the outer lead portion 13c of the lead frame 13 are fixed using a spacer 92 or the like so that the already-bonded backside bonding wire 18 does not contact the surface of the bonding stage 91.
[0019]
Thereafter, the electrodes on the surface of the semiconductor chip 11 and the corresponding inner lead portions 13 b of the lead frame 13 are connected via bonding wires 17.
[0020]
(6) Process 6 (resin sealing process)
A lead frame 13 wire-bonded between the semiconductor chips 11 and 12 and the inner lead portion 13b is sandwiched between a lower mold 93 and an upper mold 94, and a sealing resin 19 such as a liquid epoxy resin is inserted in the space. Inject.
[0021]
(7) Process 7 (Plating process)
After the sealing resin 19 is solidified and the semiconductor chips 11 and 12 and the bonding wires 17 and 18 are molded, the lead frame 13 is removed from the mold and the lead portion 13c is plated.
[0022]
(8) Process 8 (lead shaping process)
The lead frame 13 is cut and separated into individual semiconductor devices, and the outer lead portion 13c is shaped into a predetermined shape. Thereby, a multi-chip type semiconductor device as shown in FIG. 1 is completed.
[0023]
Thus, since the semiconductor device of this embodiment uses the flat lead frame 13, the manufacturing process of the lead frame 13 is simplified and the cost can be reduced. In addition, since the semiconductor chips 11 and 12 are fixed to both surfaces of the metal lead frame 13, heat dissipation and electromagnetic shielding effects can be obtained.
[0024]
Further, since the protective bumps 16 are provided at the four corners of the surface of the semiconductor chip 11, the surface of the semiconductor chip 11 is bonded when the semiconductor chip 12 is mounted or wire bonded in steps 3 and 4 of FIG. There is an advantage that the contact with the stage 91 is eliminated, the circuit surface is not damaged, and the yield is improved.
[0025]
In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. Examples of this modification include the following.
[0026]
(A) The materials and dimensions of the semiconductor device are examples, and are not limited to those described.
[0027]
(B) Although gold protective bumps 16 are provided at the four corners of the surface of the semiconductor chip 11 as a circuit surface protective material for protecting the surface of the semiconductor chip 11, other circuit surface protective materials can be used. .
[0028]
5 (a) to 5 (c) are explanatory views of a circuit surface protecting material showing another embodiment of the present invention.
[0029]
In FIG. 5A, as a circuit surface protection material, for example, a protective tape 20 such as polyimide having an adhesive applied to the back surface with a thickness of about 0.1 mm is attached to the four corners of the surface of the semiconductor chip 11. .
[0030]
In FIG. 5B, an insulating paint is applied to a portion around the surface of the semiconductor chip 11 where a connection electrode is not formed, for example, to a thickness of about 0.1 mm, and a protective film 21 is formed. is doing. Thereby, a circuit surface can be protected reliably.
[0031]
In FIG. 5C, an insulating paint is applied to a thickness of about 0.1 mm, for example, at a central portion of the surface of the semiconductor chip 11 where no connection electrode is formed, and a protective film 22 is applied. Forming. As a result, the circuit surface can be more reliably protected, and there is no possibility that an unfilled portion of the sealing resin 19 occurs during resin sealing, thereby improving the yield.
[0032]
【The invention's effect】
As described above in detail, according to the present invention, a flat lead frame in which the die pad portion and the inner lead portion are formed on the same plane is used, so that the manufacturing process of the lead frame is simplified. Cost reduction. In addition, since the first and second semiconductor chips are fixed to both surfaces of the metal lead frame, heat dissipation and electromagnetic shielding effects can be obtained. Further, a circuit surface protecting material with a predetermined thickness of insulating tape or insulating paint is provided at the four corners of the circuit forming surface of the first semiconductor chip. As a result, when the second semiconductor chip is mounted or wire bonding is performed, the surface of the first semiconductor chip does not come into contact with the bonding stage or the like, and the circuit surface can be prevented from being damaged.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a multi-chip type semiconductor device showing an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a conventional multi-chip type semiconductor device.
3 is a process diagram illustrating a method for manufacturing the semiconductor device of FIG. 1; FIG.
4 is a flowchart showing a manufacturing method of the semiconductor device of FIG. 1;
FIG. 5 is an explanatory diagram of a circuit surface protective material showing another embodiment of the present invention.
[Explanation of symbols]
11, 12 Semiconductor chip 13 Lead frame 13a Die pad portion 13b Inner lead portion 13c Outer lead portions 14, 15 Adhesive 16 Protective bumps 17, 18 Bonding wire 19 Sealing resin 20 Protective tape 21, 22 Protective coating 91 Bonding stage 92 Spacer 93 Lower mold 94 Upper mold

Claims (6)

ダイパッド部とインナーリード部が同一平面上に形成されたリードフレームと、
前記ダイパッド部の表面と裏面にそれぞれ接着剤を介して固着された第１及び第２の半導体チップと、
前記第１の半導体チップの回路面を保護するために、該第１の半導体チップの回路形成面の四隅に所定の厚さを有する絶縁性のテープを貼り付けて形成した回路面保護材と、
前記第１及び第２の半導体チップの電極と前記インナーリード部を接続するボンディングワイヤと、
前記第１及び第２の半導体チップと前記ボンディングワイヤを封止して保護する封止樹脂とを、
備えたことを特徴とする半導体装置。A lead frame in which the die pad portion and the inner lead portion are formed on the same plane;
First and second semiconductor chips each fixed to the front and back surfaces of the die pad portion via an adhesive;
In order to protect the circuit surface of the first semiconductor chip, a circuit surface protection material formed by attaching an insulating tape having a predetermined thickness to the four corners of the circuit formation surface of the first semiconductor chip;
Bonding wires connecting the electrodes of the first and second semiconductor chips and the inner lead portion;
A sealing resin for sealing and protecting the first and second semiconductor chips and the bonding wire;
A semiconductor device comprising the semiconductor device. ダイパッド部とインナーリード部が同一平面上に形成されたリードフレームと、
前記ダイパッド部の表面と裏面にそれぞれ接着剤を介して固着された第１及び第２の半導体チップと、
前記第１の半導体チップの回路面を保護するために、該第１の半導体チップの回路形成面の周囲に絶縁性の塗料を所定の厚さに塗布して形成した回路面保護材と、
前記第１及び第２の半導体チップの電極と前記インナーリード部を接続するボンディングワイヤと、
前記第１及び第２の半導体チップと前記ボンディングワイヤを封止して保護する封止樹脂とを、
備えたことを特徴とする半導体装置。 A lead frame in which the die pad portion and the inner lead portion are formed on the same plane;
First and second semiconductor chips each fixed to the front and back surfaces of the die pad portion via an adhesive;
In order to protect the circuit surface of the first semiconductor chip, a circuit surface protecting material formed by applying an insulating paint to a predetermined thickness around the circuit forming surface of the first semiconductor chip;
Bonding wires connecting the electrodes of the first and second semiconductor chips and the inner lead portion;
A sealing resin for sealing and protecting the first and second semiconductor chips and the bonding wire;
A semiconductor device comprising the semiconductor device. ダイパッド部とインナーリード部が同一平面上に形成されたリードフレームのダイパッド部の表面に、第１の半導体チップを接着剤を介して固着する第１ダイボンド工程と、A first die bonding step of fixing the first semiconductor chip to the surface of the die pad portion of the lead frame in which the die pad portion and the inner lead portion are formed on the same plane with an adhesive;
前記第１の半導体チップの回路形成面に回路面を保護するための所定の高さを有する回路面保護材を設ける保護材形成工程と、  A protective material forming step of providing a circuit surface protective material having a predetermined height for protecting the circuit surface on the circuit forming surface of the first semiconductor chip;
前記第１の半導体チップの回路形成面を下にしてボンディングステージに搭載し、前記ダイパッド部の裏面に第２の半導体チップを接着剤を介して固着する第２ダイボンド工程と、  A second die bonding step in which the circuit formation surface of the first semiconductor chip is mounted on a bonding stage and the second semiconductor chip is fixed to the back surface of the die pad portion with an adhesive;
前記第２の半導体チップの電極とこれに対応する前記インナーリード部をボンディングワイヤで接続する第１ワイヤボンド工程と、  A first wire bonding step of connecting an electrode of the second semiconductor chip and the corresponding inner lead portion with a bonding wire;
前記第１の半導体チップの電極とこれに対応する前記インナーリード部をボンディングワイヤで接続する第２ワイヤボンド工程と、  A second wire bonding step of connecting the electrode of the first semiconductor chip and the corresponding inner lead portion with a bonding wire;
前記第１及び第２の半導体チップと前記ボンディングワイヤを封止樹脂で封止する樹脂封止工程とを、  A resin sealing step of sealing the first and second semiconductor chips and the bonding wire with a sealing resin;
順次行うことを特徴とする半導体装置の製造方法。  A method for manufacturing a semiconductor device, which is performed sequentially. 前記保護材形成工程において、前記第１の半導体チップの回路形成面の四隅に金属バンプを所定の高さに盛り上げて前記回路面保護材を形成することを特徴とする請求項３記載の半導体装置の製造方法。4. The semiconductor device according to claim 3, wherein, in the protective material forming step, the circuit surface protective material is formed by raising metal bumps to predetermined heights at four corners of the circuit forming surface of the first semiconductor chip. Manufacturing method. 前記保護材形成工程において、前記第１の半導体チップの回路形成面の四隅に所定の厚さを有する絶縁性のテープを貼り付けて前記回路面保護材を形成することを特徴とする請求項３記載の半導体装置の製造方法。4. The circuit surface protection material is formed by attaching an insulating tape having a predetermined thickness to four corners of a circuit formation surface of the first semiconductor chip in the protection material forming step. The manufacturing method of the semiconductor device of description. 前記保護材形成工程において、前記第１の半導体チップの回路形成面の周囲または中央部に絶縁性の塗料を所定の厚さに塗布して前記回路面保護材を形成することを特徴とする請求項３記載の半導体装置の製造方法。In the protective material forming step, the circuit surface protective material is formed by applying an insulating paint to a predetermined thickness around or around the circuit forming surface of the first semiconductor chip. Item 4. A method for manufacturing a semiconductor device according to Item 3.
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