JPH10340906A - Surface-mount electronic part, manufacture and mounting thereof - Google Patents

Surface-mount electronic part, manufacture and mounting thereof

Info

Publication number
JPH10340906A
JPH10340906A JP14912697A JP14912697A JPH10340906A JP H10340906 A JPH10340906 A JP H10340906A JP 14912697 A JP14912697 A JP 14912697A JP 14912697 A JP14912697 A JP 14912697A JP H10340906 A JPH10340906 A JP H10340906A
Authority
JP
Japan
Prior art keywords
electronic component
electrode
mounting
semiconductor chip
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14912697A
Other languages
Japanese (ja)
Inventor
Mitsuru Mura
満 村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP14912697A priority Critical patent/JPH10340906A/en
Publication of JPH10340906A publication Critical patent/JPH10340906A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8134—Bonding interfaces of the bump connector
    • H01L2224/81345—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8336—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/83365—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To allow a gap between lamp electrodes and corresponding electrodes of a board to be narrowed with conductive particles within an anisotropic conductive material entrapped by providing signal input/output electrodes on a surface-mount electronic part and by providing the bump electrodes to be formed on the signal input/output electrodes, each bump electrode having a recess of a predetermined size in its tip. SOLUTION: Each of bumps 11 of a semiconductor chip 10 has a recess 11A in its tip. As a result, a gap between the bumps 11 and a printed wiring board 8 can be narrowed while leaving conductive particles 2 within an ACF (anisotropic conductive film) 3 located between the bumps 11 and corresponding lands 9 of the board 8 entrapped in the recesses 11A of the bumps 11 at the time the chip 10 is bonded onto the board 8 by thermocompression after the chip 10 has been positioned with respect to and mounted onto the board 8 through the ACF 3.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【目次】以下の順序で本発明を説明する。[Table of Contents] The present invention will be described in the following order.

【０００２】発明の属する技術分野 従来の技術（図７〜図８） 発明が解決しようとする課題（図８） 課題を解決するための手段 発明の実施の形態（図１〜図６） 発明の効果BACKGROUND OF THE INVENTION Prior Art (FIGS. 7 and 8) Problems to be Solved by the Invention (FIG. 8) Means for Solving the Problems Embodiments of the Invention (FIGS. 1 to 6) effect

【０００３】[0003]

【発明の属する技術分野】本発明は表面実装型電子部品
及びその製造方法並びにその実装方法に関し、例えば異
方性導電材を介してプリント配線基板上にフリツプチツ
プ実装する半導体チツプ及びその製造方法並びにその実
装方法に適用して好適なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount type electronic component, a method of manufacturing the same, and a method of mounting the same. For example, a semiconductor chip mounted on a printed wiring board via an anisotropic conductive material by a flip chip, a method of manufacturing the same, and a method thereof This is suitable for application to a mounting method.

【０００４】[0004]

【従来の技術】従来、半導体チツプをベアでプリント配
線基板上に実装する実装方法の１つとしてフリツプチツ
プ実装法があり、その１つに例えば図８に示すような絶
縁性樹脂材からなるベースフイルム１内に直径 5〔μm
〕程度の導電粒子２（例えば金粒子又はニツケル粒子
等）が複数散りばめられてなるＡＣＦ（Anisotropic Co
nductive Film ：異方性導電膜）３を用いた方法があ
る。2. Description of the Related Art Conventionally, there is a flip chip mounting method as one of mounting methods for mounting a semiconductor chip on a printed wiring board by bare, and one of such methods is a base film made of an insulating resin material as shown in FIG. 5 [μm in one
ACF (Anisotropic Co.) in which a plurality of conductive particles 2 (for example, gold particles or nickel particles, etc.) are scattered.
nductive Film).

【０００５】実際上ＡＣＦ３を用いたフリツプチツプ実
装法においては、図９に示すように、半導体チツプ５の
信号入出力用の各電極（以下、これをパツドと呼ぶ）６
上にそれぞれ突起電極（以下、これをバンプと呼ぶ）７
を形成すると供に、ＡＣＦ３をプリント配線基板８の半
導体チツプ５の実装領域上に配置し、プリント配線基板
８の基板面８Ａ上に所定パターンで形成されている電極
（以下、これをランドと呼ぶ）９と対応するように位置
決めして、ＡＣＦ３を介してプリント配線基板８上に圧
着することにより行われる。In the flip chip mounting method using the ACF 3 in practice, as shown in FIG. 9, each signal input / output electrode (hereinafter, referred to as a pad) 6 of the semiconductor chip 5 is used.
On each of them, a protruding electrode (hereinafter, referred to as a bump) 7
In addition to the above, the ACF 3 is arranged on the mounting area of the semiconductor chip 5 of the printed wiring board 8, and the electrodes formed in a predetermined pattern on the substrate surface 8A of the printed wiring board 8 (hereinafter referred to as lands). 9) Positioning is performed so as to correspond to 9 and press-fitted onto the printed wiring board 8 via the ACF 3.

【０００６】かくしてこの方法によれば、半導体チツプ
５をＡＣＦ３のベースフイルム１によりプリント配線基
板８上に固着することができ、また当該半導体チツプ５
のバンプ７とプリント配線基板８の対応するランド９と
の間の導通を、これら半導体チツプ５のバンプ７及びこ
れと対応するプリント配線基板８のランド９間に挟まれ
たＡＣＦ３の導電粒子２を介してとることができる。Thus, according to this method, the semiconductor chip 5 can be fixed on the printed wiring board 8 by the base film 1 of the ACF 3, and the semiconductor chip 5 can be fixed.
The conduction between the bumps 7 of the semiconductor chip 5 and the corresponding lands 9 of the printed wiring board 8 is determined by the conductive particles 2 of the ACF 3 sandwiched between the bumps 7 of the semiconductor chip 5 and the corresponding lands 9 of the printed wiring board 8. Can be taken through.

【０００７】[0007]

【発明が解決しようとする課題】ところが上述のような
ＡＣＦ３を用いたフリツプチツプ実装法では、半導体チ
ツプ５のバンプ７の先端形状が突起しているために半導
体チツプ５をプリント配線基板８上に圧着する際に半導
体チツプ５のバンプ７がＡＣＦ３内の導電粒子２を押し
退けながらプリント配線基板８の対応するランド９との
ギヤツプを狭めていくことにより、半導体チツプ５のバ
ンプ７及びプリント配線基板８のランド９間の導電粒子
２が逃げてしまうことがある。However, in the flip-chip mounting method using the ACF 3 as described above, the semiconductor chip 5 is pressed on the printed wiring board 8 because the tip of the bump 7 of the semiconductor chip 5 is protruding. At this time, the gap between the bump 7 of the semiconductor chip 5 and the corresponding land 9 of the printed wiring board 8 is narrowed while pushing away the conductive particles 2 in the ACF 3, thereby forming the bump 7 of the semiconductor chip 5 and the printed wiring board 8. The conductive particles 2 between the lands 9 may escape.

【０００８】この結果、ＡＣＦ３を用いたフリツプチツ
プ実装法では、必ずしもＡＣＦ３内の導電粒子２が半導
体チツプ５のバンプ７とプリント配線基板８のランド９
の間に挟まらず、これら半導体チツプ５のバンプ７及び
プリント配線基板８のランド９間を導通接続し得ないこ
とがあり、実装の信頼性が低い問題があつた。As a result, in the flip-chip mounting method using the ACF 3, the conductive particles 2 in the ACF 3 are not necessarily the bumps 7 of the semiconductor chip 5 and the lands 9 of the printed wiring board 8.
The bumps 7 of the semiconductor chip 5 and the lands 9 of the printed wiring board 8 cannot be electrically connected to each other without being sandwiched between them, and there is a problem that mounting reliability is low.

【０００９】本発明は以上の点を考慮してなされたもの
で、実装の信頼性を向上させる表面実装型電子部品及び
その製造方法並びにその実装方法を提案しようとするも
のである。SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to propose a surface mount type electronic component for improving the reliability of mounting, a method of manufacturing the same, and a method of mounting the same.

【００１０】[0010]

【課題を解決するための手段】かかる課題を解決するた
め本発明においては、表面実装型電子部品に信号入出力
用の電極と、電極上に形成された先端部に所定の大きさ
のくぼみを有する突起電極とを設けるようにした。According to the present invention, in order to solve the above-mentioned problems, a signal input / output electrode is formed on a surface-mounted electronic component, and a recess having a predetermined size is formed at a tip portion formed on the electrode. And a protruding electrode having the same.

【００１１】この結果、この表面実装型電子部品を異方
性導電材を介してプリント配線基板上に実装する際、突
起電極のくぼみが異方性導電材内の導電粒子を捕獲した
状態で当該突起電極とプリント配線基板の対応する電極
とのギヤツプを狭めることができる。As a result, when this surface-mounted electronic component is mounted on a printed wiring board via an anisotropic conductive material, the depressions of the protruding electrodes capture the conductive particles in the anisotropic conductive material. The gap between the protruding electrodes and the corresponding electrodes on the printed wiring board can be reduced.

【００１２】また本発明においては、表面実装型電子部
品の製造方法において表面実装型電子部品の電極上に突
起電極を形成する第１の工程と、突起電極の先端部に所
定の大きさのくぼみを形成する第２の工程とを設けるよ
うにした。Further, in the present invention, in the method of manufacturing a surface-mounted electronic component, a first step of forming a protruding electrode on an electrode of the surface-mounted electronic component, and a recess having a predetermined size at a tip portion of the protruding electrode. And a second step of forming

【００１３】この結果、このようにして製造された表面
実装型電子部品を異方性導電材を介してプリント配線基
板上に実装する際、突起電極のくぼみが異方性導電材内
の導電粒子を捕獲した状態で当該突起電極とプリント配
線基板の対応する電極とのギヤツプを狭めることができ
る。As a result, when the surface-mounted electronic component manufactured as described above is mounted on a printed wiring board via an anisotropic conductive material, the depression of the protruding electrode is caused by the conductive particles in the anisotropic conductive material. The gap between the protruding electrode and the corresponding electrode of the printed wiring board can be narrowed in a state where the signal is captured.

【００１４】さらに本発明においては、表面実装型電子
部品の実装方法において、表面実装型電子部品の電極上
に突起電極を形成する第１のステツプと、突起電極の先
端部に所定の大きさのくぼみを形成する第２のステツプ
と、表面実装型電子部品を異方性導電材を介してプリン
ト配線基板上に実装する第３のステツプとを設けるよう
にした。Further, according to the present invention, in a method of mounting a surface-mounted electronic component, a first step of forming a protruding electrode on an electrode of the surface-mounted electronic component, and a step of forming a predetermined size on the tip of the protruding electrode. A second step for forming a depression and a third step for mounting a surface-mounted electronic component on a printed wiring board via an anisotropic conductive material are provided.

【００１５】この結果、表面実装型電子部品をプリント
配線基板上に実装する際、突起電極のくぼみが異方性導
電材内の導電粒子を捕獲した状態で当該突起電極とプリ
ント配線基板の対応する電極とのギヤツプを狭めること
ができる。As a result, when mounting the surface-mounted electronic component on the printed wiring board, the projection electrode corresponds to the printed wiring board in a state where the depressions of the projection electrode capture the conductive particles in the anisotropic conductive material. The gap with the electrodes can be reduced.

【００１６】[0016]

【発明の実施の形態】以下図面について、本発明の一実
施の形態を詳述する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

【００１７】図９の対応部分に同一符号を付して示した
図３において、１０は全体として本実施の形態による半
導体チツプを示し、各パツド６上にそれぞれ形成された
バンプ１１の構成を除いて、図９の半導体チツプ５と同
様に構成されている。In FIG. 3 in which the same reference numerals are given to corresponding parts in FIG. 9, reference numeral 10 denotes a semiconductor chip as a whole according to the present embodiment, except for the structure of bumps 11 formed on each pad 6 respectively. Thus, it is configured similarly to the semiconductor chip 5 of FIG.

【００１８】すなわちこの半導体チツプ１０の場合、各
バンプ１１は図２に示すように、先端部にくぼみ１１Ａ
が形成されている。That is, in the case of this semiconductor chip 10, each bump 11 has a recess 11A at the tip as shown in FIG.
Are formed.

【００１９】これによりこの半導体チツプ１０において
は、図３のようにＡＣＦ３を介してプリント配線基板８
上に実装する際、半導体チツプ１０をＡＣＦ３を介して
プリント配線基板８上に位置決めしてマウントした後、
当該半導体チツプ１０をプリント配線基板８上に熱圧着
するときに、バンプ１１及びプリント配線基板８の対応
するランド９間に位置するＡＣＦ３内の導電粒子２を各
バンプ１１のくぼみ１１Ａにおいて捕らえた状態のまま
各バンプ１１及びプリント配線基板８間のギヤツプを狭
めることができるようになされている。As a result, in this semiconductor chip 10, as shown in FIG.
When the semiconductor chip 10 is mounted on the printed wiring board 8 via the ACF 3, the semiconductor chip 10 is mounted and mounted.
When the semiconductor chip 10 is thermocompression-bonded onto the printed wiring board 8, the conductive particles 2 in the ACF 3 located between the bumps 11 and the corresponding lands 9 of the printed wiring board 8 are captured in the recesses 11 </ b> A of each bump 11. The gap between each bump 11 and the printed wiring board 8 can be narrowed as it is.

【００２０】ここで、このような半導体チツプ１０は、
まず図４（Ａ）のように通常の手順により一面の所定位
置にそれぞれパツド６が設けられてなる半導体チツプ１
０を形成し、次いで図４（Ｂ）のようにこの半導体チツ
プ１０の各パツド６上にそれぞれバンプ２３を形成した
後、図４（Ｃ）のようにこれら各バンプ２３の先端部に
くぼみ１１Ａを形成することにより製造することができ
る。Here, such a semiconductor chip 10 is
First, as shown in FIG. 4A, a semiconductor chip 1 in which pads 6 are respectively provided at predetermined positions on one surface by a normal procedure.
After forming bumps 23 on each pad 6 of the semiconductor chip 10 as shown in FIG. 4B, a recess 11A is formed at the tip of each bump 23 as shown in FIG. 4C. Can be produced.

【００２１】この場合、半導体チツプ１０の各パツド６
上にバンプ２３を形成する工程（図４（Ｂ））では、い
わゆるボールバンプ法を用いることができ、実際上ボー
ルバンプ法を用いる場合には、まず図５（Ａ）に示すよ
うに、キヤピラリ２０の先端から金属ワイヤ（一般的に
は金ワイヤ）２１を突出させ、これを電気放電により溶
融させることにより、その表面張力によつてボール状の
塊（以下これを、金ボールと呼ぶ）２１Ａを形成した
後、当該金ボール２１Ａを図５（Ｂ）のように半導体チ
ツプ１０の実装面１０Ａのパツド６に加圧し、超音波を
印加することにより、半導体チツプ１０のパツド６に接
合する。In this case, each pad 6 of the semiconductor chip 10 is
In the step of forming the bumps 23 on the upper surface (FIG. 4B), a so-called ball bump method can be used. When the ball bump method is actually used, first, as shown in FIG. A metal wire (generally, a gold wire) 21 is protruded from the tip of 20 and is melted by electric discharge, so that a ball-shaped mass (hereinafter referred to as a gold ball) 21A is formed by its surface tension. Then, the gold ball 21A is pressed to the pad 6 of the mounting surface 10A of the semiconductor chip 10 as shown in FIG. 5B, and is bonded to the pad 6 of the semiconductor chip 10 by applying an ultrasonic wave.

【００２２】その後図５（Ｃ）に示すように金属ワイヤ
２１をキヤピラリ２０で保持しながら引き上げることに
より、金属ワイヤ２１を金ボール２１Ａとの境目から引
きちぎりパツド６上にバンプ２２を形成する。Thereafter, as shown in FIG. 5C, the metal wire 21 is pulled up while being held by the capillary 20, whereby the metal wire 21 is torn off from the boundary between the gold ball 21A and the bump 22 is formed on the pad 6.

【００２３】このような手順により、図６（Ａ）に示す
ように半導体チツプ１０のパツド６の全てにバンプ２２
を形成した後、図６（Ｂ）に示すように例えば一括プレ
ス等により高さを一定に揃える（レベリング）。By such a procedure, as shown in FIG. 6A, bumps 22 are formed on all of the pads 6 of the semiconductor chip 10.
Is formed, the height is made uniform (leveling) by, for example, a batch press as shown in FIG. 6B.

【００２４】これにより、半導体チツプ１０の各パツド
６上にそれぞれ同じ高さのバンプ２２Ａを形成すること
ができる。Thus, bumps 22A having the same height can be formed on each pad 6 of the semiconductor chip 10.

【００２５】また、これら各バンプ２２Ａの先端部にく
ぼみ１１Ａを形成する工程（図４（Ｃ））は、図７に示
すように、各バンプ２２Ａの先端をバンプ２２Ａの先端
径よりも僅かに小さな先端形状を有し尖つている例えば
鉛筆キヤツプの様な治具３０で叩く（Ｙ方向の動作）こ
とにより行うことができる。As shown in FIG. 7, the step of forming the depression 11A at the tip of each of the bumps 22A (FIG. 4 (C)) is performed by making the tip of each bump 22A slightly smaller than the tip diameter of the bump 22A. It can be performed by hitting (movement in the Y direction) with a jig 30 having a small tip shape and being sharp, for example, a pencil cap.

【００２６】なお、理想的なくぼみ１１Ａの径は一般的
な導電粒子の径 5〔μm 〕に対しておよそ15〔μm 〕〜
20〔μm 〕であり、実際上、例えばバンプ１１の先端径
が40〔μm 〕の場合には鉛筆キヤツプの様な治具３０の
先端のＲ形状の径が20〔μm〕で、バンプ１１に治具３
０を押し当てる際の荷重を10〔gf〕とすることによつ
て、およそ10〔μm 〕のくぼみ１１Ａを形成することが
できる。Incidentally, the diameter of the ideal recess 11A is about 15 [μm] to 5 [μm] of general conductive particles.
In practice, for example, when the tip diameter of the bump 11 is 40 [μm], the radius of the R shape at the tip of the jig 30 such as a pencil cap is 20 [μm]. Jig 3
By setting the load at which 0 is pressed to 10 [gf], the depression 11A of approximately 10 [μm] can be formed.

【００２７】以上の構成において、このプリント回路基
板４Ａでは半導体チツプ１０のバンプ１１にくぼみ１１
Ａを設けたことにより、この半導体チツプ２をＡＣＦ３
を介してプリント配線基板８にフリツプチツプ実装する
際、半導体チツプ１０の各バンプ１１とプリント配線基
板８の対応するランド９間の隙間が小さくなる接続過程
で、半導体チツプ１０のバンプ１１のくぼみ１１Ａが直
下の導電粒子２を捕獲したままギヤツプが小さくなる。In the above configuration, the printed circuit board 4A has the recesses 11 formed on the bumps 11 of the semiconductor chip 10.
By providing A, this semiconductor chip 2 is
When the flip chip is mounted on the printed wiring board 8 through the via hole, the gap 11A between the bumps 11 of the semiconductor chip 10 and the corresponding land 9 of the printed wiring board 8 is reduced during the connection process. The gap is reduced while capturing the conductive particles 2 immediately below.

【００２８】従つてこの半導体チツプ１０ではＡＣＦ３
を介してプリント配線基板８上に実装する際、半導体チ
ツプ１０のバンプ１１がＡＣＦ３内の導電粒子２を押し
退け、半導体チツプ１０のバンプ１１とプリント配線基
板８の対応するランド９間の隙間に導電粒子２が挟まれ
なかつたり、挟まる数が少なくなる恐れはなく、確実に
複数の導電粒子２を挟み込み半導体チツプ１０の各バン
プ１１とプリント配線基板８の対応するランド９との間
の導通を得ることができる。Therefore, in this semiconductor chip 10, ACF3
When the semiconductor chip 10 is mounted on the printed wiring board 8 via the semiconductor chip 10, the bumps 11 of the semiconductor chip 10 push away the conductive particles 2 in the ACF 3, and a gap is formed between the bumps 11 of the semiconductor chip 10 and the corresponding lands 9 of the printed wiring board 8. There is no danger that the particles 2 will be interposed or the number of interposed particles will not be reduced, and the conduction between the bumps 11 of the semiconductor chip 10 and the corresponding lands 9 of the printed wiring board 8 will be reliably obtained by interposing the plurality of conductive particles 2. be able to.

【００２９】以上の構成によれば、半導体チツプ１０の
バンプ２２Ａの先端にくぼみ１１Ａを設けるようにした
ことにより、プリント配線基板８上に半導体チツプ１０
をＡＣＦ３を用いてフリツプチツプ実装する際に、当該
半導体チツプ１０のバンプ１１のくぼみ１１Ａが直下の
プリント配線基板８のランド９との間にある導電粒子２
を捕獲したまま半導体チツプ１０の各バンプ１１とプリ
ント配線基板８の対応するランド９との間のギヤツプを
狭めることができる。According to the above configuration, the recess 11A is provided at the tip of the bump 22A of the semiconductor chip 10, so that the semiconductor chip 10 is provided on the printed wiring board 8.
When flip chip mounting is performed using the ACF 3, the recesses 11 A of the bumps 11 of the semiconductor chip 10 have the conductive particles 2 between the lands 9 of the printed wiring board 8 immediately below.
The gap between each bump 11 of the semiconductor chip 10 and the corresponding land 9 of the printed wiring board 8 can be narrowed while capturing.

【００３０】かくするにつき半導体チツプ１０のバンプ
１１がＡＣＦ３内の導電粒子２を押し退け、半導体チツ
プ１０のバンプ１１とプリント配線基板８のランド９間
の隙間に導電粒子２が挟まれなかつたり、挟まる数が少
なくなる恐れを格段的に減少させることができ、信頼性
高く半導体チツプ１０をプリント配線基板８上にフリツ
プチツプ実装することができる。As a result, the bumps 11 of the semiconductor chip 10 push away the conductive particles 2 in the ACF 3, and the conductive particles 2 are caught or caught in the gaps between the bumps 11 of the semiconductor chip 10 and the lands 9 of the printed wiring board 8. The possibility of the number being reduced can be greatly reduced, and the semiconductor chip 10 can be flip-chip mounted on the printed wiring board 8 with high reliability.

【００３１】なお上述の実施の形態においては、専用治
具３０を鉛筆キヤツプの様な場合について述べていた
が、本発明はこれに限らず、治具としては先端径がバン
プ２２Ａの先端径よりも僅かに小さく、突起状であるも
のを広く適用し得る。In the above-described embodiment, the case where the exclusive jig 30 is like a pencil cap is described. However, the present invention is not limited to this, and the jig has a tip diameter smaller than that of the bump 22A. Is slightly smaller, and those having a protruding shape can be widely applied.

【００３２】また上述の実施の形態においては、半導体
チツプ１０のバンプ１１のくぼみ１１Ａをレベリング後
に形成するようにした場合について述べたが、本発明は
これに限らず、レベリング工具（図示せず）に半導体チ
ツプ１０のバンプ２２Ａの先端径よりも僅かに小さく、
突起しているものを設け、レベリングと同時にバンプ２
２Ａにくぼみ１１Ａを形成するようにしても良い。In the above-described embodiment, the case where the recess 11A of the bump 11 of the semiconductor chip 10 is formed after leveling has been described. However, the present invention is not limited to this, and a leveling tool (not shown) is used. The diameter is slightly smaller than the tip diameter of the bump 22A of the semiconductor chip 10;
Provide a protruding part, and bump 2 at the same time as leveling.
The depression 11A may be formed in 2A.

【００３３】さらに上述の実施の形態においては、半導
体チツプ１０の実装面１０Ａに所定パターンで形成され
た接続パツド６に対して金（Ａｕ）ワイヤ２１に基づい
てバンプ２２を形成した場合について述べたが、本発明
はこれに限らず、金（Ａｕ）ワイヤ以外にも金を含む金
属（例えば、金とはんだとパラジウムの合金等）や金以
外のはんだ等の金属のワイヤに基づいてバンプ２２を形
成するようにしても良い。Further, in the above-described embodiment, the case where the bump 22 is formed based on the gold (Au) wire 21 on the connection pad 6 formed in a predetermined pattern on the mounting surface 10A of the semiconductor chip 10 has been described. However, the present invention is not limited to this, and the bump 22 may be formed based on a metal wire such as a metal containing gold (for example, an alloy of gold, solder and palladium) or a solder other than gold other than the gold (Au) wire. It may be formed.

【００３４】さらに上述の実施の形態においては、半導
体チツプ１０のバンプ１１をボールバンプ法により形成
するようにした場合について述べたが、本発明はこれに
限らず、バンプ１１の形成方法としてはこの他種々の方
法を適用することができる。さらに上述の実施の形態に
おいては、異方性導電材としてＡＣＦ３を用いた場合に
ついて述べたが、本発明はこれに限らず、要は、絶縁材
内に複数の導電粒子２が分散して混入されている異方性
導電材料であれば、この他種々の異方性導電材を適用し
得る。Further, in the above embodiment, the case where the bumps 11 of the semiconductor chip 10 are formed by the ball bump method has been described. However, the present invention is not limited to this, and the method of forming the bumps 11 is not limited to this. Various other methods can be applied. Further, in the above-described embodiment, the case where ACF3 is used as the anisotropic conductive material has been described. However, the present invention is not limited to this, and the point is that a plurality of conductive particles 2 are dispersed and mixed in the insulating material. As long as the anisotropic conductive material is used, various other anisotropic conductive materials can be applied.

【００３５】さらに上述の実施の形態においては、本発
明を半導体チツプ１０及びその製造方法並びにその実装
方法に適用するようにした場合について述べたが、本発
明はこれに限らず、その他種々の表面実装型電子部品及
びその製造方法並びにその実装方法に広く適用し得る。Further, in the above-described embodiment, a case has been described in which the present invention is applied to the semiconductor chip 10, a method for manufacturing the same, and a method for mounting the same. However, the present invention is not limited to this, and the present invention is not limited to this. The present invention can be widely applied to a mounting type electronic component, a manufacturing method thereof, and a mounting method thereof.

【００３６】[0036]

【発明の効果】上述のように本発明によれば、表面実装
型電子部品に信号入出力用の電極と、電極上に形成され
た先端部に所定の大きさのくぼみを有する突起電極とを
設けるようにしたことにより、表面実装型電子部品を異
方性導電材を介してプリント配線基板上に実装する際、
突起電極のくぼみが異方性導電材内の導電粒子を捕獲し
た状態で当該突起電極とプリント配線基板の対応する電
極とのギヤツプを狭めることができ、かくして実装の信
頼性を向上し得る表面実装型電子部品を実現できる。As described above, according to the present invention, a signal input / output electrode and a protruding electrode having a recess of a predetermined size at the tip formed on the electrode are provided on the surface-mounted electronic component. By mounting, when mounting the surface-mounted electronic components on the printed wiring board via the anisotropic conductive material,
Surface mounting that can reduce the gap between the protruding electrode and the corresponding electrode of the printed wiring board in a state where the recess of the protruding electrode captures the conductive particles in the anisotropic conductive material, thus improving the reliability of mounting. Type electronic parts can be realized.

【００３７】また表面実装型電子部品の製造方法におい
て、表面実装型電子部品の電極上に突起電極を形成する
第１の工程と、突起電極の先端部に所定の大きさのくぼ
みを形成する第２の工程とを設けるようにしたことによ
り、突起電極のくぼみが異方性導電材内の導電粒子を捕
獲した状態で当該突起電極とプリント配線基板の対応す
る電極とのギヤツプを狭めることができ、かくして実装
の信頼性を向上し得る表面実装型電子部品の製造方法を
実現できる。In the method of manufacturing a surface-mounted electronic component, a first step of forming a protruding electrode on an electrode of the surface-mounted electronic component and a second step of forming a recess having a predetermined size at the tip of the protruding electrode are provided. By providing the second step, the gap between the projecting electrode and the corresponding electrode of the printed wiring board can be narrowed in a state where the depressions of the projecting electrode capture the conductive particles in the anisotropic conductive material. Thus, it is possible to realize a method of manufacturing a surface mount electronic component capable of improving the reliability of mounting.

【００３８】さらに表面実装型電子部品をプリント配線
基板上に実装する実装方法において、表面実装型電子部
品の電極上に突起電極を形成する第１のステツプと、突
起電極の先端部に所定の大きさのくぼみを形成する第２
のステツプと、表面実装型電子部品を異方性導電材を介
してプリント配線基板上に実装する第３のステツプとを
設けるようにしたことにより、表面実装型電子部品をプ
リント配線基板上に実装する際、突起電極のくぼみが異
方性導電材内の導電粒子を捕獲した状態で当該突起電極
とプリント配線基板の対応する電極とのギヤツプを狭め
ることができ、かくして実装の信頼性を向上し得る表面
実装型電子部品を実現できる。Further, in a mounting method for mounting a surface-mounted electronic component on a printed wiring board, a first step of forming a protruding electrode on an electrode of the surface-mounted electronic component, and a predetermined size at a tip end of the protruding electrode. The second forming the depression
And a third step of mounting the surface-mounted electronic component on the printed wiring board via the anisotropic conductive material, thereby mounting the surface-mounted electronic component on the printed wiring board. In such a case, the gap between the projecting electrode and the corresponding electrode of the printed wiring board can be narrowed in a state where the depressions of the projecting electrode capture the conductive particles in the anisotropic conductive material, thus improving the reliability of mounting. The obtained surface mount electronic component can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本実施の形態による半導体チツプの構成を示す
部分的断面図である。FIG. 1 is a partial cross-sectional view showing a configuration of a semiconductor chip according to the present embodiment.

【図２】本実施の形態によるバンプの構成を示す端面図
である。FIG. 2 is an end view showing a configuration of a bump according to the present embodiment.

【図３】本実施の形態による半導体チツプをＡＣＦを用
いてプリント配線基板上に実装した状態を部分的に端面
をとつて示す端面図である。FIG. 3 is an end view showing a state where the semiconductor chip according to the present embodiment is mounted on a printed wiring board using an ACF, with a partial end face taken;

【図４】本実施の形態による半導体チツプの製造工程の
説明に供する部分的断面図である。FIG. 4 is a partial cross-sectional view for explaining a manufacturing step of the semiconductor chip according to the present embodiment;

【図５】ボールバンプ法によるバンプの形成工程の説明
に供する部分的断面図である。FIG. 5 is a partial cross-sectional view for explaining a bump forming step by a ball bump method.

【図６】バンプのレベリング工程前後を示す部分的断面
図である。FIG. 6 is a partial cross-sectional view showing before and after a bump leveling step.

【図７】くぼみ加工工程の説明に供する部分的断面図で
ある。FIG. 7 is a partial cross-sectional view for explaining a hollowing step.

【図８】ＡＣＦの構成の説明に供する斜視図である。FIG. 8 is a perspective view for explaining the configuration of the ACF.

【図９】従来のＡＣＦを用いたフリツプチツプ実装法の
説明に供する部分的断面図である。FIG. 9 is a partial cross-sectional view for explaining a flip-chip mounting method using a conventional ACF.

【符号の説明】[Explanation of symbols]

１……ベースフイルム、２……導電粒子、３……ＡＣ
Ｆ、４、４Ａ……プリント回路基板、５、１０……半導
体チツプ、５Ａ、１０Ａ……実装面、６……パツド、
７、１１、２２、２２Ａ、２３……バンプ、８……プリ
ント配線基板、８Ａ……基板面、９……ランド、１１Ａ
……くぼみ、２０……キヤピラリ、２１……金属ワイ
ヤ、２１Ａ……金ボール、３０……治具。1 ... base film, 2 ... conductive particles, 3 ... AC
F, 4, 4A ... printed circuit board, 5, 10 ... semiconductor chip, 5A, 10A ... mounting surface, 6 ... pad,
7, 11, 22, 22A, 23 ... bump, 8 ... printed wiring board, 8A ... board surface, 9 ... land, 11A
... hollow, 20 ... capillary, 21 ... metal wire, 21A ... gold ball, 30 ... jig.

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】信号入出力用の電極と、 上記電極上に形成された先端部に所定の大きさのくぼみ
を有する突起電極とを具えることを特徴とする表面実装
型電子部品。1. A surface-mounted electronic component comprising: a signal input / output electrode; and a protruding electrode having a recess of a predetermined size at a tip portion formed on the electrode. 【請求項２】表面実装型電子部品の電極上に突起電極を
形成する第１の工程と、 上記突起電極の先端部に所定の大きさのくぼみを形成す
る第２の工程とを具えることを特徴とする表面実装型電
子部品の製造方法。2. A method according to claim 1, further comprising: a first step of forming a protruding electrode on the electrode of the surface-mounted electronic component; and a second step of forming a recess having a predetermined size at the tip of the protruding electrode. A method for producing a surface-mounted electronic component, comprising: 【請求項３】上記突起電極は、金属ワイヤの先端を上記
表面実装型電子部品の上記電極上に接合した後、当該金
属ワイヤを引きちぎることにより形成され、 上記突起電極の上記くぼみは、上記引きちぎられた金属
ワイヤの先端の高さを揃えるレベリング時に形成された
ことを特徴とする請求項２に記載の表面実装型電子部品
の製造方法。3. The protruding electrode is formed by joining a tip of a metal wire onto the electrode of the surface-mounted electronic component and then tearing off the metal wire. 3. The method for manufacturing a surface-mounted electronic component according to claim 2, wherein the metal wire is formed at the time of leveling for equalizing the heights of the tips of the metal wires. 【請求項４】表面実装型電子部品をプリント配線基板上
に実装する表面実装型電子部品の実装方法において、 上記表面実装型電子部品の電極上に突起電極を形成する
第１のステツプと、 上記突起電極の先端部に所定の大きさのくぼみを形成す
る第２のステツプと、 上記表面実装型電子部品を異方性導電材を介して上記プ
リント配線基板上に実装する第３のステツプとを具える
ことを特徴とする表面実装型電子部品の実装方法。4. A method of mounting a surface-mounted electronic component on a printed wiring board, the method comprising the steps of: forming a projecting electrode on an electrode of the surface-mounted electronic component; A second step of forming a recess of a predetermined size at the tip of the protruding electrode; and a third step of mounting the surface-mounted electronic component on the printed wiring board via an anisotropic conductive material. A method for mounting a surface mount electronic component, comprising: 【請求項５】上記突起電極は、金属ワイヤの先端を上記
表面実装型電子部品の上記電極上に接合した後、当該金
属ワイヤを引きちぎることにより形成され、 上記突起電極の上記くぼみは、上記引きちぎられた金属
ワイヤの先端の高さを揃えるレベリング時に形成された
ことを特徴とする請求項４に記載の表面実装型電子部品
の実装方法。5. The protruding electrode is formed by joining a tip of a metal wire onto the electrode of the surface-mounted electronic component and then tearing off the metal wire. 5. The method for mounting a surface-mounted electronic component according to claim 4, wherein the mounting is performed at the time of leveling for adjusting the heights of the tips of the formed metal wires.
JP14912697A 1997-06-06 1997-06-06 Surface-mount electronic part, manufacture and mounting thereof Pending JPH10340906A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14912697A JPH10340906A (en) 1997-06-06 1997-06-06 Surface-mount electronic part, manufacture and mounting thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14912697A JPH10340906A (en) 1997-06-06 1997-06-06 Surface-mount electronic part, manufacture and mounting thereof

Publications (1)

Publication Number Publication Date
JPH10340906A true JPH10340906A (en) 1998-12-22

Family

ID=15468304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14912697A Pending JPH10340906A (en) 1997-06-06 1997-06-06 Surface-mount electronic part, manufacture and mounting thereof

Country Status (1)

Country Link
JP (1) JPH10340906A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105405825A (en) * 2015-12-09 2016-03-16 南通富士通微电子股份有限公司 Chip on film package structure
CN105551987A (en) * 2015-12-09 2016-05-04 南通富士通微电子股份有限公司 COF (Chip on Flex) packaging method
CN105551986A (en) * 2015-12-09 2016-05-04 南通富士通微电子股份有限公司 COF (Chip on Flex) packaging method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105405825A (en) * 2015-12-09 2016-03-16 南通富士通微电子股份有限公司 Chip on film package structure
CN105551987A (en) * 2015-12-09 2016-05-04 南通富士通微电子股份有限公司 COF (Chip on Flex) packaging method
CN105551986A (en) * 2015-12-09 2016-05-04 南通富士通微电子股份有限公司 COF (Chip on Flex) packaging method

Similar Documents

Publication Publication Date Title
JPH07221104A (en) Semiconductor device manufacture thereof and mask for forming electrode pin and testing wherein the mask for forming electrode pin is used
JP2001267359A (en) Method for manufacturing semiconductor device and semiconductor device
JPH11312711A (en) Method for connecting electronic component
JPH09162230A (en) Electronic circuit device and its manufacturing method
JPH10340906A (en) Surface-mount electronic part, manufacture and mounting thereof
JP3981817B2 (en) Manufacturing method of semiconductor device
JPH0523887A (en) Method for forming metal ball
JPS63122133A (en) Electrically connecting method for semiconductor chip
JP2638557B2 (en) Semiconductor device
JPH09172021A (en) Semiconductor device and manufacturing method and packaging method thereof
JP2003031613A (en) Flip chip mounting body and method of mounting the same
JP3180041B2 (en) Connection terminal and method of forming the same
JP3851585B2 (en) Connection method of bare chip semiconductor element to printed wiring board
JPH0799202A (en) Capillary for wire bonding device and method for forming electric connection bump using the same
JP3319269B2 (en) Electronic component joining method
JP4934831B2 (en) Manufacturing method of semiconductor package
JP3335562B2 (en) Semiconductor chip connection bump forming method
JPH10233401A (en) Semiconductor device
JP2000332394A (en) Substrate for mounting electronic parts and method of producing the same
JP3446608B2 (en) Semiconductor unit
JP3855523B2 (en) Connection method between IC chip and circuit board
JP3202138B2 (en) Method of forming bump electrode
JPH11284019A (en) Semiconductor device
JPH06151440A (en) Semiconductor device, its manufacture, and its packaging body
JP2002270629A (en) Electronic component and manufacturing method therefor