JP2000223649A - Chip scale ic package for multichip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a very small chip scale IC package only slightly larger than a chip contained therein by filling the gap between chips with an insulating material to cover the element surface of two chips while exposing the back face thereof thereby forming an insulation compound. SOLUTION: First and second chips 50, 52 have element surfaces 60, 62 facing the opposite side face of a film carrier 58 and bonding pads of two chips 50, 52 are connected electrically with a conductive wire 56 on a film carrier 58 through first and second conductive protrusions 64, 66. An insulating material fills the space between two chips 50, 52 to form an insulation compound 68. The insulation compound 68 seals only the conductive protrusions 64, 66 and the element surfaces 60, 62 of the chips 50, 52 such that the back faces 70, 72 of the first and second chips 50, 52 are exposed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit (IC).
More particularly with respect to packaging technology, it relates to a multi-chip chip scale IC package in which two chips can be incorporated, the overall dimensions of which are only slightly larger than the dimensions of the chip encapsulated therein. .

[0002]

BACKGROUND OF THE INVENTION In the manufacture of integrated circuit (IC) products,
Three steps are involved: (1) pretreating the semiconductor wafer, (2) forming circuit elements such as metal oxide semiconductor transistors and multilayer interconnects on the wafer, and (3) packaging the manufactured chip. . The primary goal of packaging technology is to minimize the overall dimensions of the final IC package. Conventional packaging technologies that can achieve this goal include, for example,
Scale package (CSP) and multi-chip
Module (MCM) technology is included. For submicron fabrication below 0.18 μm, IC package size is a major concern providing high integration. To increase the degree of integration, IC packages are now usually
Not only one chip but two or more chips are incorporated inside. Such an IC package is conventionally called a multi-chip IC package. The multi-chip IC package consists of a processor chip and a memory chip (DR
AM chips or flash memory chips, etc.), or logic and memory chips together. The use of multi-chip IC packaging technology not only helps to reduce manufacturing costs, but also shortens the signal transmission path between the chip and external circuits without adding special assembly processes,
Improve chip performance. The multi-chip IC package technology is also applied to, for example, a multi-chip system having the following changeable functions and operating frequencies.

[0003] 1. A system comprising a memory chip, a microprocessor, resistors, capacitors and inductors.

[0004] 2. Memory chip (DRAM), logic circuit chip and memory chip (flash memory)
A system comprising:

[0005] 3. Analog chips, logic circuit chips,
A system comprising a memory chip (including DRAM, SRAM, flash memory), resistors, capacitors and inductors.

FIG. 1 is a cross-sectional view of a conventional IC package packaged by MCM technology. This type of IC package is conventionally called a multi-chip IC package. As shown in the figure, this IC package is configured on a substrate 10 which is a multi-stage PCB.
A plurality of chips 12 are mounted on the substrate 10 by an insulating adhesive 14. Wire bonding techniques are used to electrically connect the chip 12 to a plurality of connections (not shown) on the substrate 10 through a plurality of bonding wires 16. Further, a flip chip or control collapse chip connection technique (C4) is used, and the chip 12 may be electrically connected to the substrate 10 by a conductive protrusion (bump) (not shown). After the chip 12 is set at a fixed position on the substrate 10, the resin compound 1
8 are formed and seal the chip 12. Thereafter, a plurality of tin balls 20 are placed in a ball grid array (BG).
A) It is placed below the substrate 10 using a technique. The tin balls 20 are used for bonding the manufactured IC package to a circuit board (not shown) and electrically connecting the IC package to the circuit board (not shown).

[0007]

However, one disadvantage of the multi-chip IC package of FIG. 1 is that its overall dimensions are quite large due to the fact that the chips 12 are arranged side by side on the same plane. is there. Further, the chip 12
The signal transmission path between the circuit and the external circuit connected via the tin ball 20 is also considerably long. By using C4 technology, the package size can be reduced,
In addition, the need to use proven high quality die (KGD) technology makes testing difficult to perform. As a result, the yield decreases and the cost increases. The use of KGD technology significantly increases the cost of the package.

A solution for reducing the size of a multi-chip IC package is disclosed in US Pat. No. 5,331,235, which greatly reduces the overall package size by placing the chips face-to-face. Things. The disclosed package structure is schematically illustrated in FIG. As shown, this face-to-face multi-chip IC package consists of two chips 3 positioned face to face using tape automated bonding (TAB) technology.
It is designed to incorporate 0,32. An internal lead bonding (ILB) process is performed by using the conductive protrusions 34, 36 for the two chips 30, 32, and the bonding bonding on the chips 30, 32 is performed.
Pads (not shown) are glued and electrically connected to corresponding locations on the film carrier 38. On the other hand, film
An external lead bonding (OLB) process is performed by connecting the carrier 38 to the lead frame 40. Further, the tin ball 42 is provided with two chips 3.
0, 32 and interconnects the two chips 30, 32. Finally, a resin compound 44 is formed, which seals the entire two chips 30, 32, the entire film carrier 38 and a part of the lead frame 40. This completes the packaging of the chips 30, 32 into an IC package.

However, one disadvantage of the multi-chip IC package of FIG. 2 is that the use of TAB technology significantly lengthens the signal transmission path between the chips 30, 32 and external circuits (not shown). It is. Further, a resin compound 44 is used to encapsulate the chips 30 and 32.
, The overall dimensions of the final IC package are significantly larger, and the IC package is not
The efficiency of heat dissipation is low.

The present invention relates to a multi-chip chip whose dimensions are only slightly larger than the chip housed therein.
A scale IC package is provided.

[0011] The signal transmission path between the encapsulated chip and the external circuit is shortened as compared with the prior art. Furthermore, the heat dissipation efficiency is improved compared to the prior art.

Furthermore, the chip scale IC package for a multi-chip provided by the present invention can be used without the need to use the KGD technology as in the prior art.
Can be tested directly during the process.

[0013]

[MEANS FOR SOLVING THE PROBLEMS] Multi-chip chip
A scale IC package is provided. According to the present invention, a flip chip or control collapse
Using chip connection technology, two chips are placed face-to-face on a film carrier, where conductive protrusions are used to glue the two chips to the corresponding conductive wires on the insulating film, Connection. Further, an insulating compound is formed from the insulating material filled between the two chips so as to cover the element surfaces of the two chips while exposing the back surfaces thereof. With this arrangement, the signal transmission path between the chip and the external circuit is shorter than in the prior art, and the performance of the chip is improved.

Further, the multichip chip of the present invention
Scale IC package is installed on a circuit board
A substrate can be constructed, which allows for high heat dissipation efficiency by coupling the back of one chip to printed circuit wiring on a circuit board and the back of another chip to a heat dissipation device. Further, the insulating film is optionally provided with a plurality of fixed openings filled with insulating material when the insulating compound is formed, which helps to secure the insulating compound more firmly to the film carrier. Therefore, the quality of the package is improved and the reliability is improved.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Package of Multi-chip IC
The process usually involves (1) choosing an appropriate carrier,
Three steps are involved: (2) electrically connecting the chip to the selected carrier, and (3) performing a compound molding process to form an insulating compound and enclose the chip. In the first stage, the carrier is a lead frame, film carrier or printed circuit board (PC
B). When using TAB technology, it is preferred to use a film carrier. In the second stage, the technology used is wire bonding technology or TAB
Technology, or flip chip or control collapse chip connection (C4) technology. In a third step, a resin or ceramic is used to form an insulating compound, and the chip is sealed in an IC package.

FIG. 3 shows a chip for a multichip according to the present invention.
It is sectional drawing of a scale IC package. In this preferred embodiment, a multi-chip chip scale IC package incorporating two chips 50, 52 therein is used, but its overall dimensions are slightly larger than the chips 50, 52 incorporated therein. Only. Chip 5
Numerals 0 and 52 are almost the same size and are some kind of integrated circuit such as a DRAM (Dynamic RAM) chip, a ROM (Read Only Memory) chip, a logic circuit chip and an analog circuit chip. According to the present invention, a film carrier 58 comprising an insulating film 54 and a plurality of conductive wires 56 is used to place the chips 50,52.

The first chip 50 has an element surface 60,
Various circuit elements (not shown) are formed thereon. The second chip 52 has an element surface 62, on which various circuit elements (not shown) are formed. The two chips 50, 52 are arranged facing each other, and the element surface 60 of the first chip 50 faces the element surface 62 of the second chip 52. The plurality of first conductive protrusions 64 form the first chip 50.
And one of bonding pads (not shown) on the element surface 60 of the first chip 50.
And are electrically connected. Similarly, the plurality of second conductive protrusions 66 are formed on the element surface 6 of the second chip 52.
2 and each is bonded and electrically connected to one of the bonding pads (not shown) on the element surface 62 of the second chip 52. Element surface 60 of first chip 50
And the device surface 62 of the second chip 52 is disposed opposite the side surface of the film carrier 58, and the bonding pads (not shown) of the two chips 50, 52 have first and second conductive layers. It is electrically connected to the conductive wire 56 on the film carrier 58 via the protrusions 64, 66.

In the compound molding process, an insulating material, such as epoxy, fills the space between the two chips 50, 52 to form an insulating compound (insulation encapsulation) 68. An insulating compound 68 encapsulates only the conductive protrusions 64, 66 and the element surfaces 60, 62 of the two chips 50, 52, the back surface 70 of the first chip 50 and the second chip 52.
It is a feature of the present invention that it is formed in such a manner as to expose the back surface 72 thereof. This completes the assembly of the multi-chip chip scale IC package. As illustrated in FIG. 3, the final IC package is very small in height and the overall package dimensions are very small. Further, since the back surfaces 70 and 72 of the chips 50 and 52 are exposed, heat dissipation from the chips 50 and 52 is promoted.

In accordance with the present invention, the signal transmission path between chips 50, 52 and external circuitry (not shown) only includes conductive wires 56 and conductive protrusions 64, 66, which is significantly shorter than in the prior art. The subsequent process of bending the conductive wires 56 and the installation of the completed IC package on a substrate (not shown) by surface mount technology (SMT) is conventional and will not be described in detail here.

The film package of the IC package of the present invention shown in FIG. 3 using various types of film carriers.
Carriers 58 can be implemented, each of which is shown in FIGS.

Referring to FIG. 4, the film carrier 5
A first example of 8 is a long lead cantilevered film carrier comprising an insulating film 54 on which a plurality of conductive wires 56, such as copper wires, are placed.
Two rows of guide holes 80 are formed at the end of the insulating film 54 to facilitate automatic packaging. The conductive wires 56 each have external leads attached to the insulating film 54.

Referring to FIG. 5, the film carrier 5
The second example of FIG. 8 differs from the first example of FIG. 4 only in that a free margin ring 82 is provided and supports the inner lead portion of the conductive wire 56. This free margin ring 8
The provision of 2 helps to secure the conductive wire 56 more firmly in place.

Referring to FIG. 6, the film carrier 5
The third example of FIG. 8 differs from the previous two examples of FIGS. 4 and 5 only in that a corner support ring 84 is provided for supporting the inner lead portion of the conductive wire 56. This corner support ring 84 is connected to the insulating film 54, but differs from the free allowance ring 82 shown in FIG. 5 in that the free allowance ring 82 shown in FIG. 5 is not. The provision of this corner support ring 84 helps to secure the conductive wire 56 more securely in place.

Referring to FIG. 7, the film carrier 5
The fourth example of 8 is designed according to the invention, in particular for the purpose of enhancing the fixing of the insulating compound 68 to the film carrier 58. The fourth example of the film carrier 58 is substantially similar in structure to the third example shown in FIG. 6 except that a plurality of fixed openings 86 are formed in the corner support ring 84. The fixed opening 86 can be any shape, such as a cross, a circle or a square. For example, in the embodiment of FIG. 7, the fixed opening 86 has a cross shape.

FIG. 8 is a cross-sectional view of the IC package of the present invention when the fourth example of the film carrier 58 shown in FIG. 7 is used. The area enclosed by the dashed square indicated by reference numeral 88 in FIG. 7 is the area enclosed by the insulating compound 68. Insulation is in this range 88
To form the insulating compound 68, it also fills the fixed opening 86 of the corner support ring 84 so that the resulting insulating compound 68
The carrier 58 can be more securely fixed. With the fixed compound 68, the chips 50 and 52 sealed therein are fixed in position well.

FIG. 9 shows a circuit board 10 constituting an IC board.
FIG. 2 is a cross-sectional view showing the installation of the multi-chip chip scale IC package of the present invention at 0. The circuit board 100 includes a board 102 and a plurality of printed circuit wirings 1 on the board 102.
04 and 106. The substrate 102 is, for example, a multi-stage P
It is a CB substrate. According to the present invention, a chip scale IC package for a multi-chip is formed by connecting conductive wires 56 on a film carrier 58 to a printed circuit wiring 10 on a circuit board 100 by, for example, surface mounting technology (SMT).
4 and installed on the circuit board 100. Further, the rear surface 72 of the second chip 52 is disposed so as to be in contact with the printed circuit wiring 106 connected to the ground wiring (not shown). Form a radiation path. Further, the heat dissipation device 108 can be installed on the back surface 70 of the first chip 50 to form another heat dissipation path. Therefore, the heat dissipation efficiency of the multi-chip chip scale IC package of the present invention is considerably better than the prior art.

Another advantage of the present invention is that, since the present invention is based on a film carrier, it does not require the use of KGD technology as in the prior art, so that the package
It can be tested directly during the process. Accordingly, the manufacturing cost of the multi-chip chip scale IC package of the present invention is reduced.

[0028]

In conclusion, the chip scale IC package for a multichip of the present invention has the following advantages over the prior art.

First, the overall dimensions of the multi-chip chip scale IC package are only slightly larger than the dimensions of the chip encapsulated therein, and the IC package is very small.

Second, according to the present invention, the signal transmission path between the chip and the external circuit is shorter than that of the prior art, and the performance of the chip is improved.

Third, in the present invention, the back surface of a chip in an IC package is exposed, the back surface of one chip is connected to printed circuit wiring on a circuit board, and the back surface of another chip is connected to a heat dissipation device. This arrangement allows for high heat dissipation efficiency.

Fourth, the present invention allows testing of IC packages manufactured during the packaging process without having to use KGD technology. Therefore, the manufacturing cost of the multi-chip chip scale IC package of the present invention is reduced as compared with the prior art.

While the invention has been described by way of exemplary preferred embodiments, it should be understood that the scope of the invention is not limited to the embodiments described above. On the contrary, various modifications and similar arrangements are included within the scope of the invention. Therefore, the appended claims should be construed broadly to include all such modifications and similar devices.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a conventional multichip module IC package.

FIG. 2 is a cross-sectional view of a conventional facing multichip IC package.

FIG. 3 is a chip scale IC for a multichip according to the present invention.
It is sectional drawing of a package.

FIG. 4 is a chip scale IC for a multichip according to the present invention.
FIG. 3 is a diagram showing a film carrier used in a package.

FIG. 5 is a chip scale IC for a multichip of the present invention.
FIG. 3 is a diagram showing a film carrier used in a package.

FIG. 6 is a chip scale IC for a multichip according to the present invention.
FIG. 3 is a diagram showing a film carrier used in a package.

FIG. 7 is a chip scale IC for a multichip of the present invention.
FIG. 3 is a diagram showing a film carrier used in a package.

FIG. 8 is a cross-sectional view of the IC package of the present invention when utilizing a film carrier of the type shown in FIG.

FIG. 9 shows a multichip chip of the present invention on a circuit board.
It is sectional drawing which shows installation of a scale IC package.

[Explanation of symbols]

 50,52 Chip 54 Insulating film 56 Conductive wire 58 Film carrier 64,66 Conductive protrusion 68 Insulating compound

Claims (12)

[Claims] 1. A chip scale IC package for a multichip, comprising: a film carrier including an insulating film and a plurality of conductive wires provided on the insulating film; and a plurality of first conductive protrusions. A first chip electrically connected to a corresponding conductive wire on the insulating film, and a first chip electrically connected to the corresponding conductive wire on the insulating film by a plurality of second conductive protrusions. A second chip disposed on the opposite side of the insulating film to face the first chip, and covering the element surfaces of the first and second chips while keeping their back surfaces A chip scale IC package for a multi-chip, comprising: an insulating sealing portion having an insulating material formed between the first and second chips so as to be exposed. 2. The multi-chip chip scale IC package according to claim 1, wherein said film carrier has a free margin ring for supporting an inner lead portion of said conductive wire. Chip scale IC package. 3. The multi-chip chip scale IC package according to claim 1, wherein said film carrier has a corner support ring for supporting an inner lead portion of said conductive wire. Chip scale IC package. 4. The chip scale IC package for a multi-chip according to claim 3, wherein said insulating sealing portion is formed in order to promote fixing of said insulating sealing portion to said film carrier. At least one fixed opening filled with an insulating material is formed in said insulating film.
C package. 5. The multi-chip chip scale IC package according to claim 1, wherein when the multi-chip chip scale IC package is mounted on a circuit board, the back surface of the second chip is the circuit. A chip-scale IC package for a multi-chip, which is in contact with a printed circuit wiring on a substrate. 6. The multi-chip chip scale IC according to claim 5, wherein a heat dissipation device is provided on the back surface of the first chip. package. 7. An IC substrate, comprising: a substrate; a plurality of printed circuit wirings formed on the substrate; and a multi-chip chip scale IC package installed on the substrate. Tips for
The scale IC package is a film carrier including an insulating film and a plurality of conductive wires provided on the insulating film,
A film carrier wherein the conductive wires are electrically connected to a corresponding one of the printed circuit traces on the substrate; and a plurality of first conductive protrusions to a corresponding conductive wire on the insulating film. A first chip that is electrically connected, and a second chip that is electrically connected to a corresponding conductive wire on the insulating film by a plurality of second conductive protrusions, A second chip disposed opposite the first chip on the opposite side; and the first and second chips so as to cover the element surfaces of the first and second chips while exposing their back surfaces. An IC substrate comprising: an insulating sealing portion in which an insulating material is formed between chips. 8. The IC substrate according to claim 7, wherein said film carrier has a free margin ring for supporting an inner lead portion of said conductive wire. 9. The IC board according to claim 7, wherein said film carrier has a corner support ring for supporting an inner lead portion of said conductive wire. 10. The IC substrate according to claim 9, wherein
When forming the insulating seal, at least one fixing opening filled with the insulating material is formed in the insulating film to facilitate fixing the insulating seal to the film carrier. An IC substrate characterized by the above-mentioned. 11. The IC substrate according to claim 7, wherein
An IC substrate, wherein when the chip scale IC package for a multichip is mounted on a circuit board, the back surface of the second chip contacts printed circuit wiring on the circuit board. 12. The IC substrate according to claim 11, wherein a heat dissipation device is provided on the back surface of the first chip.