JPH09135073A - Method of forming solder bump - Google Patents

Method of forming solder bump

Info

Publication number
JPH09135073A
JPH09135073A JP7292399A JP29239995A JPH09135073A JP H09135073 A JPH09135073 A JP H09135073A JP 7292399 A JP7292399 A JP 7292399A JP 29239995 A JP29239995 A JP 29239995A JP H09135073 A JPH09135073 A JP H09135073A
Authority
JP
Japan
Prior art keywords
solder
circuit board
bumps
electrode terminals
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7292399A
Other languages
Japanese (ja)
Inventor
Yoshihisa Takayama
佳久 高山
Kenji Morimoto
謙治 森本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7292399A priority Critical patent/JPH09135073A/en
Publication of JPH09135073A publication Critical patent/JPH09135073A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/38Effects and problems related to the device integration
    • H01L2924/384Bump effects
    • H01L2924/3841Solder bridging
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3485Applying solder paste, slurry or powder

Landscapes

  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To efficiently form fine bumps in sufficient level and even composition and shape at low cost by providing the three steps as follows, i.e., the first step of forming solder resist having aperture part, the second step of burying creamy solder in the aperture part and the third step of forming solder bumps only on electrode terminals. SOLUTION: A circuit board 5 made of glass epoxy wherein electrode terminals 2 are formed in the aperture part 1 of a solder resist 4 not to be in contact with the two sides of a solder resist 4 is prepared. Next, creamy solder is buried in the aperture part 1 of the solder resist 4 by sliding a squeegee. Next, the melted solder forms protruded electrode on the electrode terminals 2 by the surface tension thereof by heating the circuit board 5 using an infrared reflow furnace in nitrogen atmosphere so as to form solder bumps 3 by cooling down step for solidification. Finally, the electrodes of semiconductor chips and the solder bumps 3 formed on the circuit board 5 are aligned with one another.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体チップを回
路基板上に固定するため、回路基板に形成する半田バン
プの形成方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming solder bumps on a circuit board for fixing a semiconductor chip on the circuit board.

【0002】[0002]

【従来の技術】半導体チップをフェイスダウンの状態で
回路基板に取り付け、これと同時に、半導体チップと回
路基板との間の電気的接続をも行うフリップチップ実装
方式は、量産性が高く、接続信頼性の高い方式として知
られている。
2. Description of the Related Art A flip chip mounting method, in which a semiconductor chip is mounted face down on a circuit board, and at the same time, electrical connection between the semiconductor chip and the circuit board is performed, has high mass productivity and connection reliability. It is known as a highly effective method.

【0003】このようなフリップチップ実装方式を採用
するときには、半導体チップ及び回路基板の電極端子上
に組成及び形状が均一な多数の半田バンプを形成する必
要があり、このような半田バンプを低コストで能率良く
形成する方法が要求されている。
When adopting such a flip chip mounting method, it is necessary to form a large number of solder bumps having a uniform composition and shape on the electrode terminals of the semiconductor chip and the circuit board, and such solder bumps can be manufactured at low cost. Therefore, there is a demand for an efficient method of forming.

【0004】半田バンプを形成する方法として、電気メ
ッキの原理により電解液中にて半田の成分イオンを半導
体チップの電極端子上に付着させるプレイティング法、
真空中にて半田成分原子を蒸発させ、電極端子上に付着
させる蒸着法、ワイヤボンディングに類似した方式を用
いて半田線を電極端子に融着させた後にこれを切断する
融着法等が知られているが、上記要求を満足させるもの
ではなかった。
As a method of forming solder bumps, a plating method in which component ions of solder are attached to electrode terminals of a semiconductor chip in an electrolytic solution by the principle of electroplating,
Vapor deposition method that evaporates solder component atoms in a vacuum and deposits them on electrode terminals, fusion method that fuses solder wires to electrode terminals using a method similar to wire bonding and then cuts this is known. However, it does not satisfy the above requirements.

【0005】一方、滴下法は溶融半田を用いることによ
り、組成が均一なバンプを低コストで能率良く形成でき
る方法として知られている(特開昭60−240142
号公報)。この滴下法は、図5に示すように、ヒーター
11を備えた容器12内で半田13を溶融させ、この溶
融半田をピエゾ素子14による制御の下に容器の底に設
けたノズル15から滴下させ、回路基板17上に半田バ
ンプ16を形成するものである。
On the other hand, the dropping method is known as a method capable of efficiently forming bumps having a uniform composition at low cost by using molten solder (Japanese Patent Laid-Open No. 60-240142).
No.). In this dropping method, as shown in FIG. 5, the solder 13 is melted in a container 12 equipped with a heater 11, and this molten solder is dropped from a nozzle 15 provided on the bottom of the container under the control of a piezo element 14. The solder bumps 16 are formed on the circuit board 17.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、滴下法
にあっては、溶融半田滴をノズルから回路基板上へ落下
させるため、この溶融半田滴に加速度が付加され、回路
基板上に形成されるバンプが平らな形状となってしま
う。このため接続に必要な高さを確保しようとすると、
その体積が大きくなってしまうため、電極端子の面積を
小さくできず、回路を高密度化することが難しかった。
However, in the dropping method, since the molten solder droplets are dropped from the nozzle onto the circuit board, acceleration is applied to the molten solder droplets and bumps are formed on the circuit board. Becomes a flat shape. Therefore, if you try to secure the height required for connection,
Since the volume becomes large, the area of the electrode terminal cannot be reduced, and it is difficult to increase the density of the circuit.

【0007】[0007]

【課題を解決するための手段】上記課題を解決するため
に、本発明の半田バンプの形成方法は、半導体チップの
電極端子に対向する位置に、それぞれ電極端子が形成さ
れた回路基板の上面に、前記回路基板の電極端子ごとに
分離され、かつその電極端子とその周りの回路基板とが
露出する開口部を有するソルダレジストを形成する工程
と、前記開口部内にクリーム半田を埋め込む工程と、前
記埋め込まれたクリーム半田を溶融した後、固化するこ
とにより、その表面張力によって前記電極端子上にのみ
半田バンプを形成する工程とからなるものである。
In order to solve the above-mentioned problems, a method of forming a solder bump according to the present invention includes a method of forming a solder bump on a top surface of a circuit board having electrode terminals formed at positions facing the electrode terminals of a semiconductor chip. A step of forming a solder resist that has an opening that is separated for each electrode terminal of the circuit board and that exposes the electrode terminal and the circuit board around the electrode terminal; and a step of embedding cream solder in the opening, After the embedded cream solder is melted and then solidified, the solder bumps are formed only on the electrode terminals by the surface tension of the melted cream solder.

【0008】上記方法により、十分な高さを有しつつ微
小で、かつ組成及び形状が均一なバンプを、低コストで
能率よく形成することを提供する。
By the above method, it is possible to efficiently form minute bumps having a sufficient height and having a uniform composition and shape at low cost.

【0009】[0009]

【発明の実施の形態】本発明の請求項1に記載の発明
は、半導体チップの電極端子に対向する位置に、それぞ
れ電極端子が形成された回路基板の上面に、前記回路基
板の電極端子ごとに分離され、かつその電極端子とその
周りの回路基板とが露出する開口部を有するソルダレジ
ストを形成する工程と、前記開口部内にクリーム半田を
埋め込む工程と、前記埋め込まれたクリーム半田を溶融
した後、固化することにより、その表面張力によって前
記電極端子上にのみ半田バンプを形成する工程とからな
るものであり、上記方法によれば、ソルダーレジストの
開口部がその内部の電極端子より大きく、溶融した半田
は自らの表面張力により、電極端子上に突起状のバンプ
が得られ、また供給された半田量は、開口部の大きさに
より制御されるのでばらつきがなく、組成や形状が均一
な半田バンプを低コストで能率良く形成でき、さらに隣
接バンプ間でブリッジすることもない。
BEST MODE FOR CARRYING OUT THE INVENTION The invention according to claim 1 of the present invention includes an electrode terminal of a semiconductor chip, an electrode terminal formed on the upper surface of the circuit board, and an electrode terminal of the circuit board. And a step of forming a solder resist having an opening for exposing the electrode terminal and the circuit board around it, a step of embedding cream solder in the opening, and the embedded cream solder melted. After that, by solidifying, it comprises a step of forming solder bumps only on the electrode terminals due to its surface tension, and according to the above method, the opening of the solder resist is larger than the electrode terminals inside thereof, The molten solder produces bumps on the electrode terminals due to its surface tension, and the amount of solder supplied is controlled by the size of the opening. Variability without, uniform solder bumps composition and shape can efficiently formed at low cost, nor for bridging between further adjacent bumps.

【0010】以下に、本発明の請求項1に記載された発
明の実施の形態について、図面を用いて説明する。図1
は本発明の一実施の形態における回路基板の平面図であ
り、図2はその回路基板の電極端子上に半田バンプを形
成した後の断面図であり、図2(a)は図1におけるA
−A断面図を、図2(b)は図1におけるB−B断面図
を示している。
An embodiment of the invention described in claim 1 of the present invention will be described below with reference to the drawings. FIG.
FIG. 2 is a plan view of a circuit board according to an embodiment of the present invention, FIG. 2 is a cross-sectional view after forming a solder bump on an electrode terminal of the circuit board, and FIG.
-A sectional drawing and FIG.2 (b) have shown BB sectional drawing in FIG.

【0011】図1、2において、1はソルダーレジスト
の開口部、2は電極端子、3は半田バンプ、4はソルダ
ーレジスト、5は回路基板である。ここで半田バンプの
形成工程及びフリップチップ実装工程を図4に示した図
1におけるB−B方向の断面図に基づいて具体的に説明
する。
1 and 2, 1 is an opening of a solder resist, 2 is an electrode terminal, 3 is a solder bump, 4 is a solder resist, and 5 is a circuit board. Here, the solder bump forming step and the flip chip mounting step will be specifically described based on the cross-sectional view taken along the line BB in FIG. 1 shown in FIG.

【0012】125(W)×170(D)×50(T)
μmの寸法で形成したソルダーレジスト4の開口部1内
に、80(D)×15(T)μmの電極端子2をソルダ
ーレジスト4の2辺と接しないように形成した、ガラス
エポキシからなる回路基板5を準備する(図4
(a))。次いで、回路基板5上に、クリーム半田7を
スキージ6を摺動させることにより、ソルダーレジスト
4の開口部1内に埋め込む(図4(a),(b))。今
回使用したクリーム半田7は、平均粒径30μmφ以下
の63Sn/37Pb共晶半田を用いた。
125 (W) × 170 (D) × 50 (T)
A circuit made of glass epoxy, in which the electrode terminal 2 of 80 (D) × 15 (T) μm is formed so as not to contact the two sides of the solder resist 4 in the opening 1 of the solder resist 4 formed with the dimension of μm. A substrate 5 is prepared (Fig. 4
(A)). Next, the cream solder 7 is embedded on the circuit board 5 by sliding the squeegee 6 into the opening 1 of the solder resist 4 (FIGS. 4A and 4B). The cream solder 7 used this time was 63Sn / 37Pb eutectic solder having an average particle diameter of 30 μmφ or less.

【0013】次いで窒素雰囲気中、赤外線リフロー炉で
回路基板5を加熱することにより、溶融した半田は自ら
の表面張力によって電極端子2上に突起電極の形状を形
成し、そして冷却する事により固化し半田バンプ3が得
られる(図4(c))。この場合、得られた半田バンプ
3は、ソルダーレジスト4の開口部1内で電極端子2に
追従するように半円筒形状を有し、半田バンプ3の頂部
はソルダーレジスト4より15μm高いものが得られ
た。
Next, by heating the circuit board 5 in an infrared reflow furnace in a nitrogen atmosphere, the melted solder forms the shape of a protruding electrode on the electrode terminal 2 by its own surface tension, and is solidified by cooling. Solder bumps 3 are obtained (FIG. 4 (c)). In this case, the obtained solder bump 3 has a semi-cylindrical shape so as to follow the electrode terminal 2 in the opening 1 of the solder resist 4, and the top of the solder bump 3 is higher than the solder resist 4 by 15 μm. Was given.

【0014】次いで図4(d)に示すように、半導体チ
ップ8の電極9と回路基板5上に形成された半田バンプ
3とを位置合わせし、フェースダウンにて実装すること
により、フリップチップ実装体を得ることができる。
Next, as shown in FIG. 4D, the electrodes 9 of the semiconductor chip 8 and the solder bumps 3 formed on the circuit board 5 are aligned with each other and mounted face down to perform flip chip mounting. You can get the body.

【0015】また図3は本発明の他の実施の形態おける
回路基板の平面図であり、図3において、1はソルダー
レジストの開口部、2は電極端子、4はソルダーレジス
ト、5は回路基板である。この実施の形態においては、
上記と同様の工程で半田バンプを形成できるが、電極端
子2の面積が小さく、しかもソルダーレジスト4と離間
しているため、上述の実施の形態に比べ半田バンプ3を
より高く形成することができるものである。
FIG. 3 is a plan view of a circuit board according to another embodiment of the present invention. In FIG. 3, 1 is an opening of a solder resist, 2 is an electrode terminal, 4 is a solder resist, and 5 is a circuit board. Is. In this embodiment,
Although the solder bumps can be formed by the same process as the above, the solder bumps 3 can be formed higher than the above-described embodiment because the area of the electrode terminals 2 is small and is separated from the solder resist 4. It is a thing.

【0016】なお上述の実施の形態においては、半田バ
ンプ形成に63Sn/37Pb共晶クリーム半田を用い
たがこの組成に限るわけでなく、選択肢が非常に広範囲
にわたっている。さらに本実施の形態では、半導体チッ
プ8上の電極9は突起状を有しているが、突起状でなく
ても問題はない。
In the above-described embodiment, 63Sn / 37Pb eutectic cream solder is used for forming the solder bump, but the composition is not limited to this composition and the options are extremely wide. Furthermore, in the present embodiment, the electrode 9 on the semiconductor chip 8 has a projection shape, but it does not matter if it is not a projection shape.

【0017】[0017]

【発明の効果】以上のように本発明によれば、特別な装
置の必要もなく、回路基板の電極端子上に組成が均一で
十分な高さを有し、しかもきわめて精度の良い微小な半
田バンプを低コストにして能率的に形成することができ
る。そして、このように形成された半田バンプは、フリ
ップチップ実装のボンディングに適した形状であり、さ
らに、ソリ・ウネリが大きいためフリップチップ実装が
困難であったガラスエポキシ基板に対しても、半田バン
プ自身の高さ分だけフリップチップ実装に対する公差が
緩くなり実装歩留まりが向上し、また、半導体チップと
回路基板とのギャップが高くなるため耐ヒートサイクル
性を向上することができる。
As described above, according to the present invention, there is no need for a special device, and the composition is uniform on the electrode terminals of the circuit board and has a sufficient height. The bumps can be formed at low cost and efficiently. The solder bumps formed in this way have a shape suitable for flip-chip mounting bonding, and furthermore, solder bumps can be applied even to glass epoxy substrates where flip-chip mounting was difficult due to the large warp and swell. The tolerance for flip-chip mounting is loosened by the height of itself, the mounting yield is improved, and the heat cycle resistance can be improved because the gap between the semiconductor chip and the circuit board is increased.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半田バンプの形成方法の一実施の形態
による回路基板の平面図
FIG. 1 is a plan view of a circuit board according to an embodiment of a solder bump forming method of the invention.

【図2】同回路基板の断面図FIG. 2 is a sectional view of the circuit board.

【図3】本発明の他の実施の形態による回路基板の平面
FIG. 3 is a plan view of a circuit board according to another embodiment of the present invention.

【図4】本発明の半田バンプの形成方法における一実施
の形態を示す工程断面図
FIG. 4 is a process sectional view showing an embodiment of a method for forming a solder bump according to the present invention.

【図5】従来のバンプ形成装置を示す断面図FIG. 5 is a sectional view showing a conventional bump forming apparatus.

【符号の説明】[Explanation of symbols]

1 ソルダーレジストの開口部 2 電極端子 3 半田バンプ 4 ソルダーレジスト 5 回路基板 6 スキージ 7 クリーム半田 8 半導体チップ 9 電極 1 Solder Resist Opening 2 Electrode Terminal 3 Solder Bump 4 Solder Resist 5 Circuit Board 6 Squeegee 7 Cream Solder 8 Semiconductor Chip 9 Electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体チップの電極端子に対向する位置
に、それぞれ電極端子が形成された回路基板の上面に、
前記回路基板の電極端子ごとに分離され、かつその電極
端子とその周りの回路基板とが露出する開口部を有する
ソルダレジストを形成する工程と、 前記開口部内にクリーム半田を埋め込む工程と、 前記埋め込まれたクリーム半田を溶融した後、固化する
ことにより、その表面張力によって前記電極端子上にの
み半田バンプを形成する工程とからなる半田バンプの形
成方法。
1. An upper surface of a circuit board having electrode terminals formed at positions facing the electrode terminals of a semiconductor chip, respectively.
A step of forming a solder resist which is separated for each electrode terminal of the circuit board and has an opening exposing the electrode terminal and a circuit board around the electrode terminal; a step of embedding cream solder in the opening; A method of forming solder bumps, which comprises a step of forming solder bumps only on the electrode terminals by melting the solidified cream solder and then solidifying the cream solder.
JP7292399A 1995-11-10 1995-11-10 Method of forming solder bump Pending JPH09135073A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7292399A JPH09135073A (en) 1995-11-10 1995-11-10 Method of forming solder bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7292399A JPH09135073A (en) 1995-11-10 1995-11-10 Method of forming solder bump

Publications (1)

Publication Number Publication Date
JPH09135073A true JPH09135073A (en) 1997-05-20

Family

ID=17781288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7292399A Pending JPH09135073A (en) 1995-11-10 1995-11-10 Method of forming solder bump

Country Status (1)

Country Link
JP (1) JPH09135073A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007294954A (en) * 2006-04-21 2007-11-08 Internatl Business Mach Corp <Ibm> Filling technology of conductive bonding material
KR20160113692A (en) * 2014-03-28 2016-09-30 인텔 코포레이션 Method and process for emib chip interconnections

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007294954A (en) * 2006-04-21 2007-11-08 Internatl Business Mach Corp <Ibm> Filling technology of conductive bonding material
KR20160113692A (en) * 2014-03-28 2016-09-30 인텔 코포레이션 Method and process for emib chip interconnections
JP2017511603A (en) * 2014-03-28 2017-04-20 インテル コーポレイション EMIB chip interconnection

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