TWI412111B - Electrical connecting structure of printed circuit board and printed circuit board device - Google Patents

Abstract

Disclosed is an electrical connecting structure of printed circuit boards, characterized by forming a plurality of electrical connecting pads each having an electrical connecting pad formed thereon; forming a metal buffer layer on each electrical connecting pad of the electrical connecting structure; and forming a plurality of protrusive pillars on each metal buffer layer, thereby providing a buffering effect for allowing deviation of the substrate to release stresses in the reflow process and overcoming the defects of generated stresses caused by deviation of the protrusive pillars. The invention further provides a printed circuit board device.

Description

Electrical connection structure of circuit board and circuit board device

The present invention relates to a semiconductor device, and more particularly to an electrical connection structure of a circuit board and a circuit board device.

With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional, high-performance research and development. At present, a package substrate for carrying a semiconductor wafer includes a wire-bonded package substrate, a chip-scale package (CSP) substrate, and a flip-chip substrate (FCBGA); and is required for operation of a microprocessor, a wafer set, and a graphics chip. Packaged substrates with wiring also need to improve the quality of the transmitted chip signals, improve the bandwidth, control impedance and other functions in order to cope with the development of high I / O number of packages.

In the current packaging technology, a semiconductor wafer is electrically connected to a package substrate, and an electronic pad is disposed on a surface of the semiconductor integrated circuit (IC) wafer, and the package substrate has corresponding electrical properties. Contact pads, and conductive bumps, other conductive adhesive materials or gold wires may be appropriately disposed between the semiconductor wafer and the package substrate to electrically connect the semiconductor wafer to the package substrate.

1A is a schematic cross-sectional view of a conventional flip chip package structure. As shown, a package substrate 10 is provided. The package substrate 10 has a first surface 10a and a second surface 10b. A plurality of first electrical contact pads 101 are disposed on the surface 10a, and a plurality of second electrical contact pads 102 are disposed on the second surface 10b, and the semiconductor wafer 11 is mounted on the second surface 10b. A solder bump 12 is formed on the second electrical contact pad 102, and a surface of the semiconductor wafer 11 has a plurality of electrode pads 110 opposite to the solder bumps 12, and conductive bumps 13 are formed on each of the electrode pads 110. The conductive bumps 13 of the semiconductor wafer 11 are electrically connected to the solder bumps 12 of the package substrate 10, and the underfill material 14 is filled between the semiconductor wafer 11 and the package substrate 10 to form a package structure. The first electrical contact pads 101 of the package structure 1 are correspondingly connected to a printed circuit board (PCB) 2, and one surface of the circuit board 2 has a plurality of corresponding first electrical contacts. The third electrical contact pad 21 of the pad 101 is formed on each of the third electrical contact pads 21 The solder balls 15 are electrically connected to the first electrical contact pads 101 of the package structure 1 to electrically connect the package structure 1 to the circuit board 2.

However, the solder balls 15 of the circuit board 2 are formed on the third electrical contact pads 21 of the high-density wiring and fine pitch layout, which will cause the pitch between the solder balls 15 to be too small, and when the solder balls are After the first electrical contact pads 101 of the package structure 1 are connected to each other to form an electrical connection, the solder balls 15 are easily bridged to cause a short circuit.

In order to avoid the above problem, the industry proposes a package substrate structure. Referring to FIG. 1B, the first electrical contact pads 101 of the conventional package structure 1 are connected to the circuit having the third electrical contact pads 21. The second conductive contact pad 21 is provided with a stud 16 , and a solder material 17 is formed on the stud 16 , so that the solder materials 17 are electrically connected to the package structure 1 . Each of the first electrical contact pads 101 is electrically connected to the circuit board 2 .

In the above two conventional techniques, the solder balls 15 or the studs 16 having the solder material 17 are correspondingly disposed on the first electrical contact pads 101 of each of the package structures 1, when the solder balls 15 have When the studs 16 of the solder material 17 are connected to the first electrical contact pads 101 of the package structure 1 , the first electrical contact pads 101 on the package structure 1 are closely arranged and formed on the first electrical property. The solder mask of the contact pad 101 has a narrow opening, and the center of the plurality of solder balls 15 or the pillars 16 having the solder material 17 cannot be completely connected to the central portion of the first electrical contact pad 101 of the package structure 1. In some cases of offset, after the electrical connection is achieved through the reflow process, the solder balls 15 or the studs 16 having the solder material 17 are not completely accurately placed in the center of the first electrical contact pad 101. The stress between the solder balls 15 or the pillars 16 and the third electrical contact pads 21 may be generated, which may cause the solder balls 15 and the first electrical contact pads 101 or the pillars 16 to Between the first electrical contact pads 101, or between the solder balls 15 and the third electrical contact pads 21, or the studs 1 The interface between the 6 and the third electrical contact pads 21 is prone to breakage and peeling, thus affecting the electrical connection.

Therefore, how to provide a circuit board device to avoid the prior art, in the fine pitch layout of high-density wiring, because the solder ball pitch on the electrical contact pads of the circuit board is too small, it is easy to form a bridge between the solder balls. Resulting in a short circuit, and the stress generated by the solder ball or the metal stud due to failure to be completely accurately placed at the center of the electrical contact pad of the package structure, resulting in the occurrence of the solder ball or the metal stud and the electrical contact pad The lack of fracture and peeling has become an urgent issue to be overcome.

In view of the above-mentioned deficiencies of the prior art, the main object of the present invention is to provide an electrical connection structure and a circuit board device for a circuit board, which can avoid the occurrence of eccentric stress between the electrical connection structures in the reflow process and avoid When the pitch of the solder balls is too small and the solder balls are too large, the problem of short-circuiting between the solder balls is caused after the reflow process.

To achieve the above and other objects, the present invention provides an electrical connection structure for a circuit board, wherein the circuit board is provided with a plurality of electrical contact pads, and the electrical contact structure is disposed on the electrical contact pad. The electrical connection structure is electrically connected to the semiconductor component, the electrical connection structure includes: a plurality of metal buffer layers correspondingly disposed on the respective electrical contact pads, and the material forming the metal buffer layer is a solder material; A plurality of studs are disposed on each of the metal buffer layers, and a melting point of the studs is higher than the metal buffer layer.

The present invention provides a circuit board device comprising: a circuit board having a plurality of electrical contact pads on at least one surface thereof; a plurality of metal buffer layers correspondingly disposed on each of the electrical contact pads, and forming the metal buffer The material of the layer is a solder material; the plurality of studs are correspondingly disposed on each of the metal buffer layers, and the melting point of the stud is higher than the metal buffer layer; and the semiconductor component is electrically connected to the studs.

The semiconductor device is a semiconductor wafer or a package structure, and the semiconductor device has a plurality of electrode pads corresponding to the pillars, and solder bumps are formed on the electrode pads. .

According to the electrical connection structure and the circuit board device of the above circuit board, the material of the protruding pillar is one of a group consisting of aluminum (Al), copper (Cu) and nickel (Ni).

According to the above structure, a barrier layer is formed between the metal buffer layer and the electrical contact pad, and the material forming the barrier layer is nickel (Ni).

Further, according to the above, a solder material may be formed on the protruding pillar; or a surface treatment layer may be formed on the exposed surface of the pillar, and the material forming the surface treatment layer is electroplated nickel/gold, electroless nickel/gold plating Nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG), electroless tin plating (Immersion Tin) or electroplated tin.

Forming an insulating protective layer on the first surface of the circuit board to expose the protruding pillars; or forming the insulating protective layer on the side surfaces of the protruding pillars and exposing the top surfaces of the protruding pillars .

In addition, as described above, a solder material is formed on the top surface of the stud.

The electrical connection structure and the circuit board device of the circuit board of the invention mainly comprise a metal buffer layer of a low melting point metal formed on the electrical contact pad of the circuit board, and a pillar of a high melting point metal is formed on the metal buffer layer to The metal buffer layer is first melted in the reflow process compared to the protrusions, so that the protrusions can provide elastic deflection by the first molten metal buffer layer in the reflow process to make the protrusions The pillars avoid stress caused by the offset during the cooling process of the metal buffer layers, and the pillars are not spherically formed after reflowing, and the distance between the solder balls and the solder balls is caused. The problem of bridging shorts is reduced, and the loss caused by conventional knowledge can be avoided.

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure herein.

Please refer to FIG. 2A to FIG. 7B, which are schematic diagrams showing the electrical connection structure of the circuit board of the present invention.

[First Embodiment]

Referring to FIG. 2A, the electrical connection structure of the circuit board of the present invention includes a circuit board 31, a plurality of metal buffer layers 32, and a plurality of protrusions 33.

At least one surface of the circuit board 31 is provided with a plurality of electrical contact pads 311 having a plurality of conductive lines and conductive vias or conductive blind holes (not shown) electrically connected thereto. There are many process technologies for forming conductive lines, conductive vias and conductive blind vias on the circuit board. However, it is a well-known process technology in the industry, which is not a technical feature of the present invention and therefore will not be further described.

The plurality of metal buffer layers 32 are correspondingly disposed on the respective electrical contact pads 311, and the material forming the metal buffer layer 32 is a solder material, and the material forming the solder material is tin (Sn)/ Silver (Ag) / copper (Cu), tin (Sn) / copper (Cu), tin (Sn) / silver (Ag), tin (Sn) / zinc (Zn), or tin (Sn) / indium (In) .

The plurality of studs 33 are correspondingly disposed on the metal buffer layer 32, and the melting point of the stud 33 is higher than the metal buffer layer, and the material forming the stud 33 is a high melting point metal material. One of a group consisting of aluminum (Al), copper (Cu), and nickel (Ni).

Referring to FIG. 2B , a barrier layer 34 is formed between the metal buffer layer 32 and the electrical contact pads 311 according to the above structure. The material forming the barrier layer 34 is nickel (Ni).

[Second embodiment]

Referring to FIGS. 3A and 3B, the difference from the previous embodiment is that a solder material 35 is formed on the stud 33.

[Third embodiment]

Referring to FIGS. 4A and 4B , the difference from the foregoing embodiment is that a surface treatment layer 36 is formed on the exposed surface of the stud 33 , and the material forming the surface treatment layer 36 is electroplated nickel/gold, electroless nickel/gold. Nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG), electroless tin plating (Immersion Tin) or electroplated tin.

[Fourth embodiment]

Referring to FIGS. 5A and 5B, the difference from the foregoing embodiment is that an insulating protective layer 37 is formed on the first surface 31a of the circuit board 31, and the studs 33 are exposed.

[Fifth Embodiment]

Referring to FIGS. 6A and 6B , the difference from the fourth embodiment is that the insulating protection layer 37 is formed on the side of the protrusions 33 and exposes the top surfaces of the protrusions 33 .

[Sixth embodiment]

Referring to FIGS. 7A and 7B, the difference from the foregoing fifth embodiment is that the top surface of the stud 33 forms a solder material 35.

The electrical connection structure of the circuit board of the present invention is formed on the electrical contact pads of the circuit board to form a metal buffer layer, and a pillar is formed on the metal buffer layer, and the metal buffer layer of the low melting point metal is used. The pillars of the high melting point metal are first melted in the reflow process, so that the pillars can be elastically deflected by the first molten metal buffer layer in the reflow process, so that the pillars are During the cooling process of the metal buffer layer, the stress caused by the offset is avoided, and the bumps are not spherically formed after the solder balls are reflowed, and the distance between the solder balls and the solder balls is reduced to cause bridging. The problem of short circuit can avoid the loss of bias stress between the electrical connection structures in the reflow process.

Referring to FIG. 8, the present invention further provides a circuit board device including a circuit board 31, a plurality of metal buffer layers 32, a plurality of bumps 33, and a semiconductor component 38.

The circuit board 31 is provided with a plurality of electrical contact pads 311 on at least one surface thereof.

The plurality of metal buffer layers 32 are respectively disposed on the respective electrical contact pads 311, and the material forming the metal buffer layer 32 is a low melting point metal, and the material of the low melting point metal layer is tin (Sn). One of the groups of lead (Pb).

The plurality of studs 33 are correspondingly disposed on each of the metal buffer layers 32. The material forming the studs 33 is a high melting point metal, and the material of the high melting point metal is aluminum (Al) or copper (Cu). One of the groups consisting of nickel (Ni).

The semiconductor component 38 is electrically connected to the bumps 33. The semiconductor component 38 is a semiconductor wafer or a package structure, and the semiconductor component 38 has a plurality of electrode pads 381 corresponding to the pillars 33. A solder bump 382 is formed on the pad 381.

According to the above circuit board device, the barrier layer 34 is formed between the metal buffer layer 32 and the electrical contact pad 311, and the material forming the barrier layer 34 is nickel (Ni), such as the second Figure 2B shows.

In addition, as described above, the composite material may include a solder material 35 formed on the stud 33 as shown in FIGS. 3A and 3B, or a surface treatment layer 36 formed on the exposed surface of the stud 33 to form the surface treatment layer. The materials of 36 are electroplated nickel/gold, electroless nickel/gold, nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG), electroless tin plating (Immersion Tin) or electroplated tin, as shown in Figures 4A and 4B. Shown.

As described above, an insulating protective layer 37 is formed on the circuit board 31, and the insulating protective layer 37 exposes the studs 33 as shown in FIGS. 5A and 5B; or the insulating protective layer 37 is formed on The protrusions 33 are laterally disposed and expose the top surfaces of the protrusions 33 as shown in FIGS. 6A and 6B.

As described above, the solder material 35 is formed on the top surface of the stud 33 as shown in Figs. 7A and 7B.

The circuit board device of the present invention is characterized in that a metal buffer layer of a low melting point metal is formed on an electrical contact pad on the surface of the circuit board, and a pillar of a high melting point metal is formed on the metal buffer layer to pass the metal buffer layer. And melting the pillars in the reflow process, so that the pillars can provide elastic deflection in the reflow process by the first molten metal buffer layer, so that the pillars are buffered in the metal During the cooling process of the layer, the stress caused by the offset is avoided, and the pillars are not spherically formed after reflowing, and the distance between the solder balls and the solder balls is reduced to cause a bridge short circuit. The problem, in turn, avoids the lack of biasing stress between the electrical connection structures in the reflow process.

The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.

1. . . Package structure

10. . . Package substrate

10a, 31a. . . First surface

10b. . . Second surface

101. . . First electrical contact pad

102. . . Second electrical contact pad

11. . . Semiconductor wafer

110, 381. . . Electrode pad

12,382. . . Solder bump

13. . . Conductive bump

14. . . Bottom filling material

15. . . Solder balls

16, 33. . . Tab

17. . . Solder material

2, 31. . . Circuit board

twenty one. . . Third electrical contact pad

311. . . Electrical contact pad

32. . . Metal buffer layer

34. . . Barrier layer

35. . . Welding materials

36. . . Surface treatment layer

37. . . Insulating protective layer

38. . . Semiconductor component

1A and 1B are schematic cross-sectional views showing a conventional package substrate structure;

2A and 2B are cross-sectional views showing a first embodiment of the electrical connection structure of the circuit board of the present invention;

3A and 3B are cross-sectional views showing a second embodiment of the electrical connection structure of the circuit board of the present invention;

4A and 4B are cross-sectional views showing a third embodiment of the electrical connection structure of the circuit board of the present invention;

5A and 5B are cross-sectional views showing a fourth embodiment of the electrical connection structure of the circuit board of the present invention;

6A and 6B are cross-sectional views showing a fifth embodiment of the electrical connection structure of the circuit board of the present invention;

7A and 7B are cross-sectional views showing a sixth embodiment of the electrical connection structure of the circuit board of the present invention;

Figure 8 is a cross-sectional view showing the circuit board assembly of the present invention.

31. . . Circuit board

311. . . Electrical contact pad

32. . . Metal buffer layer

33. . . Tab

Claims (24)

An electrical connection structure of a circuit board is provided with a plurality of electrical contact pads on the circuit board, and the electrical connection structure is disposed on the electrical contact pad, and the electrical connection structure is electrically connected to the semiconductor An element having a plurality of electrode pads, wherein the electrode pads are formed with solder bumps, the electrical connection structure comprising: a plurality of metal buffer layers correspondingly disposed on the respective electrical contact pads, and forming the metal buffer layer The material is a solder material; and the plurality of bumps are correspondingly disposed on the metal buffer layers, and the solder bumps are electrically connected to the electrode pads, and the pillars have a higher melting point than the metal buffer layer. The electrical connection structure of the circuit board of claim 1, wherein the semiconductor component is a semiconductor wafer or a package structure. The electrical connection structure of the circuit board of claim 1, wherein the material forming the solder material is a low melting point metal, and the material of the low melting point metal layer is tin (Sn) / silver (Ag) / copper (Cu), tin (Sn) / copper (Cu), tin (Sn) / silver (Ag), tin (Sn) / zinc (Zn), or tin (Sn) / indium (In). The electrical connection structure of the circuit board of claim 1, wherein the material forming the protrusion is one of a group consisting of aluminum (Al), copper (Cu), and nickel (Ni). The electrical connection structure of the circuit board of claim 1 is further comprising a barrier layer formed between the metal buffer layer and the electrical contact pad. An electrical connection structure of a circuit board as claimed in claim 5, The material forming the barrier layer is nickel (Ni). For example, the electrical connection structure of the circuit board of claim 1 or 5, including the solder material, is formed on the protruding post. The electrical connection structure of the circuit board of claim 1 or 5, further comprising a surface treatment layer formed on the exposed surface of the protrusion. The electrical connection structure of the circuit board of claim 8 is characterized in that the material forming the surface treatment layer is electroplated nickel/gold, electroless nickel/gold, nickel immersion gold (ENIG), nickel palladium dip Gold (ENEPIG), electroless tin plating (Immersion Tin) or electroplated tin. The electrical connection structure of the circuit board of claim 1 or 5, further comprising an insulating protection layer formed on the circuit board and exposing the protrusions. The electrical connection structure of the circuit board of claim 1 or 5, further comprising an insulating protective layer formed on the circuit board and the side surfaces of the plurality of pillars, and exposing the top surfaces of the pillars. For example, the electrical connection structure of the circuit board of claim 11 includes a solder material formed on the top surface of the stud. A circuit board device comprising: a circuit board having a plurality of electrical contact pads on at least one surface thereof; a plurality of metal buffer layers corresponding to each of the electrical contact pads and forming a material layer of the metal buffer layer a solder material; a plurality of studs are correspondingly disposed on each of the metal buffer layers, and a melting point of the studs is higher than the metal buffer layer; The semiconductor component has a plurality of electrode pads corresponding to the pillars, and solder bumps are formed on the electrode pads to electrically connect the pillars. The circuit board device of claim 13, wherein the semiconductor component is a semiconductor wafer or a package structure. The circuit board device of claim 13, wherein the material for forming the solder material is tin (Sn) / silver (Ag) / copper (Cu), tin (Sn) / copper (Cu), tin (Sn ) / Silver (Ag), Tin (Sn) / Zinc (Zn), or Tin (Sn) / Indium (In). The circuit board device of claim 13, wherein the material forming the stud is one of a group consisting of aluminum (Al), copper (Cu), and nickel (Ni). The circuit board device of claim 13 further comprising a barrier layer formed between the metal buffer layer and the electrical contact pad. The circuit board device of claim 17, wherein the material forming the barrier layer is nickel (Ni). A circuit board device according to claim 13 or 17, further comprising a solder material formed on the stud. A circuit board device according to claim 13 or 17, further comprising a surface treatment layer formed on the exposed surface of the stud. The circuit board device of claim 20, wherein the material for forming the surface treatment layer is electroplated nickel/gold, electroless nickel/gold, nickel immersion gold (ENIG), and nickel-palladium immersion gold (ENEPIG). , electroless tin plating (Immersion Tin) or electroplating tin. Such as the circuit board device of the 13th or 17th patent application, including An insulating protective layer is formed on the first surface of the circuit board and exposes the studs. The circuit board device of claim 13 or 17, further comprising an insulating protective layer formed on the first surface of the circuit board and the side surfaces of the plurality of pillars, and exposing the top surfaces of the pillars. A circuit board device as claimed in claim 23, comprising a solder material formed on a top surface of the stud.